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ide: add IDE_HFLAG_ABUSE_SET_DMA_MODE host flag

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* Add IDE_HFLAG_ABUSE_SET_DMA_MODE host flag and use it to decide
  what to do with transfer modes < XFER_PIO_0 in ide_set_xfer_rate().

* Set IDE_HFLAG_ABUSE_SET_DMA_MODE in host drivers that need it
  (aec62xx, amd74xx, cs5520, cs5535, hpt34x, hpt366, pdc202xx_old,
  serverworks, tc86c001 and via82cxxx) and cleanup ->set_dma_mode
  methods in host drivers that don't (IDE core code guarantees that
  ->set_dma_mode will be called only for modes which are present
  in SWDMA/MWDMA/UDMA masks).

While at it:

* Add IDE_HFLAGS_HPT34X/HPT3XX/PDC202XX/SVWKS define in
  hpt34x/hpt366/pdc202xx_old/serverworks host driver.

There should be no functionality changes caused by this patch.

Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2008-01-25 22:17:18 +01:00
parent 428c6440ef
commit 4db90a1452
30 changed files with 120 additions and 224 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/ide/arm/icside.c
View File

@ -272,8 +272,6 @@ static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
case XFER_SW_DMA_0: case XFER_SW_DMA_0:
cycle_time = 480; cycle_time = 480;
break; break;
default:
return;
} }
/* /*

2
drivers/ide/cris/ide-cris.c
View File

@ -747,8 +747,6 @@ static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
strobe = ATA_DMA2_STROBE; strobe = ATA_DMA2_STROBE;
hold = ATA_DMA2_HOLD; hold = ATA_DMA2_HOLD;
break; break;
default:
return;
} }
if (speed >= XFER_UDMA_0) if (speed >= XFER_UDMA_0)

6
drivers/ide/ide-lib.c
View File

@ -441,6 +441,12 @@ int ide_set_xfer_rate(ide_drive_t *drive, u8 rate)
* case could happen iff the transfer mode has already been set on * case could happen iff the transfer mode has already been set on
* the device by ide-proc.c::set_xfer_rate()). * the device by ide-proc.c::set_xfer_rate()).
*/ */
if (rate < XFER_PIO_0) {
if (hwif->host_flags & IDE_HFLAG_ABUSE_SET_DMA_MODE)
return ide_set_dma_mode(drive, rate);
else
return ide_config_drive_speed(drive, rate);
}
return ide_set_dma_mode(drive, rate); return ide_set_dma_mode(drive, rate);
} }

2
drivers/ide/mips/au1xxx-ide.c
View File

@ -198,8 +198,6 @@ static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
break; break;
#endif #endif
default:
return;
} }
au_writel(mem_sttime,MEM_STTIME2); au_writel(mem_sttime,MEM_STTIME2);

13
drivers/ide/pci/aec62xx.c
View File

@ -202,6 +202,7 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_SERIALIZE | .host_flags = IDE_HFLAG_SERIALIZE |
IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_ATAPI_DMA |
IDE_HFLAG_ABUSE_SET_DMA_MODE |
IDE_HFLAG_OFF_BOARD, IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
@ -211,6 +212,7 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.init_chipset = init_chipset_aec62xx, .init_chipset = init_chipset_aec62xx,
.init_hwif = init_hwif_aec62xx, .init_hwif = init_hwif_aec62xx,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
IDE_HFLAG_ABUSE_SET_DMA_MODE |
IDE_HFLAG_OFF_BOARD, IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
@ -220,7 +222,8 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.init_chipset = init_chipset_aec62xx, .init_chipset = init_chipset_aec62xx,
.init_hwif = init_hwif_aec62xx, .init_hwif = init_hwif_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_ATAPI_DMA, .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
IDE_HFLAG_ABUSE_SET_DMA_MODE,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4, .udma_mask = ATA_UDMA4,
@ -228,7 +231,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.name = "AEC6280", .name = "AEC6280",
.init_chipset = init_chipset_aec62xx, .init_chipset = init_chipset_aec62xx,
.init_hwif = init_hwif_aec62xx, .init_hwif = init_hwif_aec62xx,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
IDE_HFLAG_ABUSE_SET_DMA_MODE |
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,
@ -237,7 +242,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
.init_chipset = init_chipset_aec62xx, .init_chipset = init_chipset_aec62xx,
.init_hwif = init_hwif_aec62xx, .init_hwif = init_hwif_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
IDE_HFLAG_ABUSE_SET_DMA_MODE |
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,

3
drivers/ide/pci/alim15x3.c
View File

@ -402,9 +402,6 @@ static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
u8 tmpbyte = 0x00; u8 tmpbyte = 0x00;
int m5229_udma = (hwif->channel) ? 0x57 : 0x56; int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
if (speed < XFER_PIO_0)
return;
if (speed == XFER_UDMA_6) if (speed == XFER_UDMA_6)
speed1 = 0x47; speed1 = 0x47;

1
drivers/ide/pci/amd74xx.c
View File

@ -266,6 +266,7 @@ static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
#define IDE_HFLAGS_AMD \ #define IDE_HFLAGS_AMD \
(IDE_HFLAG_PIO_NO_BLACKLIST | \ (IDE_HFLAG_PIO_NO_BLACKLIST | \
IDE_HFLAG_PIO_NO_DOWNGRADE | \ IDE_HFLAG_PIO_NO_DOWNGRADE | \
IDE_HFLAG_ABUSE_SET_DMA_MODE | \
IDE_HFLAG_POST_SET_MODE | \ IDE_HFLAG_POST_SET_MODE | \
IDE_HFLAG_IO_32BIT | \ IDE_HFLAG_IO_32BIT | \
IDE_HFLAG_UNMASK_IRQS | \ IDE_HFLAG_UNMASK_IRQS | \

3
drivers/ide/pci/atiixp.c
View File

@ -133,9 +133,6 @@ static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
u32 tmp32; u32 tmp32;
u16 tmp16; u16 tmp16;
if (speed < XFER_MW_DMA_0)
return;
spin_lock_irqsave(&atiixp_lock, flags); spin_lock_irqsave(&atiixp_lock, flags);
save_mdma_mode[drive->dn] = 0; save_mdma_mode[drive->dn] = 0;

2
drivers/ide/pci/cmd64x.c
View File

@ -322,8 +322,6 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
case XFER_MW_DMA_0: case XFER_MW_DMA_0:
program_cycle_times(drive, 480, 215); program_cycle_times(drive, 480, 215);
break; break;
default:
return;
} }
if (speed >= XFER_SW_DMA_0) if (speed >= XFER_SW_DMA_0)

1
drivers/ide/pci/cs5520.c
View File

@ -137,6 +137,7 @@ static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
IDE_HFLAG_CS5520 | \ IDE_HFLAG_CS5520 | \
IDE_HFLAG_VDMA | \ IDE_HFLAG_VDMA | \
IDE_HFLAG_NO_ATAPI_DMA | \ IDE_HFLAG_NO_ATAPI_DMA | \
IDE_HFLAG_ABUSE_SET_DMA_MODE |\
IDE_HFLAG_BOOTABLE, \ IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO4, \ .pio_mask = ATA_PIO4, \
} }

2
drivers/ide/pci/cs5530.c
View File

@ -116,8 +116,6 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
case XFER_MW_DMA_0: timings = 0x00077771; break; case XFER_MW_DMA_0: timings = 0x00077771; break;
case XFER_MW_DMA_1: timings = 0x00012121; break; case XFER_MW_DMA_1: timings = 0x00012121; break;
case XFER_MW_DMA_2: timings = 0x00002020; break; case XFER_MW_DMA_2: timings = 0x00002020; break;
default:
return;
} }
basereg = CS5530_BASEREG(drive->hwif); basereg = CS5530_BASEREG(drive->hwif);
reg = inl(basereg + 4); /* get drive0 config register */ reg = inl(basereg + 4); /* get drive0 config register */

2
drivers/ide/pci/cs5535.c
View File

@ -190,7 +190,7 @@ static const struct ide_port_info cs5535_chipset __devinitdata = {
.name = "CS5535", .name = "CS5535",
.init_hwif = init_hwif_cs5535, .init_hwif = init_hwif_cs5535,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_BOOTABLE, IDE_HFLAG_ABUSE_SET_DMA_MODE | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4, .udma_mask = ATA_UDMA4,

12
drivers/ide/pci/hpt34x.c
View File

@ -129,14 +129,18 @@ static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
hwif->set_dma_mode = &hpt34x_set_mode; hwif->set_dma_mode = &hpt34x_set_mode;
} }
#define IDE_HFLAGS_HPT34X \
(IDE_HFLAG_NO_ATAPI_DMA | \
IDE_HFLAG_ABUSE_SET_DMA_MODE | \
IDE_HFLAG_NO_AUTODMA)
static const struct ide_port_info hpt34x_chipsets[] __devinitdata = { static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
{ /* 0 */ { /* 0 */
.name = "HPT343", .name = "HPT343",
.init_chipset = init_chipset_hpt34x, .init_chipset = init_chipset_hpt34x,
.init_hwif = init_hwif_hpt34x, .init_hwif = init_hwif_hpt34x,
.extra = 16, .extra = 16,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | .host_flags = IDE_HFLAGS_HPT34X,
IDE_HFLAG_NO_AUTODMA,
.pio_mask = ATA_PIO5, .pio_mask = ATA_PIO5,
}, },
{ /* 1 */ { /* 1 */
@ -144,9 +148,7 @@ static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
.init_chipset = init_chipset_hpt34x, .init_chipset = init_chipset_hpt34x,
.init_hwif = init_hwif_hpt34x, .init_hwif = init_hwif_hpt34x,
.extra = 16, .extra = 16,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | .host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
IDE_HFLAG_NO_AUTODMA |
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO5, .pio_mask = ATA_PIO5,
#ifdef CONFIG_HPT34X_AUTODMA #ifdef CONFIG_HPT34X_AUTODMA
.swdma_mask = ATA_SWDMA2, .swdma_mask = ATA_SWDMA2,

19
drivers/ide/pci/hpt366.c
View File

@ -1461,6 +1461,11 @@ static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
return 0; return 0;
} }
#define IDE_HFLAGS_HPT3XX \
(IDE_HFLAG_NO_ATAPI_DMA | \
IDE_HFLAG_ABUSE_SET_DMA_MODE | \
IDE_HFLAG_OFF_BOARD)
static const struct ide_port_info hpt366_chipsets[] __devinitdata = { static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
{ /* 0 */ { /* 0 */
.name = "HPT36x", .name = "HPT36x",
@ -1475,9 +1480,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
*/ */
.enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_SINGLE | .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
IDE_HFLAG_NO_ATAPI_DMA |
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
},{ /* 1 */ },{ /* 1 */
@ -1487,7 +1490,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.init_dma = init_dma_hpt366, .init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
},{ /* 2 */ },{ /* 2 */
@ -1497,7 +1500,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.init_dma = init_dma_hpt366, .init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
},{ /* 3 */ },{ /* 3 */
@ -1507,7 +1510,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.init_dma = init_dma_hpt366, .init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
},{ /* 4 */ },{ /* 4 */
@ -1518,7 +1521,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
},{ /* 5 */ },{ /* 5 */
@ -1528,7 +1531,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
.init_dma = init_dma_hpt366, .init_dma = init_dma_hpt366,
.enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
.extra = 240, .extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAGS_HPT3XX,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
} }

21
drivers/ide/pci/it8213.c
View File

@ -101,24 +101,11 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
pci_read_config_byte(dev, 0x54, &reg54); pci_read_config_byte(dev, 0x54, &reg54);
pci_read_config_byte(dev, 0x55, &reg55); pci_read_config_byte(dev, 0x55, &reg55);
switch(speed) {
case XFER_UDMA_6:
case XFER_UDMA_4:
case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
case XFER_UDMA_5:
case XFER_UDMA_3:
case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
break;
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_SW_DMA_2:
break;
default:
return;
}
if (speed >= XFER_UDMA_0) { if (speed >= XFER_UDMA_0) {
u8 udma = speed - XFER_UDMA_0;
u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
if (!(reg48 & u_flag)) if (!(reg48 & u_flag))
pci_write_config_byte(dev, 0x48, reg48 | u_flag); pci_write_config_byte(dev, 0x48, reg48 | u_flag);
if (speed >= XFER_UDMA_5) { if (speed >= XFER_UDMA_5) {

18
drivers/ide/pci/pdc202xx_new.c
View File

@ -162,32 +162,18 @@ static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
if (max_dma_rate(hwif->pci_dev) == 4) { if (max_dma_rate(hwif->pci_dev) == 4) {
u8 mode = speed & 0x07; u8 mode = speed & 0x07;
switch (speed) { if (speed >= XFER_UDMA_0) {
case XFER_UDMA_6:
case XFER_UDMA_5:
case XFER_UDMA_4:
case XFER_UDMA_3:
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0:
set_indexed_reg(hwif, 0x10 + adj, set_indexed_reg(hwif, 0x10 + adj,
udma_timings[mode].reg10); udma_timings[mode].reg10);
set_indexed_reg(hwif, 0x11 + adj, set_indexed_reg(hwif, 0x11 + adj,
udma_timings[mode].reg11); udma_timings[mode].reg11);
set_indexed_reg(hwif, 0x12 + adj, set_indexed_reg(hwif, 0x12 + adj,
udma_timings[mode].reg12); udma_timings[mode].reg12);
break; } else {
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_MW_DMA_0:
set_indexed_reg(hwif, 0x0e + adj, set_indexed_reg(hwif, 0x0e + adj,
mwdma_timings[mode].reg0e); mwdma_timings[mode].reg0e);
set_indexed_reg(hwif, 0x0f + adj, set_indexed_reg(hwif, 0x0f + adj,
mwdma_timings[mode].reg0f); mwdma_timings[mode].reg0f);
break;
default:
printk(KERN_ERR "pdc202xx_new: "
"Unknown speed %d ignored\n", speed);
} }
} else if (speed == XFER_UDMA_2) { } else if (speed == XFER_UDMA_2) {
/* Set tHOLD bit to 0 if using UDMA mode 2 */ /* Set tHOLD bit to 0 if using UDMA mode 2 */

12
drivers/ide/pci/pdc202xx_old.c
View File

@ -375,6 +375,11 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
} }
} }
#define IDE_HFLAGS_PDC202XX \
(IDE_HFLAG_ERROR_STOPS_FIFO | \
IDE_HFLAG_ABUSE_SET_DMA_MODE | \
IDE_HFLAG_OFF_BOARD)
#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \ #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
{ \ { \
.name = name_str, \ .name = name_str, \
@ -382,9 +387,7 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
.init_hwif = init_hwif_pdc202xx, \ .init_hwif = init_hwif_pdc202xx, \
.init_dma = init_dma_pdc202xx, \ .init_dma = init_dma_pdc202xx, \
.extra = 48, \ .extra = 48, \
.host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | \ .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
extra_flags | \
IDE_HFLAG_OFF_BOARD, \
.pio_mask = ATA_PIO4, \ .pio_mask = ATA_PIO4, \
.mwdma_mask = ATA_MWDMA2, \ .mwdma_mask = ATA_MWDMA2, \
.udma_mask = udma, \ .udma_mask = udma, \
@ -397,8 +400,7 @@ static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
.init_hwif = init_hwif_pdc202xx, .init_hwif = init_hwif_pdc202xx,
.init_dma = init_dma_pdc202xx, .init_dma = init_dma_pdc202xx,
.extra = 16, .extra = 16,
.host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | .host_flags = IDE_HFLAGS_PDC202XX,
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA2, .udma_mask = ATA_UDMA2,

17
drivers/ide/pci/piix.c
View File

@ -203,20 +203,11 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
pci_read_config_byte(dev, 0x54, &reg54); pci_read_config_byte(dev, 0x54, &reg54);
pci_read_config_byte(dev, 0x55, &reg55); pci_read_config_byte(dev, 0x55, &reg55);
switch(speed) {
case XFER_UDMA_4:
case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
case XFER_UDMA_5:
case XFER_UDMA_3:
case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_SW_DMA_2: break;
default: return;
}
if (speed >= XFER_UDMA_0) { if (speed >= XFER_UDMA_0) {
u8 udma = speed - XFER_UDMA_0;
u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
if (!(reg48 & u_flag)) if (!(reg48 & u_flag))
pci_write_config_byte(dev, 0x48, reg48 | u_flag); pci_write_config_byte(dev, 0x48, reg48 | u_flag);
if (speed == XFER_UDMA_5) { if (speed == XFER_UDMA_5) {

2
drivers/ide/pci/sc1200.c
View File

@ -185,8 +185,6 @@ static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
case PCI_CLK_66: timings = 0x00015151; break; case PCI_CLK_66: timings = 0x00015151; break;
} }
break; break;
default:
return;
} }
if (unit == 0) { /* are we configuring drive0? */ if (unit == 0) { /* are we configuring drive0? */

12
drivers/ide/pci/scc_pata.c
View File

@ -254,19 +254,7 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
offset = 0; /* 100MHz */ offset = 0; /* 100MHz */
} }
switch (speed) {
case XFER_UDMA_6:
case XFER_UDMA_5:
case XFER_UDMA_4:
case XFER_UDMA_3:
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0:
idx = speed - XFER_UDMA_0; idx = speed - XFER_UDMA_0;
break;
default:
return;
}
jcactsel = JCACTSELtbl[offset][idx]; jcactsel = JCACTSELtbl[offset][idx];
if (is_slave) { if (is_slave) {

17
drivers/ide/pci/serverworks.c
View File

@ -366,12 +366,17 @@ static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
} }
} }
#define IDE_HFLAGS_SVWKS \
(IDE_HFLAG_LEGACY_IRQS | \
IDE_HFLAG_ABUSE_SET_DMA_MODE | \
IDE_HFLAG_BOOTABLE)
static const struct ide_port_info serverworks_chipsets[] __devinitdata = { static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
{ /* 0 */ { /* 0 */
.name = "SvrWks OSB4", .name = "SvrWks OSB4",
.init_chipset = init_chipset_svwks, .init_chipset = init_chipset_svwks,
.init_hwif = init_hwif_svwks, .init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, .host_flags = IDE_HFLAGS_SVWKS,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = 0x00, /* UDMA is problematic on OSB4 */ .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
@ -379,7 +384,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
.name = "SvrWks CSB5", .name = "SvrWks CSB5",
.init_chipset = init_chipset_svwks, .init_chipset = init_chipset_svwks,
.init_hwif = init_hwif_svwks, .init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, .host_flags = IDE_HFLAGS_SVWKS,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,
@ -387,7 +392,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
.name = "SvrWks CSB6", .name = "SvrWks CSB6",
.init_chipset = init_chipset_svwks, .init_chipset = init_chipset_svwks,
.init_hwif = init_hwif_svwks, .init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, .host_flags = IDE_HFLAGS_SVWKS,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,
@ -395,8 +400,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
.name = "SvrWks CSB6", .name = "SvrWks CSB6",
.init_chipset = init_chipset_svwks, .init_chipset = init_chipset_svwks,
.init_hwif = init_hwif_svwks, .init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,
@ -404,8 +408,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
.name = "SvrWks HT1000", .name = "SvrWks HT1000",
.init_chipset = init_chipset_svwks, .init_chipset = init_chipset_svwks,
.init_hwif = init_hwif_svwks, .init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE | .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA5, .udma_mask = ATA_UDMA5,

27
drivers/ide/pci/siimage.c
View File

@ -278,27 +278,14 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
scsc = is_sata(hwif) ? 1 : scsc; scsc = is_sata(hwif) ? 1 : scsc;
switch(speed) { if (speed >= XFER_UDMA_0) {
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_MW_DMA_0:
multi = dma[speed - XFER_MW_DMA_0];
mode |= ((unit) ? 0x20 : 0x02);
break;
case XFER_UDMA_6:
case XFER_UDMA_5:
case XFER_UDMA_4:
case XFER_UDMA_3:
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0:
multi = dma[2]; multi = dma[2];
ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
(ultra5[speed - XFER_UDMA_0])); ultra5[speed - XFER_UDMA_0]);
mode |= ((unit) ? 0x30 : 0x03); mode |= (unit ? 0x30 : 0x03);
break; } else {
default: multi = dma[speed - XFER_MW_DMA_0];
return; mode |= (unit ? 0x20 : 0x02);
} }
if (hwif->mmio) { if (hwif->mmio) {

19
drivers/ide/pci/sis5513.c
View File

@ -351,25 +351,10 @@ static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
{ {
/* Config chip for mode */ if (speed >= XFER_UDMA_0)
switch(speed) {
case XFER_UDMA_6:
case XFER_UDMA_5:
case XFER_UDMA_4:
case XFER_UDMA_3:
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0:
sis_program_udma_timings(drive, speed); sis_program_udma_timings(drive, speed);
break; else
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_MW_DMA_0:
sis_program_timings(drive, speed); sis_program_timings(drive, speed);
break;
default:
break;
}
} }
static u8 sis5513_ata133_udma_filter(ide_drive_t *drive) static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)

8
drivers/ide/pci/sl82c105.c
View File

@ -115,10 +115,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
drive->name, ide_xfer_verbose(speed))); drive->name, ide_xfer_verbose(speed)));
switch (speed) {
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_MW_DMA_0:
drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
/* /*
@ -138,10 +134,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
pci_write_config_word(dev, reg, drv_ctrl); pci_write_config_word(dev, reg, drv_ctrl);
} }
break;
default:
return;
}
} }
/* /*

14
drivers/ide/pci/slc90e66.c
View File

@ -91,19 +91,9 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
pci_read_config_word(dev, 0x48, &reg48); pci_read_config_word(dev, 0x48, &reg48);
pci_read_config_word(dev, 0x4a, &reg4a); pci_read_config_word(dev, 0x4a, &reg4a);
switch(speed) {
case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_SW_DMA_2: break;
default: return;
}
if (speed >= XFER_UDMA_0) { if (speed >= XFER_UDMA_0) {
u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
if (!(reg48 & u_flag)) if (!(reg48 & u_flag))
pci_write_config_word(dev, 0x48, reg48|u_flag); pci_write_config_word(dev, 0x48, reg48|u_flag);
/* FIXME: (reg4a & a_speed) ? */ /* FIXME: (reg4a & a_speed) ? */

3
drivers/ide/pci/tc86c001.c
View File

@ -222,7 +222,8 @@ static const struct ide_port_info tc86c001_chipset __devinitdata = {
.name = "TC86C001", .name = "TC86C001",
.init_chipset = init_chipset_tc86c001, .init_chipset = init_chipset_tc86c001,
.init_hwif = init_hwif_tc86c001, .init_hwif = init_hwif_tc86c001,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD, .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD |
IDE_HFLAG_ABUSE_SET_DMA_MODE,
.pio_mask = ATA_PIO4, .pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2, .mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA4, .udma_mask = ATA_UDMA4,

2
drivers/ide/pci/triflex.c
View File

@ -81,8 +81,6 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
case XFER_PIO_0: case XFER_PIO_0:
timing = 0x0808; timing = 0x0808;
break; break;
default:
return;
} }
triflex_timings &= ~(0xFFFF << (16 * unit)); triflex_timings &= ~(0xFFFF << (16 * unit));

1
drivers/ide/pci/via82cxxx.c
View File

@ -439,6 +439,7 @@ static const struct ide_port_info via82cxxx_chipset __devinitdata = {
.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
IDE_HFLAG_PIO_NO_DOWNGRADE | IDE_HFLAG_PIO_NO_DOWNGRADE |
IDE_HFLAG_ABUSE_SET_DMA_MODE |
IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_IO_32BIT | IDE_HFLAG_IO_32BIT |
IDE_HFLAG_BOOTABLE, IDE_HFLAG_BOOTABLE,

24
drivers/ide/ppc/pmac.c
View File

@ -828,15 +828,8 @@ static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
tl[0] = *timings; tl[0] = *timings;
tl[1] = *timings2; tl[1] = *timings2;
switch(speed) {
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
case XFER_UDMA_6: if (speed >= XFER_UDMA_0) {
case XFER_UDMA_5:
case XFER_UDMA_4:
case XFER_UDMA_3:
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0:
if (pmif->kind == controller_kl_ata4) if (pmif->kind == controller_kl_ata4)
ret = set_timings_udma_ata4(&tl[0], speed); ret = set_timings_udma_ata4(&tl[0], speed);
else if (pmif->kind == controller_un_ata6 else if (pmif->kind == controller_un_ata6
@ -845,21 +838,10 @@ static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
else if (pmif->kind == controller_sh_ata6) else if (pmif->kind == controller_sh_ata6)
ret = set_timings_udma_shasta(&tl[0], &tl[1], speed); ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
else else
ret = 1; ret = -1;
break; } else
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
case XFER_MW_DMA_0:
set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed); set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
break;
case XFER_SW_DMA_2:
case XFER_SW_DMA_1:
case XFER_SW_DMA_0:
return;
#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
default:
ret = 1;
}
if (ret) if (ret)
return; return;

1
include/linux/ide.h
View File

@ -1094,6 +1094,7 @@ enum {
IDE_HFLAG_IO_32BIT = (1 << 24), IDE_HFLAG_IO_32BIT = (1 << 24),
/* unmask IRQs */ /* unmask IRQs */
IDE_HFLAG_UNMASK_IRQS = (1 << 25), IDE_HFLAG_UNMASK_IRQS = (1 << 25),
IDE_HFLAG_ABUSE_SET_DMA_MODE = (1 << 26),
}; };
#ifdef CONFIG_BLK_DEV_OFFBOARD #ifdef CONFIG_BLK_DEV_OFFBOARD