From 70ad0d0351470d6c1d22063497e644ecf847b63f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Jun 2017 12:16:32 +0200 Subject: [PATCH 1/7] clk: meson8b: export the SAR ADC clocks Export the clocks for the SAR ADC so they can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 4 ++-- include/dt-bindings/clock/meson8b-clkc.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 3881defc8644..5447d4a5c9ba 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -87,7 +87,7 @@ #define CLKID_PERIPHS 20 #define CLKID_SPICC 21 #define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 +/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 #define CLKID_RNG0 25 #define CLKID_UART0 26 @@ -133,7 +133,7 @@ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_UART2 68 -#define CLKID_SANA 69 +/* #define CLKID_SANA */ #define CLKID_VPU_INTR 70 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 #define CLKID_CLK81_A9 72 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index a55ff8c9b30f..1c7f090da440 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -21,5 +21,7 @@ #define CLKID_ZERO 13 #define CLKID_MPEG_SEL 14 #define CLKID_MPEG_DIV 15 +#define CLKID_SAR_ADC 23 +#define CLKID_SANA 69 #endif /* __MESON8B_CLKC_H */ From e2e5f3211fe2b57f4a9feed5c053c48aea7eb2a2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Jun 2017 12:16:33 +0200 Subject: [PATCH 2/7] clk: meson8b: export the SDIO clock Export the SDIO clock so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 5447d4a5c9ba..e0fb386ccc23 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -94,7 +94,7 @@ #define CLKID_SDHC 27 #define CLKID_STREAM 28 #define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 +/* #define CLKID_SDIO */ #define CLKID_ABUF 31 #define CLKID_HIU_IFACE 32 #define CLKID_ASSIST_MISC 33 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 1c7f090da440..821b08574900 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -22,6 +22,7 @@ #define CLKID_MPEG_SEL 14 #define CLKID_MPEG_DIV 15 #define CLKID_SAR_ADC 23 +#define CLKID_SDIO 30 #define CLKID_SANA 69 #endif /* __MESON8B_CLKC_H */ From 06eff6a792967d0cbb70424bc6acded91b28e41f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Jun 2017 12:16:34 +0200 Subject: [PATCH 3/7] clk: meson8b: export the gate clock for the HW random number generator This exports the clock so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index e0fb386ccc23..51c3f6717180 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -89,7 +89,7 @@ #define CLKID_I2C 22 /* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 +/* #define CLKID_RNG0 */ #define CLKID_UART0 26 #define CLKID_SDHC 27 #define CLKID_STREAM 28 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 821b08574900..f004e6760b5d 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -22,6 +22,7 @@ #define CLKID_MPEG_SEL 14 #define CLKID_MPEG_DIV 15 #define CLKID_SAR_ADC 23 +#define CLKID_RNG0 25 #define CLKID_SDIO 30 #define CLKID_SANA 69 From 677f6af5d685a5990148222804f3649196789b91 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Jun 2017 12:16:35 +0200 Subject: [PATCH 4/7] clk: meson8b: export the USB clocks Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 10 +++++----- include/dt-bindings/clock/meson8b-clkc.h | 5 +++++ 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 51c3f6717180..17479c60864d 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -114,12 +114,12 @@ #define CLKID_AIU 47 #define CLKID_UART1 48 #define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 +/* #define CLKID_USB0 */ +/* #define CLKID_USB1 */ #define CLKID_RESET 52 #define CLKID_NAND 53 #define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 +/* #define CLKID_USB */ #define CLKID_VDIN1 56 #define CLKID_AHB_ARB0 57 #define CLKID_EFUSE 58 @@ -128,8 +128,8 @@ #define CLKID_AHB_CTRL_BUS 61 #define CLKID_HDMI_INTR_SYNC 62 #define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 +/* CLKID_USB1_DDR_BRIDGE */ +/* CLKID_USB0_DDR_BRIDGE */ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_UART2 68 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index f004e6760b5d..04f0d1fcd308 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -24,6 +24,11 @@ #define CLKID_SAR_ADC 23 #define CLKID_RNG0 25 #define CLKID_SDIO 30 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_USB 55 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_SANA 69 #endif /* __MESON8B_CLKC_H */ From c22f06d3c0c943005697d03e46dccad2aa0bc8c0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Jun 2017 12:16:36 +0200 Subject: [PATCH 5/7] clk: meson8b: export the ethernet gate clock Export the ethernet gate clock to the dt-bindings. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 17479c60864d..a687e02547dc 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -100,7 +100,7 @@ #define CLKID_ASSIST_MISC 33 #define CLKID_SPI 34 #define CLKID_I2S_SPDIF 35 -#define CLKID_ETH 36 +/* #define CLKID_ETH */ #define CLKID_DEMUX 37 #define CLKID_AIU_GLUE 38 #define CLKID_IEC958 39 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 04f0d1fcd308..e29227fb52a1 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -24,6 +24,7 @@ #define CLKID_SAR_ADC 23 #define CLKID_RNG0 25 #define CLKID_SDIO 30 +#define CLKID_ETH 36 #define CLKID_USB0 50 #define CLKID_USB1 51 #define CLKID_USB 55 From 855f06a1009faabb0c6a3e9b49d115496d325856 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Jun 2017 20:33:39 +0200 Subject: [PATCH 6/7] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on. In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources. The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code). The difference between the Meson8 and Meson8b clock gates seem to be: - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, CSI_DIG_CLKIN gates which don't seem to be available on Meson8b - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead of "PERIPHS_TOP" (on Meson8b) - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL kernel sources) None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block). The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching. None of these VPU clocks are not supported by our mainline meson8b clock driver yet though. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Acked-by: Kevin Hilman Signed-off-by: Jerome Brunet --- .../bindings/clock/amlogic,meson8b-clkc.txt | 11 +++++++---- drivers/clk/meson/Kconfig | 6 +++--- drivers/clk/meson/meson8b.c | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 2b7b3fa588d7..606da38c0959 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -1,11 +1,14 @@ -* Amlogic Meson8b Clock and Reset Unit +* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit -The Amlogic Meson8b clock controller generates and supplies clock to various -controllers within the SoC. +The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and +supplies clock to various controllers within the SoC. Required Properties: -- compatible: should be "amlogic,meson8b-clkc" +- compatible: must be one of: + - "amlogic,meson8-clkc" for Meson8 (S802) SoCs + - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs + - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - reg: it must be composed by two tuples: 0) physical base address of the xtal register and length of memory mapped region. diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 19480bcc7046..4a806203b73c 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B bool depends on COMMON_CLK_AMLOGIC help - Support for the clock controller on AmLogic S805 devices, aka - meson8b. Say Y if you want peripherals and CPU frequency scaling to - work. + Support for the clock controller on AmLogic S802 (Meson8), + S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you + want peripherals and CPU frequency scaling to work. config COMMON_CLK_GXBB bool diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 9d1aaf6e9ac6..bb3f1de876b1 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1,5 +1,6 @@ /* - * AmLogic S805 / Meson8b Clock Controller Driver + * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller + * Driver * * Copyright (c) 2015 Endless Mobile, Inc. * Author: Carlo Caione @@ -777,7 +778,9 @@ iounmap: } static const struct of_device_id meson8b_clkc_match_table[] = { + { .compatible = "amlogic,meson8-clkc" }, { .compatible = "amlogic,meson8b-clkc" }, + { .compatible = "amlogic,meson8m2-clkc" }, { } }; From 215c80a7d65312911ca7b08d42b05652e27eed5f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Jun 2017 15:55:45 +0200 Subject: [PATCH 7/7] clk: meson: gxbb: add all clk81 parents Remove the FIXME on clk81 mux and add all the documented parents Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2919a0e044a5..f4117a368aa1 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -603,7 +603,11 @@ static struct meson_clk_mpll gxbb_mpll2 = { * coordinated clock rates feature */ -static u32 mux_table_clk81[] = { 6, 5, 7 }; +static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; +static const char * const clk81_parent_names[] = { + "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", + "fclk_div3", "fclk_div5" +}; static struct clk_mux gxbb_mpeg_clk_sel = { .reg = (void *)HHI_MPEG_CLK_CNTL, @@ -616,13 +620,12 @@ static struct clk_mux gxbb_mpeg_clk_sel = { .name = "mpeg_clk_sel", .ops = &clk_mux_ro_ops, /* - * FIXME bits 14:12 selects from 8 possible parents: + * bits 14:12 selects from 8 possible parents: * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, * fclk_div4, fclk_div3, fclk_div5 */ - .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", - "fclk_div5" }, - .num_parents = 3, + .parent_names = clk81_parent_names, + .num_parents = ARRAY_SIZE(clk81_parent_names), .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), }, };