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iio: adc: ad7280a: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 003f1d48de52 ("staging:iio:adc:ad7280a: Split buff[2] into tx and rx parts")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-11-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:55:50 +01:00
parent b990cdfe75
commit 4e20084295
1 changed files with 1 additions and 1 deletions
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drivers/iio/adc/ad7280a.c
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@ -183,7 +183,7 @@ struct ad7280_state {
unsigned char cb_mask[AD7280A_MAX_CHAIN];
struct mutex lock; /* protect sensor state */
__be32 tx ____cacheline_aligned;
__be32 tx __aligned(IIO_DMA_MINALIGN);
__be32 rx;
};