Serial driver fixes for 4.19-rc7
Here are 3 small serial driver fixes for 4.19-rc7 - 2 sh-sci bugfixes for reported issues - a revert of the PM handling for the 8250_dw code All of these have been in linux-next with no reported issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCW7mhRw8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+ykYngCghu5cEWdhIHHZh9PsRh4PBcE1LgUAoLhsnAw/ f3yufssSk5Wx8+OZmTK/ =xIYc -----END PGP SIGNATURE----- Merge tag 'tty-4.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty I wrote: "Serial driver fixes for 4.19-rc7 Here are 3 small serial driver fixes for 4.19-rc7 - 2 sh-sci bugfixes for reported issues - a revert of the PM handling for the 8250_dw code All of these have been in linux-next with no reported issues." * tag 'tty-4.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: Revert "serial: sh-sci: Allow for compressed SCIF address" Revert "serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE" Revert "serial: 8250_dw: Fix runtime PM handling"
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4ebaf0754c
@ -630,10 +630,6 @@ static int dw8250_probe(struct platform_device *pdev)
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if (!data->skip_autocfg)
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dw8250_setup_port(p);
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#ifdef CONFIG_PM
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uart.capabilities |= UART_CAP_RPM;
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#endif
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/* If we have a valid fifosize, try hooking up DMA */
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if (p->fifosize) {
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data->dma.rxconf.src_maxburst = p->fifosize / 4;
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@ -291,6 +291,33 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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.error_clear = SCIF_ERROR_CLEAR,
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},
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/*
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* The "SCIFA" that is in RZ/T and RZ/A2.
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* It looks like a normal SCIF with FIFO data, but with a
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* compressed address space. Also, the break out of interrupts
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* are different: ERI/BRI, RXI, TXI, TEI, DRI.
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*/
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[SCIx_RZ_SCIFA_REGTYPE] = {
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.regs = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x02, 8 },
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[SCSCR] = { 0x04, 16 },
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[SCxTDR] = { 0x06, 8 },
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[SCxSR] = { 0x08, 16 },
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[SCxRDR] = { 0x0A, 8 },
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[SCFCR] = { 0x0C, 16 },
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[SCFDR] = { 0x0E, 16 },
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[SCSPTR] = { 0x10, 16 },
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[SCLSR] = { 0x12, 16 },
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},
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.fifosize = 16,
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.overrun_reg = SCLSR,
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.overrun_mask = SCLSR_ORER,
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.sampling_rate_mask = SCI_SR(32),
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.error_mask = SCIF_DEFAULT_ERROR_MASK,
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.error_clear = SCIF_ERROR_CLEAR,
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},
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/*
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* Common SH-3 SCIF definitions.
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*/
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@ -319,15 +346,15 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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[SCIx_SH4_SCIF_REGTYPE] = {
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.regs = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x02, 8 },
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[SCSCR] = { 0x04, 16 },
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[SCxTDR] = { 0x06, 8 },
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[SCxSR] = { 0x08, 16 },
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[SCxRDR] = { 0x0a, 8 },
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[SCFCR] = { 0x0c, 16 },
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[SCFDR] = { 0x0e, 16 },
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[SCSPTR] = { 0x10, 16 },
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[SCLSR] = { 0x12, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x0c, 8 },
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[SCxSR] = { 0x10, 16 },
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[SCxRDR] = { 0x14, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCSPTR] = { 0x20, 16 },
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[SCLSR] = { 0x24, 16 },
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},
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.fifosize = 16,
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.overrun_reg = SCLSR,
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@ -2810,7 +2837,7 @@ static int sci_init_single(struct platform_device *dev,
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{
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struct uart_port *port = &sci_port->port;
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const struct resource *res;
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unsigned int i, regtype;
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unsigned int i;
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int ret;
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sci_port->cfg = p;
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@ -2847,7 +2874,6 @@ static int sci_init_single(struct platform_device *dev,
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if (unlikely(sci_port->params == NULL))
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return -EINVAL;
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regtype = sci_port->params - sci_port_params;
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switch (p->type) {
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case PORT_SCIFB:
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sci_port->rx_trigger = 48;
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@ -2902,10 +2928,6 @@ static int sci_init_single(struct platform_device *dev,
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port->regshift = 1;
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}
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if (regtype == SCIx_SH4_SCIF_REGTYPE)
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if (sci_port->reg_size >= 0x20)
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port->regshift = 1;
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/*
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* The UART port needs an IRQ value, so we peg this to the RX IRQ
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* for the multi-IRQ ports, which is where we are primarily
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@ -3110,6 +3132,10 @@ static const struct of_device_id of_sci_match[] = {
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.compatible = "renesas,scif-r7s72100",
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
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},
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{
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.compatible = "renesas,scif-r7s9210",
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
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},
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/* Family-specific types */
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{
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.compatible = "renesas,rcar-gen1-scif",
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@ -36,6 +36,7 @@ enum {
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SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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SCIx_SH7705_SCIF_REGTYPE,
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SCIx_HSCIF_REGTYPE,
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SCIx_RZ_SCIFA_REGTYPE,
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SCIx_NR_REGTYPES,
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};
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