drm/i915: Eliminate has_4tile feature flag
We don't really need a feature flag for has_4tile since there's a well-defined cutover point (DG2) at which all new platforms started using Tile4 as their Y-major tiling layout. The GT side of the code already handles Tile4 vs legacy TileY with checks on the IP version rather than looking at the feature flag, and we can simplify the display code similarly (which will also make it more self-contained for re-use in the Xe driver). Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230810234618.3738870-4-matthew.d.roper@intel.com
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@ -32,6 +32,7 @@ struct drm_printer;
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func(overlay_needs_physical); \
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func(supports_tv);
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#define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
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#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
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#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
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#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
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@ -733,7 +733,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
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#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
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#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
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#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
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#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
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#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
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@ -713,7 +713,6 @@ static const struct intel_device_info adl_p_info = {
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.has_3d_pipeline = 1, \
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.has_64bit_reloc = 1, \
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.has_flat_ccs = 1, \
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.has_4tile = 1, \
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.has_global_mocs = 1, \
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.has_gt_uc = 1, \
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.has_llc = 1, \
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@ -150,7 +150,6 @@ enum intel_ppgtt_type {
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func(gpu_reset_clobbers_display); \
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func(has_reset_engine); \
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func(has_3d_pipeline); \
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func(has_4tile); \
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func(has_flat_ccs); \
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func(has_global_mocs); \
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func(has_gmd_id); \
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