drm/amdgpu/vcn3.0: convert to IP version checking
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -95,7 +95,7 @@ static int vcn_v3_0_early_init(void *handle)
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adev->vcn.num_enc_rings = 1;
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} else {
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if (adev->asic_type == CHIP_SIENNA_CICHLID) {
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if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
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u32 harvest;
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adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
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@ -112,7 +112,7 @@ static int vcn_v3_0_early_init(void *handle)
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} else
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adev->vcn.num_vcn_inst = 1;
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if (adev->asic_type == CHIP_BEIGE_GOBY)
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if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
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adev->vcn.num_enc_rings = 0;
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else
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adev->vcn.num_enc_rings = 2;
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@ -1272,7 +1272,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
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fw_shared->rb.wptr = lower_32_bits(ring->wptr);
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fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
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if (adev->asic_type != CHIP_BEIGE_GOBY) {
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if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
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fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
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ring = &adev->vcn.inst[i].ring_enc[0];
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WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
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@ -1644,7 +1644,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
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UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
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~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
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if (adev->asic_type != CHIP_BEIGE_GOBY) {
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if (adev->ip_versions[UVD_HWIP] != IP_VERSION(3, 0, 33)) {
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/* Restore */
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fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
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fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
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