dmaengine: sh: Add DMAC driver for RZ/G2L SoC
Add DMA Controller driver for RZ/G2L SoC. Based on the work done by Chris Brandt for RZ/A DMA driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210806095322.2326-4-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Biju Das
Vinod Koul
parent
ab959c7d4e
commit
5000d37042
@ -47,3 +47,12 @@ config RENESAS_USB_DMAC
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help
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This driver supports the USB-DMA controller found in the Renesas
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SoCs.
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config RZ_DMAC
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tristate "Renesas RZ/G2L DMA Controller"
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depends on ARCH_R9A07G044 || COMPILE_TEST
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select RENESAS_DMA
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select DMA_VIRTUAL_CHANNELS
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help
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This driver supports the general purpose DMA controller found in the
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Renesas RZ/G2L SoC variants.
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@ -15,3 +15,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
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obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
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obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
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obj-$(CONFIG_RZ_DMAC) += rz-dmac.o
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971
drivers/dma/sh/rz-dmac.c
Normal file
971
drivers/dma/sh/rz-dmac.c
Normal file
@ -0,0 +1,971 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L DMA Controller Driver
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*
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* Based on imx-dma.c
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "../dmaengine.h"
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#include "../virt-dma.h"
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enum rz_dmac_prep_type {
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RZ_DMAC_DESC_MEMCPY,
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RZ_DMAC_DESC_SLAVE_SG,
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};
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struct rz_lmdesc {
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u32 header;
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u32 sa;
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u32 da;
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u32 tb;
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u32 chcfg;
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u32 chitvl;
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u32 chext;
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u32 nxla;
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};
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struct rz_dmac_desc {
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struct virt_dma_desc vd;
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dma_addr_t src;
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dma_addr_t dest;
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size_t len;
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struct list_head node;
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enum dma_transfer_direction direction;
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enum rz_dmac_prep_type type;
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/* For slave sg */
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struct scatterlist *sg;
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unsigned int sgcount;
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};
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#define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd)
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struct rz_dmac_chan {
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struct virt_dma_chan vc;
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void __iomem *ch_base;
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void __iomem *ch_cmn_base;
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unsigned int index;
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int irq;
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struct rz_dmac_desc *desc;
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int descs_allocated;
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enum dma_slave_buswidth src_word_size;
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enum dma_slave_buswidth dst_word_size;
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dma_addr_t src_per_address;
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dma_addr_t dst_per_address;
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u32 chcfg;
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u32 chctrl;
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int mid_rid;
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struct list_head ld_free;
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struct list_head ld_queue;
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struct list_head ld_active;
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struct {
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struct rz_lmdesc *base;
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struct rz_lmdesc *head;
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struct rz_lmdesc *tail;
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dma_addr_t base_dma;
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} lmdesc;
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};
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#define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan)
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struct rz_dmac {
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struct dma_device engine;
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struct device *dev;
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void __iomem *base;
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void __iomem *ext_base;
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unsigned int n_channels;
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struct rz_dmac_chan *channels;
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DECLARE_BITMAP(modules, 1024);
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};
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#define to_rz_dmac(d) container_of(d, struct rz_dmac, engine)
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/*
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* -----------------------------------------------------------------------------
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* Registers
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*/
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#define CHSTAT 0x0024
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#define CHCTRL 0x0028
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#define CHCFG 0x002c
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#define NXLA 0x0038
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#define DCTRL 0x0000
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#define EACH_CHANNEL_OFFSET 0x0040
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#define CHANNEL_0_7_OFFSET 0x0000
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#define CHANNEL_0_7_COMMON_BASE 0x0300
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#define CHANNEL_8_15_OFFSET 0x0400
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#define CHANNEL_8_15_COMMON_BASE 0x0700
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#define CHSTAT_ER BIT(4)
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#define CHSTAT_EN BIT(0)
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#define CHCTRL_CLRINTMSK BIT(17)
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#define CHCTRL_CLRSUS BIT(9)
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#define CHCTRL_CLRTC BIT(6)
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#define CHCTRL_CLREND BIT(5)
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#define CHCTRL_CLRRQ BIT(4)
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#define CHCTRL_SWRST BIT(3)
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#define CHCTRL_STG BIT(2)
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#define CHCTRL_CLREN BIT(1)
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#define CHCTRL_SETEN BIT(0)
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#define CHCTRL_DEFAULT (CHCTRL_CLRINTMSK | CHCTRL_CLRSUS | \
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CHCTRL_CLRTC | CHCTRL_CLREND | \
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CHCTRL_CLRRQ | CHCTRL_SWRST | \
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CHCTRL_CLREN)
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#define CHCFG_DMS BIT(31)
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#define CHCFG_DEM BIT(24)
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#define CHCFG_DAD BIT(21)
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#define CHCFG_SAD BIT(20)
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#define CHCFG_REQD BIT(3)
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#define CHCFG_SEL(bits) ((bits) & 0x07)
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#define CHCFG_MEM_COPY (0x80400008)
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#define CHCFG_FILL_DDS(a) (((a) << 16) & GENMASK(19, 16))
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#define CHCFG_FILL_SDS(a) (((a) << 12) & GENMASK(15, 12))
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#define CHCFG_FILL_TM(a) (((a) & BIT(5)) << 22)
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#define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6)
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#define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5)
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#define CHCFG_FILL_HIEN(a) (((a) & BIT(0)) << 5)
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#define MID_RID_MASK GENMASK(9, 0)
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#define CHCFG_MASK GENMASK(15, 10)
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#define CHCFG_DS_INVALID 0xFF
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#define DCTRL_LVINT BIT(1)
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#define DCTRL_PR BIT(0)
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#define DCTRL_DEFAULT (DCTRL_LVINT | DCTRL_PR)
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/* LINK MODE DESCRIPTOR */
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#define HEADER_LV BIT(0)
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#define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16
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#define RZ_DMAC_MAX_CHANNELS 16
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#define DMAC_NR_LMDESC 64
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/*
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* -----------------------------------------------------------------------------
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* Device access
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*/
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static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val,
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unsigned int offset)
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{
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writel(val, dmac->base + offset);
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}
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static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val,
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unsigned int offset)
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{
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writel(val, dmac->ext_base + offset);
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}
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static u32 rz_dmac_ext_readl(struct rz_dmac *dmac, unsigned int offset)
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{
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return readl(dmac->ext_base + offset);
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}
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static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val,
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unsigned int offset, int which)
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{
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if (which)
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writel(val, channel->ch_base + offset);
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else
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writel(val, channel->ch_cmn_base + offset);
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}
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static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel,
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unsigned int offset, int which)
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{
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if (which)
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return readl(channel->ch_base + offset);
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else
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return readl(channel->ch_cmn_base + offset);
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}
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/*
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* -----------------------------------------------------------------------------
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* Initialization
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*/
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static void rz_lmdesc_setup(struct rz_dmac_chan *channel,
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struct rz_lmdesc *lmdesc)
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{
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u32 nxla;
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channel->lmdesc.base = lmdesc;
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channel->lmdesc.head = lmdesc;
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channel->lmdesc.tail = lmdesc;
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nxla = channel->lmdesc.base_dma;
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while (lmdesc < (channel->lmdesc.base + (DMAC_NR_LMDESC - 1))) {
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lmdesc->header = 0;
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nxla += sizeof(*lmdesc);
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lmdesc->nxla = nxla;
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lmdesc++;
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}
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lmdesc->header = 0;
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lmdesc->nxla = channel->lmdesc.base_dma;
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}
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/*
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* -----------------------------------------------------------------------------
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* Descriptors preparation
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*/
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static void rz_dmac_lmdesc_recycle(struct rz_dmac_chan *channel)
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{
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struct rz_lmdesc *lmdesc = channel->lmdesc.head;
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while (!(lmdesc->header & HEADER_LV)) {
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lmdesc->header = 0;
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lmdesc++;
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if (lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
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lmdesc = channel->lmdesc.base;
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}
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channel->lmdesc.head = lmdesc;
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}
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static void rz_dmac_enable_hw(struct rz_dmac_chan *channel)
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{
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struct dma_chan *chan = &channel->vc.chan;
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struct rz_dmac *dmac = to_rz_dmac(chan->device);
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unsigned long flags;
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u32 nxla;
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u32 chctrl;
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u32 chstat;
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dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index);
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local_irq_save(flags);
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rz_dmac_lmdesc_recycle(channel);
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nxla = channel->lmdesc.base_dma +
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(sizeof(struct rz_lmdesc) * (channel->lmdesc.head -
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channel->lmdesc.base));
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chstat = rz_dmac_ch_readl(channel, CHSTAT, 1);
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if (!(chstat & CHSTAT_EN)) {
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chctrl = (channel->chctrl | CHCTRL_SETEN);
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rz_dmac_ch_writel(channel, nxla, NXLA, 1);
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rz_dmac_ch_writel(channel, channel->chcfg, CHCFG, 1);
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rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1);
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rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1);
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}
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local_irq_restore(flags);
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}
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static void rz_dmac_disable_hw(struct rz_dmac_chan *channel)
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{
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struct dma_chan *chan = &channel->vc.chan;
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struct rz_dmac *dmac = to_rz_dmac(chan->device);
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unsigned long flags;
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dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index);
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local_irq_save(flags);
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rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
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local_irq_restore(flags);
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}
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static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars)
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{
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u32 dmars_offset = (nr / 2) * 4;
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u32 shift = (nr % 2) * 16;
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u32 dmars32;
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dmars32 = rz_dmac_ext_readl(dmac, dmars_offset);
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dmars32 &= ~(0xffff << shift);
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dmars32 |= dmars << shift;
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rz_dmac_ext_writel(dmac, dmars32, dmars_offset);
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}
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static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel)
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{
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struct dma_chan *chan = &channel->vc.chan;
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struct rz_dmac *dmac = to_rz_dmac(chan->device);
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struct rz_lmdesc *lmdesc = channel->lmdesc.base;
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struct rz_dmac_desc *d = channel->desc;
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u32 chcfg = CHCFG_MEM_COPY;
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lmdesc = channel->lmdesc.tail;
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/* prepare descriptor */
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lmdesc->sa = d->src;
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lmdesc->da = d->dest;
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lmdesc->tb = d->len;
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lmdesc->chcfg = chcfg;
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lmdesc->chitvl = 0;
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lmdesc->chext = 0;
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lmdesc->header = HEADER_LV;
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rz_dmac_set_dmars_register(dmac, channel->index, 0);
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channel->chcfg = chcfg;
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channel->chctrl = CHCTRL_STG | CHCTRL_SETEN;
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}
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static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
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{
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struct dma_chan *chan = &channel->vc.chan;
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struct rz_dmac *dmac = to_rz_dmac(chan->device);
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struct rz_dmac_desc *d = channel->desc;
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struct scatterlist *sg, *sgl = d->sg;
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struct rz_lmdesc *lmdesc;
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unsigned int i, sg_len = d->sgcount;
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channel->chcfg |= CHCFG_SEL(channel->index) | CHCFG_DEM | CHCFG_DMS;
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if (d->direction == DMA_DEV_TO_MEM) {
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channel->chcfg |= CHCFG_SAD;
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channel->chcfg &= ~CHCFG_REQD;
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} else {
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channel->chcfg |= CHCFG_DAD | CHCFG_REQD;
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}
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lmdesc = channel->lmdesc.tail;
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for (i = 0, sg = sgl; i < sg_len; i++, sg = sg_next(sg)) {
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if (d->direction == DMA_DEV_TO_MEM) {
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lmdesc->sa = channel->src_per_address;
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lmdesc->da = sg_dma_address(sg);
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} else {
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lmdesc->sa = sg_dma_address(sg);
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lmdesc->da = channel->dst_per_address;
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}
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lmdesc->tb = sg_dma_len(sg);
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lmdesc->chitvl = 0;
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lmdesc->chext = 0;
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if (i == (sg_len - 1)) {
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lmdesc->chcfg = (channel->chcfg & ~CHCFG_DEM);
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lmdesc->header = HEADER_LV;
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} else {
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lmdesc->chcfg = channel->chcfg;
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lmdesc->header = HEADER_LV;
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}
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if (++lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
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lmdesc = channel->lmdesc.base;
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}
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channel->lmdesc.tail = lmdesc;
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rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
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channel->chctrl = CHCTRL_SETEN;
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}
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static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan)
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{
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struct rz_dmac_desc *d = chan->desc;
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&chan->vc);
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if (!vd)
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return 0;
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list_del(&vd->node);
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switch (d->type) {
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case RZ_DMAC_DESC_MEMCPY:
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rz_dmac_prepare_desc_for_memcpy(chan);
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break;
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case RZ_DMAC_DESC_SLAVE_SG:
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rz_dmac_prepare_descs_for_slave_sg(chan);
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break;
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default:
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return -EINVAL;
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}
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rz_dmac_enable_hw(chan);
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return 0;
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}
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/*
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* -----------------------------------------------------------------------------
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* DMA engine operations
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*/
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static int rz_dmac_alloc_chan_resources(struct dma_chan *chan)
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{
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struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
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while (channel->descs_allocated < RZ_DMAC_MAX_CHAN_DESCRIPTORS) {
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struct rz_dmac_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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break;
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list_add_tail(&desc->node, &channel->ld_free);
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channel->descs_allocated++;
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}
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if (!channel->descs_allocated)
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return -ENOMEM;
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return channel->descs_allocated;
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}
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static void rz_dmac_free_chan_resources(struct dma_chan *chan)
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{
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struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
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struct rz_dmac *dmac = to_rz_dmac(chan->device);
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struct rz_lmdesc *lmdesc = channel->lmdesc.base;
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struct rz_dmac_desc *desc, *_desc;
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||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
|
||||
spin_lock_irqsave(&channel->vc.lock, flags);
|
||||
|
||||
for (i = 0; i < DMAC_NR_LMDESC; i++)
|
||||
lmdesc[i].header = 0;
|
||||
|
||||
rz_dmac_disable_hw(channel);
|
||||
list_splice_tail_init(&channel->ld_active, &channel->ld_free);
|
||||
list_splice_tail_init(&channel->ld_queue, &channel->ld_free);
|
||||
|
||||
if (channel->mid_rid >= 0) {
|
||||
clear_bit(channel->mid_rid, dmac->modules);
|
||||
channel->mid_rid = -EINVAL;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
|
||||
list_for_each_entry_safe(desc, _desc, &channel->ld_free, node) {
|
||||
kfree(desc);
|
||||
channel->descs_allocated--;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&channel->ld_free);
|
||||
vchan_free_chan_resources(&channel->vc);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *
|
||||
rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
||||
size_t len, unsigned long flags)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
struct rz_dmac *dmac = to_rz_dmac(chan->device);
|
||||
struct rz_dmac_desc *desc;
|
||||
|
||||
dev_dbg(dmac->dev, "%s channel: %d src=0x%pad dst=0x%pad len=%zu\n",
|
||||
__func__, channel->index, &src, &dest, len);
|
||||
|
||||
if (list_empty(&channel->ld_free))
|
||||
return NULL;
|
||||
|
||||
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
|
||||
|
||||
desc->type = RZ_DMAC_DESC_MEMCPY;
|
||||
desc->src = src;
|
||||
desc->dest = dest;
|
||||
desc->len = len;
|
||||
desc->direction = DMA_MEM_TO_MEM;
|
||||
|
||||
list_move_tail(channel->ld_free.next, &channel->ld_queue);
|
||||
return vchan_tx_prep(&channel->vc, &desc->vd, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *
|
||||
rz_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
|
||||
unsigned int sg_len,
|
||||
enum dma_transfer_direction direction,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
struct rz_dmac_desc *desc;
|
||||
struct scatterlist *sg;
|
||||
int dma_length = 0;
|
||||
int i = 0;
|
||||
|
||||
if (list_empty(&channel->ld_free))
|
||||
return NULL;
|
||||
|
||||
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
|
||||
|
||||
for_each_sg(sgl, sg, sg_len, i) {
|
||||
dma_length += sg_dma_len(sg);
|
||||
}
|
||||
|
||||
desc->type = RZ_DMAC_DESC_SLAVE_SG;
|
||||
desc->sg = sgl;
|
||||
desc->sgcount = sg_len;
|
||||
desc->len = dma_length;
|
||||
desc->direction = direction;
|
||||
|
||||
if (direction == DMA_DEV_TO_MEM)
|
||||
desc->src = channel->src_per_address;
|
||||
else
|
||||
desc->dest = channel->dst_per_address;
|
||||
|
||||
list_move_tail(channel->ld_free.next, &channel->ld_queue);
|
||||
return vchan_tx_prep(&channel->vc, &desc->vd, flags);
|
||||
}
|
||||
|
||||
static int rz_dmac_terminate_all(struct dma_chan *chan)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
unsigned long flags;
|
||||
LIST_HEAD(head);
|
||||
|
||||
rz_dmac_disable_hw(channel);
|
||||
spin_lock_irqsave(&channel->vc.lock, flags);
|
||||
list_splice_tail_init(&channel->ld_active, &channel->ld_free);
|
||||
list_splice_tail_init(&channel->ld_queue, &channel->ld_free);
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
vchan_get_all_descriptors(&channel->vc, &head);
|
||||
vchan_dma_desc_free_list(&channel->vc, &head);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rz_dmac_issue_pending(struct dma_chan *chan)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
struct rz_dmac *dmac = to_rz_dmac(chan->device);
|
||||
struct rz_dmac_desc *desc;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&channel->vc.lock, flags);
|
||||
|
||||
if (!list_empty(&channel->ld_queue)) {
|
||||
desc = list_first_entry(&channel->ld_queue,
|
||||
struct rz_dmac_desc, node);
|
||||
channel->desc = desc;
|
||||
if (vchan_issue_pending(&channel->vc)) {
|
||||
if (rz_dmac_xfer_desc(channel) < 0)
|
||||
dev_warn(dmac->dev, "ch: %d couldn't issue DMA xfer\n",
|
||||
channel->index);
|
||||
else
|
||||
list_move_tail(channel->ld_queue.next,
|
||||
&channel->ld_active);
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
}
|
||||
|
||||
static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds)
|
||||
{
|
||||
u8 i;
|
||||
const enum dma_slave_buswidth ds_lut[] = {
|
||||
DMA_SLAVE_BUSWIDTH_1_BYTE,
|
||||
DMA_SLAVE_BUSWIDTH_2_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_4_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_8_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_16_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_32_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_64_BYTES,
|
||||
DMA_SLAVE_BUSWIDTH_128_BYTES,
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ds_lut); i++) {
|
||||
if (ds_lut[i] == ds)
|
||||
return i;
|
||||
}
|
||||
|
||||
return CHCFG_DS_INVALID;
|
||||
}
|
||||
|
||||
static int rz_dmac_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *config)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
u32 val;
|
||||
|
||||
channel->src_per_address = config->src_addr;
|
||||
channel->src_word_size = config->src_addr_width;
|
||||
channel->dst_per_address = config->dst_addr;
|
||||
channel->dst_word_size = config->dst_addr_width;
|
||||
|
||||
val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
|
||||
if (val == CHCFG_DS_INVALID)
|
||||
return -EINVAL;
|
||||
|
||||
channel->chcfg |= CHCFG_FILL_DDS(val);
|
||||
|
||||
val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
|
||||
if (val == CHCFG_DS_INVALID)
|
||||
return -EINVAL;
|
||||
|
||||
channel->chcfg |= CHCFG_FILL_SDS(val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rz_dmac_virt_desc_free(struct virt_dma_desc *vd)
|
||||
{
|
||||
/*
|
||||
* Place holder
|
||||
* Descriptor allocation is done during alloc_chan_resources and
|
||||
* get freed during free_chan_resources.
|
||||
* list is used to manage the descriptors and avoid any memory
|
||||
* allocation/free during DMA read/write.
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* -----------------------------------------------------------------------------
|
||||
* IRQ handling
|
||||
*/
|
||||
|
||||
static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel)
|
||||
{
|
||||
struct dma_chan *chan = &channel->vc.chan;
|
||||
struct rz_dmac *dmac = to_rz_dmac(chan->device);
|
||||
u32 chstat, chctrl;
|
||||
|
||||
chstat = rz_dmac_ch_readl(channel, CHSTAT, 1);
|
||||
if (chstat & CHSTAT_ER) {
|
||||
dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n",
|
||||
channel->index, chstat);
|
||||
rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
|
||||
goto done;
|
||||
}
|
||||
|
||||
chctrl = rz_dmac_ch_readl(channel, CHCTRL, 1);
|
||||
rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1);
|
||||
done:
|
||||
return;
|
||||
}
|
||||
|
||||
static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct rz_dmac_chan *channel = dev_id;
|
||||
|
||||
if (channel) {
|
||||
rz_dmac_irq_handle_channel(channel);
|
||||
return IRQ_WAKE_THREAD;
|
||||
}
|
||||
/* handle DMAERR irq */
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t rz_dmac_irq_handler_thread(int irq, void *dev_id)
|
||||
{
|
||||
struct rz_dmac_chan *channel = dev_id;
|
||||
struct rz_dmac_desc *desc = NULL;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&channel->vc.lock, flags);
|
||||
|
||||
if (list_empty(&channel->ld_active)) {
|
||||
/* Someone might have called terminate all */
|
||||
goto out;
|
||||
}
|
||||
|
||||
desc = list_first_entry(&channel->ld_active, struct rz_dmac_desc, node);
|
||||
vchan_cookie_complete(&desc->vd);
|
||||
list_move_tail(channel->ld_active.next, &channel->ld_free);
|
||||
if (!list_empty(&channel->ld_queue)) {
|
||||
desc = list_first_entry(&channel->ld_queue, struct rz_dmac_desc,
|
||||
node);
|
||||
channel->desc = desc;
|
||||
if (rz_dmac_xfer_desc(channel) == 0)
|
||||
list_move_tail(channel->ld_queue.next, &channel->ld_active);
|
||||
}
|
||||
out:
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* -----------------------------------------------------------------------------
|
||||
* OF xlate and channel filter
|
||||
*/
|
||||
|
||||
static bool rz_dmac_chan_filter(struct dma_chan *chan, void *arg)
|
||||
{
|
||||
struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
|
||||
struct rz_dmac *dmac = to_rz_dmac(chan->device);
|
||||
struct of_phandle_args *dma_spec = arg;
|
||||
u32 ch_cfg;
|
||||
|
||||
channel->mid_rid = dma_spec->args[0] & MID_RID_MASK;
|
||||
ch_cfg = (dma_spec->args[0] & CHCFG_MASK) >> 10;
|
||||
channel->chcfg = CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) |
|
||||
CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg);
|
||||
|
||||
return !test_and_set_bit(channel->mid_rid, dmac->modules);
|
||||
}
|
||||
|
||||
static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
if (dma_spec->args_count != 1)
|
||||
return NULL;
|
||||
|
||||
/* Only slave DMA channels can be allocated via DT */
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
|
||||
return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec);
|
||||
}
|
||||
|
||||
/*
|
||||
* -----------------------------------------------------------------------------
|
||||
* Probe and remove
|
||||
*/
|
||||
|
||||
static int rz_dmac_chan_probe(struct rz_dmac *dmac,
|
||||
struct rz_dmac_chan *channel,
|
||||
unsigned int index)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dmac->dev);
|
||||
struct rz_lmdesc *lmdesc;
|
||||
char pdev_irqname[5];
|
||||
char *irqname;
|
||||
int ret;
|
||||
|
||||
channel->index = index;
|
||||
channel->mid_rid = -EINVAL;
|
||||
|
||||
/* Request the channel interrupt. */
|
||||
sprintf(pdev_irqname, "ch%u", index);
|
||||
channel->irq = platform_get_irq_byname(pdev, pdev_irqname);
|
||||
if (channel->irq < 0)
|
||||
return channel->irq;
|
||||
|
||||
irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
|
||||
dev_name(dmac->dev), index);
|
||||
if (!irqname)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = devm_request_threaded_irq(dmac->dev, channel->irq,
|
||||
rz_dmac_irq_handler,
|
||||
rz_dmac_irq_handler_thread, 0,
|
||||
irqname, channel);
|
||||
if (ret) {
|
||||
dev_err(dmac->dev, "failed to request IRQ %u (%d)\n",
|
||||
channel->irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set io base address for each channel */
|
||||
if (index < 8) {
|
||||
channel->ch_base = dmac->base + CHANNEL_0_7_OFFSET +
|
||||
EACH_CHANNEL_OFFSET * index;
|
||||
channel->ch_cmn_base = dmac->base + CHANNEL_0_7_COMMON_BASE;
|
||||
} else {
|
||||
channel->ch_base = dmac->base + CHANNEL_8_15_OFFSET +
|
||||
EACH_CHANNEL_OFFSET * (index - 8);
|
||||
channel->ch_cmn_base = dmac->base + CHANNEL_8_15_COMMON_BASE;
|
||||
}
|
||||
|
||||
/* Allocate descriptors */
|
||||
lmdesc = dma_alloc_coherent(&pdev->dev,
|
||||
sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
|
||||
&channel->lmdesc.base_dma, GFP_KERNEL);
|
||||
if (!lmdesc) {
|
||||
dev_err(&pdev->dev, "Can't allocate memory (lmdesc)\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
rz_lmdesc_setup(channel, lmdesc);
|
||||
|
||||
/* Initialize register for each channel */
|
||||
rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
|
||||
|
||||
channel->vc.desc_free = rz_dmac_virt_desc_free;
|
||||
vchan_init(&channel->vc, &dmac->engine);
|
||||
INIT_LIST_HEAD(&channel->ld_queue);
|
||||
INIT_LIST_HEAD(&channel->ld_free);
|
||||
INIT_LIST_HEAD(&channel->ld_active);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "unable to read dma-channels property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!dmac->n_channels || dmac->n_channels > RZ_DMAC_MAX_CHANNELS) {
|
||||
dev_err(dev, "invalid number of channels %u\n", dmac->n_channels);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rz_dmac_probe(struct platform_device *pdev)
|
||||
{
|
||||
const char *irqname = "error";
|
||||
struct dma_device *engine;
|
||||
struct rz_dmac *dmac;
|
||||
int channel_num;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
int irq;
|
||||
|
||||
dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
|
||||
if (!dmac)
|
||||
return -ENOMEM;
|
||||
|
||||
dmac->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, dmac);
|
||||
|
||||
ret = rz_dmac_parse_of(&pdev->dev, dmac);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
|
||||
sizeof(*dmac->channels), GFP_KERNEL);
|
||||
if (!dmac->channels)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Request resources */
|
||||
dmac->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(dmac->base))
|
||||
return PTR_ERR(dmac->base);
|
||||
|
||||
dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(dmac->ext_base))
|
||||
return PTR_ERR(dmac->ext_base);
|
||||
|
||||
/* Register interrupt handler for error */
|
||||
irq = platform_get_irq_byname(pdev, irqname);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0,
|
||||
irqname, NULL);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
|
||||
irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize the channels. */
|
||||
INIT_LIST_HEAD(&dmac->engine.channels);
|
||||
|
||||
for (i = 0; i < dmac->n_channels; i++) {
|
||||
ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Register the DMAC as a DMA provider for DT. */
|
||||
ret = of_dma_controller_register(pdev->dev.of_node, rz_dmac_of_xlate,
|
||||
NULL);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
/* Register the DMA engine device. */
|
||||
engine = &dmac->engine;
|
||||
dma_cap_set(DMA_SLAVE, engine->cap_mask);
|
||||
dma_cap_set(DMA_MEMCPY, engine->cap_mask);
|
||||
rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL);
|
||||
rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL);
|
||||
|
||||
engine->dev = &pdev->dev;
|
||||
|
||||
engine->device_alloc_chan_resources = rz_dmac_alloc_chan_resources;
|
||||
engine->device_free_chan_resources = rz_dmac_free_chan_resources;
|
||||
engine->device_tx_status = dma_cookie_status;
|
||||
engine->device_prep_slave_sg = rz_dmac_prep_slave_sg;
|
||||
engine->device_prep_dma_memcpy = rz_dmac_prep_dma_memcpy;
|
||||
engine->device_config = rz_dmac_config;
|
||||
engine->device_terminate_all = rz_dmac_terminate_all;
|
||||
engine->device_issue_pending = rz_dmac_issue_pending;
|
||||
|
||||
engine->copy_align = DMAENGINE_ALIGN_1_BYTE;
|
||||
dma_set_max_seg_size(engine->dev, U32_MAX);
|
||||
|
||||
ret = dma_async_device_register(engine);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to register\n");
|
||||
goto dma_register_err;
|
||||
}
|
||||
return 0;
|
||||
|
||||
dma_register_err:
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
err:
|
||||
channel_num = i ? i - 1 : 0;
|
||||
for (i = 0; i < channel_num; i++) {
|
||||
struct rz_dmac_chan *channel = &dmac->channels[i];
|
||||
|
||||
dma_free_coherent(NULL,
|
||||
sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
|
||||
channel->lmdesc.base,
|
||||
channel->lmdesc.base_dma);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rz_dmac_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rz_dmac *dmac = platform_get_drvdata(pdev);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < dmac->n_channels; i++) {
|
||||
struct rz_dmac_chan *channel = &dmac->channels[i];
|
||||
|
||||
dma_free_coherent(NULL,
|
||||
sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
|
||||
channel->lmdesc.base,
|
||||
channel->lmdesc.base_dma);
|
||||
}
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
dma_async_device_unregister(&dmac->engine);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_rz_dmac_match[] = {
|
||||
{ .compatible = "renesas,rz-dmac", },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_rz_dmac_match);
|
||||
|
||||
static struct platform_driver rz_dmac_driver = {
|
||||
.driver = {
|
||||
.name = "rz-dmac",
|
||||
.of_match_table = of_rz_dmac_match,
|
||||
},
|
||||
.probe = rz_dmac_probe,
|
||||
.remove = rz_dmac_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(rz_dmac_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RZ/G2L DMA Controller Driver");
|
||||
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user