skge: XM PHY handling fixes
Change how PHY is managed on SysKonnect fibre based boards. Poll for PHY coming up 1 per second, but use interrupt to detect loss. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
60b24b5179
commit
501fb72d05
@ -57,7 +57,7 @@
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#define TX_WATCHDOG (5 * HZ)
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#define NAPI_WEIGHT 64
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#define BLINK_MS 250
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#define LINK_HZ (HZ/2)
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#define LINK_HZ HZ
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MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
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MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
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@ -995,19 +995,15 @@ static void xm_link_down(struct skge_hw *hw, int port)
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{
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struct net_device *dev = hw->dev[port];
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struct skge_port *skge = netdev_priv(dev);
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u16 cmd, msk;
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u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
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if (hw->phy_type == SK_PHY_XMAC) {
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msk = xm_read16(hw, port, XM_IMSK);
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msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
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xm_write16(hw, port, XM_IMSK, msk);
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}
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xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
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cmd = xm_read16(hw, port, XM_MMU_CMD);
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cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
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xm_write16(hw, port, XM_MMU_CMD, cmd);
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/* dummy read to ensure writing */
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(void) xm_read16(hw, port, XM_MMU_CMD);
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xm_read16(hw, port, XM_MMU_CMD);
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if (netif_carrier_ok(dev))
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skge_link_down(skge);
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@ -1103,7 +1099,7 @@ static void genesis_reset(struct skge_hw *hw, int port)
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/* reset the statistics module */
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xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
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xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
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xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
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xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
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xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
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xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
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@ -1141,7 +1137,7 @@ static void bcom_check_link(struct skge_hw *hw, int port)
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u16 status;
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/* read twice because of latch */
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(void) xm_phy_read(hw, port, PHY_BCOM_STAT);
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xm_phy_read(hw, port, PHY_BCOM_STAT);
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status = xm_phy_read(hw, port, PHY_BCOM_STAT);
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if ((status & PHY_ST_LSYNC) == 0) {
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@ -1342,7 +1338,7 @@ static void xm_phy_init(struct skge_port *skge)
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mod_timer(&skge->link_timer, jiffies + LINK_HZ);
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}
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static void xm_check_link(struct net_device *dev)
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static int xm_check_link(struct net_device *dev)
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{
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struct skge_port *skge = netdev_priv(dev);
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struct skge_hw *hw = skge->hw;
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@ -1350,25 +1346,25 @@ static void xm_check_link(struct net_device *dev)
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u16 status;
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/* read twice because of latch */
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(void) xm_phy_read(hw, port, PHY_XMAC_STAT);
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xm_phy_read(hw, port, PHY_XMAC_STAT);
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status = xm_phy_read(hw, port, PHY_XMAC_STAT);
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if ((status & PHY_ST_LSYNC) == 0) {
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xm_link_down(hw, port);
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return;
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return 0;
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}
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if (skge->autoneg == AUTONEG_ENABLE) {
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u16 lpa, res;
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if (!(status & PHY_ST_AN_OVER))
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return;
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return 0;
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lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
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if (lpa & PHY_B_AN_RF) {
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printk(KERN_NOTICE PFX "%s: remote fault\n",
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dev->name);
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return;
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return 0;
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}
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res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
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@ -1384,7 +1380,7 @@ static void xm_check_link(struct net_device *dev)
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default:
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printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
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dev->name);
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return;
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return 0;
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}
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/* We are using IEEE 802.3z/D5.0 Table 37-4 */
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@ -1408,11 +1404,14 @@ static void xm_check_link(struct net_device *dev)
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if (!netif_carrier_ok(dev))
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genesis_link_up(skge);
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return 1;
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}
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/* Poll to check for link coming up.
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*
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* Since internal PHY is wired to a level triggered pin, can't
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* get an interrupt when carrier is detected.
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* get an interrupt when carrier is detected, need to poll for
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* link coming up.
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*/
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static void xm_link_timer(unsigned long arg)
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{
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@ -1420,29 +1419,35 @@ static void xm_link_timer(unsigned long arg)
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struct net_device *dev = skge->netdev;
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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int i;
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unsigned long flags;
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if (!netif_running(dev))
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return;
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if (netif_carrier_ok(dev)) {
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xm_read16(hw, port, XM_ISRC);
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if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
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goto nochange;
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} else {
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if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
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goto nochange;
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xm_read16(hw, port, XM_ISRC);
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if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
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goto nochange;
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spin_lock_irqsave(&hw->phy_lock, flags);
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/*
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* Verify that the link by checking GPIO register three times.
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* This pin has the signal from the link_sync pin connected to it.
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*/
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for (i = 0; i < 3; i++) {
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if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
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goto link_down;
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}
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spin_lock(&hw->phy_lock);
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xm_check_link(dev);
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spin_unlock(&hw->phy_lock);
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nochange:
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if (netif_running(dev))
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mod_timer(&skge->link_timer, jiffies + LINK_HZ);
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/* Re-enable interrupt to detect link down */
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if (xm_check_link(dev)) {
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u16 msk = xm_read16(hw, port, XM_IMSK);
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msk &= ~XM_IS_INP_ASS;
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xm_write16(hw, port, XM_IMSK, msk);
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xm_read16(hw, port, XM_ISRC);
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} else {
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link_down:
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mod_timer(&skge->link_timer,
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round_jiffies(jiffies + LINK_HZ));
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}
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spin_unlock_irqrestore(&hw->phy_lock, flags);
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}
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static void genesis_mac_init(struct skge_hw *hw, int port)
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@ -1686,14 +1691,16 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
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printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
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skge->netdev->name, status);
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if (hw->phy_type == SK_PHY_XMAC &&
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(status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
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xm_link_down(hw, port);
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if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
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xm_link_down(hw, port);
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mod_timer(&skge->link_timer, jiffies + 1);
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}
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if (status & XM_IS_TXF_UR) {
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xm_write32(hw, port, XM_MODE, XM_MD_FTF);
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++skge->net_stats.tx_fifo_errors;
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}
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if (status & XM_IS_RXF_OV) {
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xm_write32(hw, port, XM_MODE, XM_MD_FRF);
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++skge->net_stats.rx_fifo_errors;
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@ -1753,11 +1760,12 @@ static void genesis_link_up(struct skge_port *skge)
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}
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xm_write32(hw, port, XM_MODE, mode);
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msk = XM_DEF_MSK;
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if (hw->phy_type != SK_PHY_XMAC)
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msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
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/* Turn on detection of Tx underrun, Rx overrun */
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msk = xm_read16(hw, port, XM_IMSK);
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msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
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xm_write16(hw, port, XM_IMSK, msk);
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xm_read16(hw, port, XM_ISRC);
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/* get MMU Command Reg. */
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@ -2191,12 +2191,10 @@ enum {
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XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
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XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
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XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
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XM_IMSK_DISABLE = 0xffff,
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};
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#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | \
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XM_IS_RXF_OV | XM_IS_TXF_UR))
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/* XM_HW_CFG 16 bit r/w Hardware Config Register */
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enum {
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XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
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