Merge branch kvm-arm64/6.6/pmu-fixes into kvmarm-master/next
* kvm-arm64/6.6/pmu-fixes: : . : Another set of PMU fixes, coutrtesy of Reiji Watanabe. : From the cover letter: : : "This series fixes a couple of PMUver related handling of : vPMU support. : : On systems where the PMUVer is not uniform across all PEs, : KVM currently does not advertise PMUv3 to the guest, : even if userspace successfully runs KVM_ARM_VCPU_INIT with : KVM_ARM_VCPU_PMU_V3." : : Additionally, a fix for an obscure counter oversubscription : issue happening when the hsot profines the guest's EL0. : . KVM: arm64: pmu: Guard PMU emulation definitions with CONFIG_KVM KVM: arm64: pmu: Resync EL0 state on counter rotation KVM: arm64: PMU: Don't advertise STALL_SLOT_{FRONTEND,BACKEND} KVM: arm64: PMU: Don't advertise the STALL_SLOT event KVM: arm64: PMU: Avoid inappropriate use of host's PMUVer KVM: arm64: PMU: Disallow vPMU on non-uniform PMUVer Signed-off-by: Marc Zyngier <maz@kernel.org>
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commit
50a40ff7d3
@ -227,6 +227,8 @@ static inline bool kvm_set_pmuserenr(u64 val)
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return false;
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}
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static inline void kvm_vcpu_pmu_resync_el0(void) {}
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/* PMU Version in DFR Register */
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#define ARMV8_PMU_DFR_VER_NI 0
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#define ARMV8_PMU_DFR_VER_V3P4 0x5
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@ -49,6 +49,7 @@
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#define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
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#define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
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#define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
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#define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
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#define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
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KVM_DIRTY_LOG_INITIALLY_SET)
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@ -804,6 +804,9 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu)
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kvm_pmu_handle_pmcr(vcpu,
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__vcpu_sys_reg(vcpu, PMCR_EL0));
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if (kvm_check_request(KVM_REQ_RESYNC_PMU_EL0, vcpu))
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kvm_vcpu_pmu_restore_guest(vcpu);
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if (kvm_check_request(KVM_REQ_SUSPEND, vcpu))
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return kvm_vcpu_suspend(vcpu);
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@ -14,6 +14,7 @@
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#include <asm/kvm_emulate.h>
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#include <kvm/arm_pmu.h>
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#include <kvm/arm_vgic.h>
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#include <asm/arm_pmuv3.h>
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#define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0)
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@ -35,12 +36,8 @@ static struct kvm_pmc *kvm_vcpu_idx_to_pmc(struct kvm_vcpu *vcpu, int cnt_idx)
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return &vcpu->arch.pmu.pmc[cnt_idx];
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}
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static u32 kvm_pmu_event_mask(struct kvm *kvm)
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static u32 __kvm_pmu_event_mask(unsigned int pmuver)
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{
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unsigned int pmuver;
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pmuver = kvm->arch.arm_pmu->pmuver;
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switch (pmuver) {
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case ID_AA64DFR0_EL1_PMUVer_IMP:
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return GENMASK(9, 0);
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@ -55,6 +52,14 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
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}
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}
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static u32 kvm_pmu_event_mask(struct kvm *kvm)
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{
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u64 dfr0 = IDREG(kvm, SYS_ID_AA64DFR0_EL1);
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u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, dfr0);
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return __kvm_pmu_event_mask(pmuver);
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}
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/**
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* kvm_pmc_is_64bit - determine if counter is 64bit
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* @pmc: counter context
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@ -672,8 +677,11 @@ void kvm_host_pmu_init(struct arm_pmu *pmu)
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{
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struct arm_pmu_entry *entry;
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if (pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_NI ||
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pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
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/*
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* Check the sanitised PMU version for the system, as KVM does not
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* support implementations where PMUv3 exists on a subset of CPUs.
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*/
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if (!pmuv3_implemented(kvm_arm_pmu_get_pmuver_limit()))
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return;
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mutex_lock(&arm_pmus_lock);
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@ -750,11 +758,12 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
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} else {
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val = read_sysreg(pmceid1_el0);
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/*
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* Don't advertise STALL_SLOT, as PMMIR_EL0 is handled
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* Don't advertise STALL_SLOT*, as PMMIR_EL0 is handled
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* as RAZ
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*/
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if (vcpu->kvm->arch.arm_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4)
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val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32);
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val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) |
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BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) |
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BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32));
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base = 32;
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}
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@ -950,11 +959,17 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
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return 0;
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}
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case KVM_ARM_VCPU_PMU_V3_FILTER: {
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u8 pmuver = kvm_arm_pmu_get_pmuver_limit();
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struct kvm_pmu_event_filter __user *uaddr;
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struct kvm_pmu_event_filter filter;
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int nr_events;
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nr_events = kvm_pmu_event_mask(kvm) + 1;
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/*
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* Allow userspace to specify an event filter for the entire
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* event range supported by PMUVer of the hardware, rather
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* than the guest's PMUVer for KVM backward compatibility.
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*/
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nr_events = __kvm_pmu_event_mask(pmuver) + 1;
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uaddr = (struct kvm_pmu_event_filter __user *)(long)attr->addr;
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@ -236,3 +236,21 @@ bool kvm_set_pmuserenr(u64 val)
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ctxt_sys_reg(hctxt, PMUSERENR_EL0) = val;
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return true;
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}
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/*
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* If we interrupted the guest to update the host PMU context, make
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* sure we re-apply the guest EL0 state.
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*/
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void kvm_vcpu_pmu_resync_el0(void)
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{
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struct kvm_vcpu *vcpu;
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if (!has_vhe() || !in_interrupt())
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return;
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vcpu = kvm_get_running_vcpu();
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if (!vcpu)
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return;
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kvm_make_request(KVM_REQ_RESYNC_PMU_EL0, vcpu);
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}
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@ -772,6 +772,8 @@ static void armv8pmu_start(struct arm_pmu *cpu_pmu)
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/* Enable all counters */
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armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
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kvm_vcpu_pmu_resync_el0();
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}
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static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
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@ -12,7 +12,7 @@
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#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
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#ifdef CONFIG_HW_PERF_EVENTS
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#if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM)
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struct kvm_pmc {
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u8 idx; /* index into the pmu->pmc array */
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@ -74,6 +74,7 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
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struct kvm_pmu_events *kvm_get_pmu_events(void);
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void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
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void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
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void kvm_vcpu_pmu_resync_el0(void);
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#define kvm_vcpu_has_pmu(vcpu) \
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(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
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@ -171,6 +172,7 @@ static inline u8 kvm_arm_pmu_get_pmuver_limit(void)
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{
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return 0;
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}
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static inline void kvm_vcpu_pmu_resync_el0(void) {}
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#endif
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