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drm/xe: Drop TLB invalidation from ring operations

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Now that we issue TLB invalidations on unbinds and rebind from execs we
no longer need to issue TLB invalidations from the ring operations.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
This commit is contained in:
Matthew Brost 2023-01-26 10:40:41 -08:00 committed by Rodrigo Vivi
parent 5387e865d9
commit 50a48cca60
1 changed files with 1 additions and 39 deletions
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40
drivers/gpu/drm/xe/xe_ring_ops.c
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@ -83,31 +83,6 @@ static int emit_flush_invalidate(u32 flag, u32 *dw, int i)
return i;
}
static int emit_pipe_invalidate(u32 mask_flags, u32 *dw, int i)
{
u32 flags = PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_VF_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_STORE_DATA_INDEX;
flags &= ~mask_flags;
dw[i++] = GFX_OP_PIPE_CONTROL(6);
dw[i++] = flags;
dw[i++] = LRC_PPHWSP_SCRATCH_ADDR;
dw[i++] = 0;
dw[i++] = 0;
dw[i++] = 0;
return i;
}
#define MI_STORE_QWORD_IMM_GEN8_POSTED (MI_INSTR(0x20, 3) | (1 << 21))
static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
@ -148,11 +123,6 @@ static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc,
u32 dw[MAX_JOB_SIZE_DW], i = 0;
u32 ppgtt_flag = get_ppgtt_flag(job);
/* XXX: Conditional flushing possible */
dw[i++] = preparser_disable(true);
i = emit_flush_invalidate(0, dw, i);
dw[i++] = preparser_disable(false);
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
seqno, dw, i);
@ -181,9 +151,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
struct xe_device *xe = gt_to_xe(gt);
bool decode = job->engine->class == XE_ENGINE_CLASS_VIDEO_DECODE;
/* XXX: Conditional flushing possible */
dw[i++] = preparser_disable(true);
i = emit_flush_invalidate(decode ? MI_INVALIDATE_BSD : 0, dw, i);
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs) {
if (decode)
@ -244,15 +212,8 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
struct xe_gt *gt = job->engine->gt;
struct xe_device *xe = gt_to_xe(gt);
bool pvc = xe->info.platform == XE_PVC;
u32 mask_flags = 0;
/* XXX: Conditional flushing possible */
dw[i++] = preparser_disable(true);
if (pvc)
mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE)
mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS;
i = emit_pipe_invalidate(mask_flags, dw, i);
/* Wa_1809175790 */
if (!xe->info.has_flat_ccs)
i = emit_aux_table_inv(gt, GEN12_CCS_AUX_INV.reg, dw, i);
@ -287,6 +248,7 @@ static void emit_migration_job_gen12(struct xe_sched_job *job,
i = emit_bb_start(job->batch_addr[0], BIT(8), dw, i);
/* XXX: Do we need this? Leaving for now. */
dw[i++] = preparser_disable(true);
i = emit_flush_invalidate(0, dw, i);
dw[i++] = preparser_disable(false);