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powerpc sstep: Add support for prefixed load/stores

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This adds emulation support for the following prefixed integer
load/stores:
  * Prefixed Load Byte and Zero (plbz)
  * Prefixed Load Halfword and Zero (plhz)
  * Prefixed Load Halfword Algebraic (plha)
  * Prefixed Load Word and Zero (plwz)
  * Prefixed Load Word Algebraic (plwa)
  * Prefixed Load Doubleword (pld)
  * Prefixed Store Byte (pstb)
  * Prefixed Store Halfword (psth)
  * Prefixed Store Word (pstw)
  * Prefixed Store Doubleword (pstd)
  * Prefixed Load Quadword (plq)
  * Prefixed Store Quadword (pstq)

the follow prefixed floating-point load/stores:
  * Prefixed Load Floating-Point Single (plfs)
  * Prefixed Load Floating-Point Double (plfd)
  * Prefixed Store Floating-Point Single (pstfs)
  * Prefixed Store Floating-Point Double (pstfd)

and for the following prefixed VSX load/stores:
  * Prefixed Load VSX Scalar Doubleword (plxsd)
  * Prefixed Load VSX Scalar Single-Precision (plxssp)
  * Prefixed Load VSX Vector [0|1]  (plxv, plxv0, plxv1)
  * Prefixed Store VSX Scalar Doubleword (pstxsd)
  * Prefixed Store VSX Scalar Single-Precision (pstxssp)
  * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Reviewed-by: Balamuruhan S <bala24@linux.ibm.com>
[mpe: Use CONFIG_PPC64 not __powerpc64__, use get_op()]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200506034050.24806-30-jniethe5@gmail.com
This commit is contained in:
Jordan Niethe 2020-05-06 13:40:49 +10:00 committed by Michael Ellerman
parent 9409d2f9da
commit 50b80a12e4
2 changed files with 166 additions and 2 deletions
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4
arch/powerpc/include/asm/sstep.h
View File

@ -90,11 +90,15 @@ enum instruction_type {
#define VSX_LDLEFT 4 /* load VSX register from left */ #define VSX_LDLEFT 4 /* load VSX register from left */
#define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */
/* Prefixed flag, ORed in with type */
#define PREFIXED 0x800
/* Size field in type word */ /* Size field in type word */
#define SIZE(n) ((n) << 12) #define SIZE(n) ((n) << 12)
#define GETSIZE(w) ((w) >> 12) #define GETSIZE(w) ((w) >> 12)
#define GETTYPE(t) ((t) & INSTR_TYPE_MASK) #define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
#define GETLENGTH(t) (((t) & PREFIXED) ? 8 : 4)
#define MKOP(t, f, s) ((t) | (f) | SIZE(s)) #define MKOP(t, f, s) ((t) | (f) | SIZE(s))

164
arch/powerpc/lib/sstep.c
View File

@ -13,6 +13,7 @@
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <asm/cpu_has_feature.h> #include <asm/cpu_has_feature.h>
#include <asm/cputable.h> #include <asm/cputable.h>
#include <asm/disassemble.h>
extern char system_call_common[]; extern char system_call_common[];
@ -187,6 +188,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned int instr,
return ea; return ea;
} }
/*
* Calculate effective address for a MLS:D-form / 8LS:D-form
* prefixed instruction
*/
static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
unsigned int suffix,
const struct pt_regs *regs)
{
int ra, prefix_r;
unsigned int dd;
unsigned long ea, d0, d1, d;
prefix_r = instr & (1ul << 20);
ra = (suffix >> 16) & 0x1f;
d0 = instr & 0x3ffff;
d1 = suffix & 0xffff;
d = (d0 << 16) | d1;
/*
* sign extend a 34 bit number
*/
dd = (unsigned int)(d >> 2);
ea = (signed int)dd;
ea = (ea << 2) | (d & 0x3);
if (!prefix_r && ra)
ea += regs->gpr[ra];
else if (!prefix_r && !ra)
; /* Leave ea as is */
else if (prefix_r && !ra)
ea += regs->nip;
else if (prefix_r && ra)
; /* Invalid form. Should already be checked for by caller! */
return ea;
}
/* /*
* Return the largest power of 2, not greater than sizeof(unsigned long), * Return the largest power of 2, not greater than sizeof(unsigned long),
* such that x is a multiple of it. * such that x is a multiple of it.
@ -1165,6 +1204,9 @@ static nokprobe_inline int trap_compare(long v1, long v2)
int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
struct ppc_inst instr) struct ppc_inst instr)
{ {
#ifdef CONFIG_PPC64
unsigned int suffixopcode, prefixtype, prefix_r;
#endif
unsigned int opcode, ra, rb, rc, rd, spr, u; unsigned int opcode, ra, rb, rc, rd, spr, u;
unsigned long int imm; unsigned long int imm;
unsigned long int val, val2; unsigned long int val, val2;
@ -2652,6 +2694,124 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
break; break;
} }
break; break;
case 1: /* Prefixed instructions */
prefix_r = word & (1ul << 20);
ra = (suffix >> 16) & 0x1f;
op->update_reg = ra;
rd = (suffix >> 21) & 0x1f;
op->reg = rd;
op->val = regs->gpr[rd];
suffixopcode = get_op(suffix);
prefixtype = (word >> 24) & 0x3;
switch (prefixtype) {
case 0: /* Type 00 Eight-Byte Load/Store */
if (prefix_r && ra)
break;
op->ea = mlsd_8lsd_ea(word, suffix, regs);
switch (suffixopcode) {
case 41: /* plwa */
op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
break;
case 42: /* plxsd */
op->reg = rd + 32;
op->type = MKOP(LOAD_VSX, PREFIXED, 8);
op->element_size = 8;
op->vsx_flags = VSX_CHECK_VEC;
break;
case 43: /* plxssp */
op->reg = rd + 32;
op->type = MKOP(LOAD_VSX, PREFIXED, 4);
op->element_size = 8;
op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
break;
case 46: /* pstxsd */
op->reg = rd + 32;
op->type = MKOP(STORE_VSX, PREFIXED, 8);
op->element_size = 8;
op->vsx_flags = VSX_CHECK_VEC;
break;
case 47: /* pstxssp */
op->reg = rd + 32;
op->type = MKOP(STORE_VSX, PREFIXED, 4);
op->element_size = 8;
op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
break;
case 51: /* plxv1 */
op->reg += 32;
fallthrough;
case 50: /* plxv0 */
op->type = MKOP(LOAD_VSX, PREFIXED, 16);
op->element_size = 16;
op->vsx_flags = VSX_CHECK_VEC;
break;
case 55: /* pstxv1 */
op->reg = rd + 32;
fallthrough;
case 54: /* pstxv0 */
op->type = MKOP(STORE_VSX, PREFIXED, 16);
op->element_size = 16;
op->vsx_flags = VSX_CHECK_VEC;
break;
case 56: /* plq */
op->type = MKOP(LOAD, PREFIXED, 16);
break;
case 57: /* pld */
op->type = MKOP(LOAD, PREFIXED, 8);
break;
case 60: /* stq */
op->type = MKOP(STORE, PREFIXED, 16);
break;
case 61: /* pstd */
op->type = MKOP(STORE, PREFIXED, 8);
break;
}
break;
case 1: /* Type 01 Eight-Byte Register-to-Register */
break;
case 2: /* Type 10 Modified Load/Store */
if (prefix_r && ra)
break;
op->ea = mlsd_8lsd_ea(word, suffix, regs);
switch (suffixopcode) {
case 32: /* plwz */
op->type = MKOP(LOAD, PREFIXED, 4);
break;
case 34: /* plbz */
op->type = MKOP(LOAD, PREFIXED, 1);
break;
case 36: /* pstw */
op->type = MKOP(STORE, PREFIXED, 4);
break;
case 38: /* pstb */
op->type = MKOP(STORE, PREFIXED, 1);
break;
case 40: /* plhz */
op->type = MKOP(LOAD, PREFIXED, 2);
break;
case 42: /* plha */
op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
break;
case 44: /* psth */
op->type = MKOP(STORE, PREFIXED, 2);
break;
case 48: /* plfs */
op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
break;
case 50: /* plfd */
op->type = MKOP(LOAD_FP, PREFIXED, 8);
break;
case 52: /* pstfs */
op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
break;
case 54: /* pstfd */
op->type = MKOP(STORE_FP, PREFIXED, 8);
break;
}
break;
case 3: /* Type 11 Modified Register-to-Register */
break;
}
#endif /* __powerpc64__ */ #endif /* __powerpc64__ */
} }
@ -2760,7 +2920,7 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
{ {
unsigned long next_pc; unsigned long next_pc;
next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
switch (GETTYPE(op->type)) { switch (GETTYPE(op->type)) {
case COMPUTE: case COMPUTE:
if (op->type & SETREG) if (op->type & SETREG)
@ -3205,7 +3365,7 @@ int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
return 0; return 0;
instr_done: instr_done:
regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
return 1; return 1;
} }
NOKPROBE_SYMBOL(emulate_step); NOKPROBE_SYMBOL(emulate_step);