drm/nouveau/fifo/nv50-: rip out dma channels
I honestly don't even know why... These have never been used. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs
parent
e78b1b545c
commit
50c4a64491
@ -61,8 +61,6 @@
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#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
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#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
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#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
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#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
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#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
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#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
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#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
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@ -27,8 +27,6 @@ nvkm-y += nvkm/engine/fifo/dmanv04.o
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nvkm-y += nvkm/engine/fifo/dmanv10.o
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nvkm-y += nvkm/engine/fifo/dmanv17.o
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nvkm-y += nvkm/engine/fifo/dmanv40.o
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nvkm-y += nvkm/engine/fifo/dmanv50.o
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nvkm-y += nvkm/engine/fifo/dmag84.o
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nvkm-y += nvkm/engine/fifo/gpfifonv50.o
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nvkm-y += nvkm/engine/fifo/gpfifog84.o
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@ -48,8 +48,6 @@ void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int);
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int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
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const struct nvkm_oclass *, struct nv50_fifo_chan *);
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extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass;
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extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass;
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extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass;
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extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass;
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#endif
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@ -1,94 +0,0 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "channv50.h"
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#include <core/client.h>
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#include <core/ramht.h>
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#include <nvif/class.h>
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#include <nvif/cl826e.h>
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#include <nvif/unpack.h>
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static int
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g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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struct nvkm_object *parent = oclass->parent;
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union {
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struct g82_channel_dma_v0 v0;
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} *args = data;
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struct nv50_fifo *fifo = nv50_fifo(base);
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struct nv50_fifo_chan *chan;
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int ret = -ENOSYS;
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nvif_ioctl(parent, "create channel dma size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
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"pushbuf %llx offset %016llx\n",
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args->v0.version, args->v0.vmm, args->v0.pushbuf,
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args->v0.offset);
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if (!args->v0.pushbuf)
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return -EINVAL;
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} else
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return ret;
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &chan->base.object;
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ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
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oclass, chan);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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nvkm_kmap(chan->ramfc);
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nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
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nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
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nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
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nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
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nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
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nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
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nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
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nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
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(4 << 24) /* SEARCH_FULL */ |
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(chan->ramht->gpuobj->node->offset >> 4));
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nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10);
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nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12);
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nvkm_done(chan->ramfc);
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return 0;
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}
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const struct nvkm_fifo_chan_oclass
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g84_fifo_dma_oclass = {
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.base.oclass = G82_CHANNEL_DMA,
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.base.minver = 0,
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.base.maxver = 0,
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.ctor = g84_fifo_dma_new,
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};
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@ -1,92 +0,0 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "channv50.h"
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#include <core/client.h>
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#include <core/ramht.h>
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#include <nvif/class.h>
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#include <nvif/cl506e.h>
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#include <nvif/unpack.h>
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static int
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nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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struct nvkm_object *parent = oclass->parent;
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union {
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struct nv50_channel_dma_v0 v0;
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} *args = data;
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struct nv50_fifo *fifo = nv50_fifo(base);
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struct nv50_fifo_chan *chan;
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int ret = -ENOSYS;
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nvif_ioctl(parent, "create channel dma size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
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"pushbuf %llx offset %016llx\n",
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args->v0.version, args->v0.vmm, args->v0.pushbuf,
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args->v0.offset);
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if (!args->v0.pushbuf)
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return -EINVAL;
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} else
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return ret;
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &chan->base.object;
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ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
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oclass, chan);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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nvkm_kmap(chan->ramfc);
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nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
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nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
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nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
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nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
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nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
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nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
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nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
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nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
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nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
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(4 << 24) /* SEARCH_FULL */ |
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(chan->ramht->gpuobj->node->offset >> 4));
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nvkm_done(chan->ramfc);
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return 0;
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}
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const struct nvkm_fifo_chan_oclass
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nv50_fifo_dma_oclass = {
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.base.oclass = NV50_CHANNEL_DMA,
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.base.minver = 0,
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.base.maxver = 0,
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.ctor = nv50_fifo_dma_new,
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};
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@ -119,7 +119,6 @@ g84_fifo = {
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.uevent_init = g84_fifo_uevent_init,
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.uevent_fini = g84_fifo_uevent_fini,
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.chan = {
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&g84_fifo_dma_oclass,
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&g84_fifo_gpfifo_oclass,
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NULL
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},
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@ -136,7 +136,6 @@ nv50_fifo = {
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.pause = nv04_fifo_pause,
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.start = nv04_fifo_start,
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.chan = {
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&nv50_fifo_dma_oclass,
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&nv50_fifo_gpfifo_oclass,
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NULL
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},
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