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[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC

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Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8540 ADS, MPC8548 CDS, and MPC8560 ADS.

Also fixed up the size of the PCI node on MPC8560 ADS.

Signed-off-by: Dave Jiang <djiang@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dave Jiang 2007-05-10 10:03:05 -07:00 committed by Paul Mackerras
parent 1c2de47cd4
commit 50cf67075b
3 changed files with 49 additions and 1 deletions
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16
arch/powerpc/boot/dts/mpc8540ads.dts
View File

@ -48,6 +48,22 @@
reg = <e0000000 00100000>; // CCSRBAR 1M reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 { i2c@3000 {
device_type = "i2c"; device_type = "i2c";
compatible = "fsl-i2c"; compatible = "fsl-i2c";

16
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -48,6 +48,22 @@
reg = <e0000000 00100000>; // CCSRBAR 1M reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 { i2c@3000 {
device_type = "i2c"; device_type = "i2c";
compatible = "fsl-i2c"; compatible = "fsl-i2c";

18
arch/powerpc/boot/dts/mpc8560ads.dts
View File

@ -48,6 +48,22 @@
reg = <e0000000 00000200>; reg = <e0000000 00000200>;
bus-frequency = <13ab6680>; bus-frequency = <13ab6680>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
mdio@24520 { mdio@24520 {
device_type = "mdio"; device_type = "mdio";
compatible = "gianfar"; compatible = "gianfar";
@ -110,7 +126,7 @@
#address-cells = <3>; #address-cells = <3>;
compatible = "85xx"; compatible = "85xx";
device_type = "pci"; device_type = "pci";
reg = <8000 400>; reg = <8000 1000>;
clock-frequency = <3f940aa>; clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <f800 0 0 7>;
interrupt-map = < interrupt-map = <