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drm/xe: Fix indent in xe_hw_engine_print_state()

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Fix the indent to align with open parenthesis, following the coding
style.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20230508225322.2692066-5-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-05-08 15:53:22 -07:00 committed by Rodrigo Vivi
parent ee21379acc
commit 50f1f05916
1 changed files with 32 additions and 32 deletions
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64
drivers/gpu/drm/xe/xe_hw_engine.c
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@ -580,70 +580,70 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
return;
drm_printf(p, "%s (physical), logical instance=%d\n", hwe->name,
hwe->logical_instance);
hwe->logical_instance);
drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n",
hwe->domain,
xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
hwe->domain,
xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
drm_printf(p, "\tHWSTAM: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
hw_engine_mmio_read32(hwe,
hw_engine_mmio_read32(hwe,
RING_EXECLIST_SQ_CONTENTS_LO(0)));
drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
hw_engine_mmio_read32(hwe,
hw_engine_mmio_read32(hwe,
RING_EXECLIST_SQ_CONTENTS_HI(0)));
drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
drm_printf(p, "\tRING_START: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_START(0)));
hw_engine_mmio_read32(hwe, RING_START(0)));
drm_printf(p, "\tRING_HEAD: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
drm_printf(p, "\tRING_TAIL: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
drm_printf(p, "\tRING_CTL: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_CTL(0)));
hw_engine_mmio_read32(hwe, RING_CTL(0)));
drm_printf(p, "\tRING_MODE: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_MODE(0)));
hw_engine_mmio_read32(hwe, RING_MODE(0)));
drm_printf(p, "\tRING_IMR: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_IMR(0)));
hw_engine_mmio_read32(hwe, RING_IMR(0)));
drm_printf(p, "\tRING_ESR: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_ESR(0)));
hw_engine_mmio_read32(hwe, RING_ESR(0)));
drm_printf(p, "\tRING_EMR: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_EMR(0)));
hw_engine_mmio_read32(hwe, RING_EMR(0)));
drm_printf(p, "\tRING_EIR: 0x%08x\n",
hw_engine_mmio_read32(hwe, RING_EIR(0)));
hw_engine_mmio_read32(hwe, RING_EIR(0)));
drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
drm_printf(p, "\tACTHD: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
drm_printf(p, "\tIPEIR: 0x%08x\n",
hw_engine_mmio_read32(hwe, IPEIR(0)));
hw_engine_mmio_read32(hwe, IPEIR(0)));
drm_printf(p, "\tIPEHR: 0x%08x\n\n",
hw_engine_mmio_read32(hwe, IPEHR(0)));
hw_engine_mmio_read32(hwe, IPEHR(0)));
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
drm_printf(p, "\tRCU_MODE: 0x%08x\n",
xe_mmio_read32(hwe->gt, RCU_MODE));
xe_mmio_read32(hwe->gt, RCU_MODE));
}