arm64: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board
Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Francesco Dolcini <francesco.dolcini@toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Marek Vasut
Shawn Guo
parent
7899eb6cb1
commit
510c527b4f
@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
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321
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
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321
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
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@ -0,0 +1,321 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright 2021-2022 Marek Vasut <marex@denx.de>
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*/
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/dts-v1/;
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#include "imx8mm-verdin.dtsi"
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/ {
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model = "MENLO MX8MM EMBEDDED DEVICE";
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compatible = "menlo,mx8menlo",
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"toradex,verdin-imx8mm",
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"fsl,imx8mm";
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/delete-node/ gpio-keys;
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led>;
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user1 {
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label = "TestLed601";
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gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc0";
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};
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user2 {
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label = "TestLed602";
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gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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beeper {
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compatible = "gpio-beeper";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_beeper>;
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gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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};
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/* Fixed clock dedicated to SPI CAN on carrier board */
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clk_xtal20: clk-xtal20 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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};
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};
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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/* CAN controller on the baseboard */
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canfd: can@0 {
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compatible = "microchip,mcp2518fd";
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clocks = <&clk_xtal20>;
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interrupt-parent = <&gpio1>;
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interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
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reg = <0>;
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spi-max-frequency = <2000000>;
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};
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};
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&ecspi2 {
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pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
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status = "disabled";
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};
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ðphy0 {
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max-speed = <100>;
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};
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&fec1 {
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status = "okay";
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};
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&flexspi {
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status = "okay";
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flash@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <66000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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&gpio1 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio2 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio3 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "DISP_reset", "KBD_intI",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio4 {
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/*
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* CPLD_D[n] is ARM_CPLD[n] in schematic
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* CPLD_int is SA_INTERRUPT in schematic
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* CPLD_reset is RESET_SOFT in schematic
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*/
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gpio-line-names =
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"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
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"", "CPLD_D[0]", "", "",
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"", "", "", "CPLD_D[2]",
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"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
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"CPLD_D[7]", "", "", "",
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"", "", "", "",
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"", "", "", "KBD_intK",
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"", "", "", "";
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};
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&gpio5 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpio_expander_21 {
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status = "okay";
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};
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&hwmon {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&i2c4 {
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/* None of this is present on the SoM. */
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/delete-node/ bridge@2c;
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/delete-node/ hdmi@48;
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/delete-node/ touch@4a;
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/delete-node/ sensor@4f;
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/delete-node/ eeprom@50;
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/delete-node/ eeprom@57;
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};
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&iomuxc {
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pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
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<&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
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pinctrl_beeper: beepergrp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
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MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
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MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
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MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
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>;
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};
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pinctrl_led: ledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
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MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
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>;
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};
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pinctrl_uart4_rts: uart4rtsgrp {
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fsl,pins = <
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/* SODIMM 222 */
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
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>;
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};
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};
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&pinctrl_gpio1 {
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fsl,pins = <
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/* SODIMM 206 */
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MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
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>;
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};
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&pinctrl_gpio_hog1 {
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fsl,pins = <
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/* SODIMM 88 */
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MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
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/* CPLD_int */
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MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
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/* CPLD_reset */
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MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
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/* SODIMM 94 */
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MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
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/* SODIMM 96 */
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MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
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/* CPLD_D[7] */
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MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
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/* CPLD_D[6] */
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MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
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/* CPLD_D[5] */
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MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
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/* CPLD_D[4] */
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MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
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/* CPLD_D[3] */
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MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
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/* CPLD_D[2] */
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MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
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/* CPLD_D[1] */
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MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
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/* CPLD_D[0] */
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MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
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/* KBD_intK */
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MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
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/* DISP_reset */
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MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
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/* KBD_intI */
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MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
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/* SODIMM 46 */
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MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
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>;
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};
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&pinctrl_uart1 {
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fsl,pins = <
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/* SODIMM 149 */
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MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
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/* SODIMM 147 */
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MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
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/* SODIMM 210 */
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MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
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/* SODIMM 212 */
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MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
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>;
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};
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®_usb_otg1_vbus {
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/delete-property/ enable-active-high;
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gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
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};
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®_usb_otg2_vbus {
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/delete-property/ enable-active-high;
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gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
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};
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&sai2 {
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status = "disabled";
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};
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&uart1 {
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&uart4 {
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pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
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linux,rs485-enabled-at-boot-time;
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rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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status = "okay";
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};
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