MIPS: Loongson64: Bump ISA level to MIPSR2
Despite early sample of Loongson-3A1000, the whole Loongson64 family have implemented all the features required by MIPS64 Release2. Thus we decide to bump the ISA option to R2. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com Cc: linux-kernel@vger.kernel.org
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@ -1436,10 +1436,14 @@ config CPU_LOONGSON64
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bool "Loongson 64-bit CPU"
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depends on SYS_HAS_CPU_LOONGSON64
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select ARCH_HAS_PHYS_TO_DMA
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select CPU_MIPSR2
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select CPU_HAS_PREFETCH
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_SUPPORTS_MSA
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select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
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select CPU_MIPSR2_IRQ_VI
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select WEAK_ORDERING
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select WEAK_REORDERING_BEYOND_LLSC
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select MIPS_ASID_BITS_VARIABLE
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@ -1457,8 +1461,6 @@ config CPU_LOONGSON64
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config LOONGSON3_ENHANCEMENT
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bool "New Loongson-3 CPU Enhancements"
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default n
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select CPU_MIPSR2
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select CPU_HAS_PREFETCH
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depends on CPU_LOONGSON64
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help
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New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
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@ -23,7 +23,7 @@
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* TLB hazards
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*/
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#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
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!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
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!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
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/*
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* MIPSR2 defines ehb for hazard avoidance
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@ -158,7 +158,7 @@ do { \
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} while (0)
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#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
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defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
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defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
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defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
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/*
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