crypto: cavium/nitrox - use pci_alloc_irq_vectors() while enabling MSI-X.
replace pci_enable_msix_exact() with pci_alloc_irq_vectors(). get the required vector count from pci_msix_vec_count(). use struct nitrox_q_vector as the argument to tasklets. Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com> Reviewed-by: Gadam Sreerama <sgadam@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Srikanth Jampala
Herbert Xu
parent
e7892dd6d8
commit
5155e118dd
@ -12,13 +12,10 @@ void crypto_free_context(void *ctx);
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struct nitrox_device *nitrox_get_first_device(void);
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void nitrox_put_device(struct nitrox_device *ndev);
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void nitrox_pf_cleanup_isr(struct nitrox_device *ndev);
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int nitrox_pf_init_isr(struct nitrox_device *ndev);
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int nitrox_common_sw_init(struct nitrox_device *ndev);
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void nitrox_common_sw_cleanup(struct nitrox_device *ndev);
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void pkt_slc_resp_handler(unsigned long data);
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void pkt_slc_resp_tasklet(unsigned long data);
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int nitrox_process_se_request(struct nitrox_device *ndev,
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struct se_crypto_request *req,
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completion_t cb,
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@ -18,6 +18,7 @@
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* @response_head: submitted request list
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* @backlog_head: backlog queue
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* @dbell_csr_addr: doorbell register address for this queue
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* @compl_cnt_csr_addr: completion count register address of the slc port
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* @base: command queue base address
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* @dma: dma address of the base
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* @pending_count: request pending at device
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@ -39,6 +40,7 @@ struct nitrox_cmdq {
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struct list_head backlog_head;
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u8 __iomem *dbell_csr_addr;
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u8 __iomem *compl_cnt_csr_addr;
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u8 *base;
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dma_addr_t dma;
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@ -88,30 +90,17 @@ struct nitrox_stats {
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atomic64_t dropped;
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};
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#define MAX_MSIX_VECTOR_NAME 20
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/**
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* vectors for queues (64 AE, 64 SE and 64 ZIP) and
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* error condition/mailbox.
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*/
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#define MAX_MSIX_VECTORS 192
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struct nitrox_msix {
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struct msix_entry *entries;
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char **names;
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DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS);
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u32 nr_entries;
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};
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struct bh_data {
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/* slc port completion count address */
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u8 __iomem *completion_cnt_csr_addr;
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#define IRQ_NAMESZ 32
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struct nitrox_q_vector {
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char name[IRQ_NAMESZ];
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bool valid;
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int ring;
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struct tasklet_struct resp_tasklet;
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union {
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struct nitrox_cmdq *cmdq;
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struct tasklet_struct resp_handler;
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struct nitrox_device *ndev;
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};
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struct nitrox_bh {
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struct bh_data *slc;
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};
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/*
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@ -160,8 +149,7 @@ enum vf_mode {
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* @mode: Device mode PF/VF
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* @ctx_pool: DMA pool for crypto context
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* @pkt_inq: Packet input rings
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* @msix: MSI-X information
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* @bh: post processing work
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* @qvec: MSI-X queue vectors information
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* @hw: hardware information
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* @debugfs_dir: debugfs directory
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*/
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@ -186,8 +174,8 @@ struct nitrox_device {
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struct dma_pool *ctx_pool;
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struct nitrox_cmdq *pkt_inq;
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struct nitrox_msix msix;
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struct nitrox_bh bh;
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struct nitrox_q_vector *qvec;
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int num_vecs;
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struct nitrox_stats stats;
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struct nitrox_hw hw;
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@ -8,8 +8,14 @@
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#include "nitrox_common.h"
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#include "nitrox_hal.h"
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/**
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* One vector for each type of ring
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* - NPS packet ring, AQMQ ring and ZQMQ ring
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*/
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#define NR_RING_VECTORS 3
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#define NPS_CORE_INT_ACTIVE_ENTRY 192
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/* base entry for packet ring/port */
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#define PKT_RING_MSIX_BASE 0
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#define NON_RING_MSIX_BASE 192
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/**
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* nps_pkt_slc_isr - IRQ handler for NPS solicit port
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@ -18,13 +24,14 @@
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*/
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static irqreturn_t nps_pkt_slc_isr(int irq, void *data)
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{
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struct bh_data *slc = data;
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union nps_pkt_slc_cnts pkt_slc_cnts;
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struct nitrox_q_vector *qvec = data;
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union nps_pkt_slc_cnts slc_cnts;
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struct nitrox_cmdq *cmdq = qvec->cmdq;
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pkt_slc_cnts.value = readq(slc->completion_cnt_csr_addr);
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slc_cnts.value = readq(cmdq->compl_cnt_csr_addr);
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/* New packet on SLC output port */
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if (pkt_slc_cnts.s.slc_int)
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tasklet_hi_schedule(&slc->resp_handler);
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if (slc_cnts.s.slc_int)
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tasklet_hi_schedule(&qvec->resp_tasklet);
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return IRQ_HANDLED;
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}
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@ -191,56 +198,92 @@ static void clear_bmi_err_intr(struct nitrox_device *ndev)
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dev_err_ratelimited(DEV(ndev), "BMI_INT 0x%016llx\n", value);
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}
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/**
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* clear_nps_core_int_active - clear NPS_CORE_INT_ACTIVE interrupts
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* @ndev: NITROX device
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*/
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static void clear_nps_core_int_active(struct nitrox_device *ndev)
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static void nps_core_int_tasklet(unsigned long data)
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{
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union nps_core_int_active core_int_active;
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struct nitrox_q_vector *qvec = (void *)(uintptr_t)(data);
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struct nitrox_device *ndev = qvec->ndev;
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core_int_active.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
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if (core_int_active.s.nps_core)
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clear_nps_core_err_intr(ndev);
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if (core_int_active.s.nps_pkt)
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clear_nps_pkt_err_intr(ndev);
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if (core_int_active.s.pom)
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clear_pom_err_intr(ndev);
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if (core_int_active.s.pem)
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clear_pem_err_intr(ndev);
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if (core_int_active.s.lbc)
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clear_lbc_err_intr(ndev);
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if (core_int_active.s.efl)
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clear_efl_err_intr(ndev);
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if (core_int_active.s.bmi)
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clear_bmi_err_intr(ndev);
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/* If more work callback the ISR, set resend */
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core_int_active.s.resend = 1;
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nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int_active.value);
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/* if pf mode do queue recovery */
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if (ndev->mode == __NDEV_MODE_PF) {
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} else {
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/**
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* if VF(s) enabled communicate the error information
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* to VF(s)
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*/
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}
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}
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/**
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* nps_core_int_isr - interrupt handler for NITROX errors and
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* mailbox communication
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*/
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static irqreturn_t nps_core_int_isr(int irq, void *data)
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{
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struct nitrox_device *ndev = data;
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union nps_core_int_active core_int;
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clear_nps_core_int_active(ndev);
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core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
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if (core_int.s.nps_core)
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clear_nps_core_err_intr(ndev);
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if (core_int.s.nps_pkt)
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clear_nps_pkt_err_intr(ndev);
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if (core_int.s.pom)
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clear_pom_err_intr(ndev);
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if (core_int.s.pem)
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clear_pem_err_intr(ndev);
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if (core_int.s.lbc)
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clear_lbc_err_intr(ndev);
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if (core_int.s.efl)
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clear_efl_err_intr(ndev);
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if (core_int.s.bmi)
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clear_bmi_err_intr(ndev);
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/* If more work callback the ISR, set resend */
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core_int.s.resend = 1;
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nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value);
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return IRQ_HANDLED;
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}
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static int nitrox_enable_msix(struct nitrox_device *ndev)
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void nitrox_unregister_interrupts(struct nitrox_device *ndev)
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{
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struct msix_entry *entries;
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char **names;
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int i, nr_entries, ret;
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struct pci_dev *pdev = ndev->pdev;
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int i;
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for (i = 0; i < ndev->num_vecs; i++) {
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struct nitrox_q_vector *qvec;
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int vec;
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qvec = ndev->qvec + i;
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if (!qvec->valid)
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continue;
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/* get the vector number */
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vec = pci_irq_vector(pdev, i);
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irq_set_affinity_hint(vec, NULL);
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free_irq(vec, qvec);
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tasklet_disable(&qvec->resp_tasklet);
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tasklet_kill(&qvec->resp_tasklet);
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qvec->valid = false;
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}
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kfree(ndev->qvec);
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pci_free_irq_vectors(pdev);
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}
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int nitrox_register_interrupts(struct nitrox_device *ndev)
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{
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struct pci_dev *pdev = ndev->pdev;
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struct nitrox_q_vector *qvec;
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int nr_vecs, vec, cpu;
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int ret, i;
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/*
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* PF MSI-X vectors
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@ -254,216 +297,71 @@ static int nitrox_enable_msix(struct nitrox_device *ndev)
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* ....
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* Entry 192: NPS_CORE_INT_ACTIVE
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*/
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nr_entries = (ndev->nr_queues * NR_RING_VECTORS) + 1;
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entries = kcalloc_node(nr_entries, sizeof(struct msix_entry),
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GFP_KERNEL, ndev->node);
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if (!entries)
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return -ENOMEM;
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nr_vecs = pci_msix_vec_count(pdev);
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names = kcalloc(nr_entries, sizeof(char *), GFP_KERNEL);
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if (!names) {
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kfree(entries);
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/* Enable MSI-X */
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ret = pci_alloc_irq_vectors(pdev, nr_vecs, nr_vecs, PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_err(DEV(ndev), "msix vectors %d alloc failed\n", nr_vecs);
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return ret;
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}
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ndev->num_vecs = nr_vecs;
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ndev->qvec = kcalloc(nr_vecs, sizeof(*qvec), GFP_KERNEL);
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if (!ndev->qvec) {
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pci_free_irq_vectors(pdev);
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return -ENOMEM;
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}
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/* fill entires */
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for (i = 0; i < (nr_entries - 1); i++)
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entries[i].entry = i;
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/* request irqs for packet rings/ports */
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for (i = PKT_RING_MSIX_BASE; i < (nr_vecs - 1); i += NR_RING_VECTORS) {
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qvec = &ndev->qvec[i];
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entries[i].entry = NPS_CORE_INT_ACTIVE_ENTRY;
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qvec->ring = i / NR_RING_VECTORS;
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if (qvec->ring >= ndev->nr_queues)
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break;
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for (i = 0; i < nr_entries; i++) {
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*(names + i) = kzalloc(MAX_MSIX_VECTOR_NAME, GFP_KERNEL);
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if (!(*(names + i))) {
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ret = -ENOMEM;
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goto msix_fail;
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}
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}
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ndev->msix.entries = entries;
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ndev->msix.names = names;
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ndev->msix.nr_entries = nr_entries;
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ret = pci_enable_msix_exact(ndev->pdev, ndev->msix.entries,
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ndev->msix.nr_entries);
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snprintf(qvec->name, IRQ_NAMESZ, "nitrox-pkt%d", qvec->ring);
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/* get the vector number */
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vec = pci_irq_vector(pdev, i);
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ret = request_irq(vec, nps_pkt_slc_isr, 0, qvec->name, qvec);
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if (ret) {
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dev_err(&ndev->pdev->dev, "Failed to enable MSI-X IRQ(s) %d\n",
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ret);
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goto msix_fail;
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}
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return 0;
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msix_fail:
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for (i = 0; i < nr_entries; i++)
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kfree(*(names + i));
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kfree(entries);
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kfree(names);
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return ret;
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}
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static void nitrox_cleanup_pkt_slc_bh(struct nitrox_device *ndev)
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{
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int i;
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if (!ndev->bh.slc)
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return;
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for (i = 0; i < ndev->nr_queues; i++) {
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struct bh_data *bh = &ndev->bh.slc[i];
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tasklet_disable(&bh->resp_handler);
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tasklet_kill(&bh->resp_handler);
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}
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kfree(ndev->bh.slc);
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ndev->bh.slc = NULL;
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}
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static int nitrox_setup_pkt_slc_bh(struct nitrox_device *ndev)
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{
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u32 size;
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int i;
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size = ndev->nr_queues * sizeof(struct bh_data);
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ndev->bh.slc = kzalloc(size, GFP_KERNEL);
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if (!ndev->bh.slc)
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return -ENOMEM;
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for (i = 0; i < ndev->nr_queues; i++) {
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struct bh_data *bh = &ndev->bh.slc[i];
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u64 offset;
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offset = NPS_PKT_SLC_CNTSX(i);
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/* pre calculate completion count address */
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bh->completion_cnt_csr_addr = NITROX_CSR_ADDR(ndev, offset);
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bh->cmdq = &ndev->pkt_inq[i];
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tasklet_init(&bh->resp_handler, pkt_slc_resp_handler,
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(unsigned long)bh);
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}
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return 0;
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}
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static int nitrox_request_irqs(struct nitrox_device *ndev)
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{
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struct pci_dev *pdev = ndev->pdev;
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struct msix_entry *msix_ent = ndev->msix.entries;
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int nr_ring_vectors, i = 0, ring, cpu, ret;
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char *name;
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/*
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* PF MSI-X vectors
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*
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* Entry 0: NPS PKT ring 0
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* Entry 1: AQMQ ring 0
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* Entry 2: ZQM ring 0
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* Entry 3: NPS PKT ring 1
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* ....
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* Entry 192: NPS_CORE_INT_ACTIVE
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*/
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nr_ring_vectors = ndev->nr_queues * NR_RING_VECTORS;
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/* request irq for pkt ring/ports only */
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while (i < nr_ring_vectors) {
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name = *(ndev->msix.names + i);
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ring = (i / NR_RING_VECTORS);
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snprintf(name, MAX_MSIX_VECTOR_NAME, "n5(%d)-slc-ring%d",
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ndev->idx, ring);
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ret = request_irq(msix_ent[i].vector, nps_pkt_slc_isr, 0,
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name, &ndev->bh.slc[ring]);
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if (ret) {
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dev_err(&pdev->dev, "failed to get irq %d for %s\n",
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msix_ent[i].vector, name);
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return ret;
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}
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cpu = ring % num_online_cpus();
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irq_set_affinity_hint(msix_ent[i].vector, get_cpu_mask(cpu));
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set_bit(i, ndev->msix.irqs);
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i += NR_RING_VECTORS;
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}
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/* Request IRQ for NPS_CORE_INT_ACTIVE */
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name = *(ndev->msix.names + i);
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snprintf(name, MAX_MSIX_VECTOR_NAME, "n5(%d)-nps-core-int", ndev->idx);
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ret = request_irq(msix_ent[i].vector, nps_core_int_isr, 0, name, ndev);
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if (ret) {
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dev_err(&pdev->dev, "failed to get irq %d for %s\n",
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msix_ent[i].vector, name);
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return ret;
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}
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set_bit(i, ndev->msix.irqs);
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return 0;
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}
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static void nitrox_disable_msix(struct nitrox_device *ndev)
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{
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struct msix_entry *msix_ent = ndev->msix.entries;
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char **names = ndev->msix.names;
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int i = 0, ring, nr_ring_vectors;
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nr_ring_vectors = ndev->msix.nr_entries - 1;
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/* clear pkt ring irqs */
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while (i < nr_ring_vectors) {
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if (test_and_clear_bit(i, ndev->msix.irqs)) {
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ring = (i / NR_RING_VECTORS);
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irq_set_affinity_hint(msix_ent[i].vector, NULL);
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free_irq(msix_ent[i].vector, &ndev->bh.slc[ring]);
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}
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i += NR_RING_VECTORS;
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}
|
||||
irq_set_affinity_hint(msix_ent[i].vector, NULL);
|
||||
free_irq(msix_ent[i].vector, ndev);
|
||||
clear_bit(i, ndev->msix.irqs);
|
||||
|
||||
kfree(ndev->msix.entries);
|
||||
for (i = 0; i < ndev->msix.nr_entries; i++)
|
||||
kfree(*(names + i));
|
||||
|
||||
kfree(names);
|
||||
pci_disable_msix(ndev->pdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* nitrox_pf_cleanup_isr: Cleanup PF MSI-X and IRQ
|
||||
* @ndev: NITROX device
|
||||
*/
|
||||
void nitrox_pf_cleanup_isr(struct nitrox_device *ndev)
|
||||
{
|
||||
nitrox_disable_msix(ndev);
|
||||
nitrox_cleanup_pkt_slc_bh(ndev);
|
||||
}
|
||||
|
||||
/**
|
||||
* nitrox_init_isr - Initialize PF MSI-X vectors and IRQ
|
||||
* @ndev: NITROX device
|
||||
*
|
||||
* Return: 0 on success, a negative value on failure.
|
||||
*/
|
||||
int nitrox_pf_init_isr(struct nitrox_device *ndev)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = nitrox_setup_pkt_slc_bh(ndev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = nitrox_enable_msix(ndev);
|
||||
if (err)
|
||||
goto msix_fail;
|
||||
|
||||
err = nitrox_request_irqs(ndev);
|
||||
if (err)
|
||||
dev_err(DEV(ndev), "irq failed for pkt ring/port%d\n",
|
||||
qvec->ring);
|
||||
goto irq_fail;
|
||||
}
|
||||
cpu = qvec->ring % num_online_cpus();
|
||||
irq_set_affinity_hint(vec, get_cpu_mask(cpu));
|
||||
|
||||
tasklet_init(&qvec->resp_tasklet, pkt_slc_resp_tasklet,
|
||||
(unsigned long)qvec);
|
||||
qvec->cmdq = &ndev->pkt_inq[qvec->ring];
|
||||
qvec->valid = true;
|
||||
}
|
||||
|
||||
/* request irqs for non ring vectors */
|
||||
i = NON_RING_MSIX_BASE;
|
||||
qvec = &ndev->qvec[i];
|
||||
|
||||
snprintf(qvec->name, IRQ_NAMESZ, "nitrox-core-int%d", i);
|
||||
/* get the vector number */
|
||||
vec = pci_irq_vector(pdev, i);
|
||||
ret = request_irq(vec, nps_core_int_isr, 0, qvec->name, qvec);
|
||||
if (ret) {
|
||||
dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", i);
|
||||
goto irq_fail;
|
||||
}
|
||||
cpu = num_online_cpus();
|
||||
irq_set_affinity_hint(vec, get_cpu_mask(cpu));
|
||||
|
||||
tasklet_init(&qvec->resp_tasklet, nps_core_int_tasklet,
|
||||
(unsigned long)qvec);
|
||||
qvec->ndev = ndev;
|
||||
qvec->valid = true;
|
||||
|
||||
return 0;
|
||||
|
||||
irq_fail:
|
||||
nitrox_disable_msix(ndev);
|
||||
msix_fail:
|
||||
nitrox_cleanup_pkt_slc_bh(ndev);
|
||||
return err;
|
||||
nitrox_unregister_interrupts(ndev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
10
drivers/crypto/cavium/nitrox/nitrox_isr.h
Normal file
10
drivers/crypto/cavium/nitrox/nitrox_isr.h
Normal file
@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __NITROX_ISR_H
|
||||
#define __NITROX_ISR_H
|
||||
|
||||
#include "nitrox_dev.h"
|
||||
|
||||
int nitrox_register_interrupts(struct nitrox_device *ndev);
|
||||
void nitrox_unregister_interrupts(struct nitrox_device *ndev);
|
||||
|
||||
#endif /* __NITROX_ISR_H */
|
||||
@ -69,6 +69,7 @@ static void nitrox_cmdq_cleanup(struct nitrox_cmdq *cmdq)
|
||||
nitrox_cmdq_reset(cmdq);
|
||||
|
||||
cmdq->dbell_csr_addr = NULL;
|
||||
cmdq->compl_cnt_csr_addr = NULL;
|
||||
cmdq->unalign_base = NULL;
|
||||
cmdq->base = NULL;
|
||||
cmdq->unalign_dma = 0;
|
||||
@ -112,6 +113,9 @@ static int nitrox_alloc_pktin_queues(struct nitrox_device *ndev)
|
||||
/* packet input ring doorbell address */
|
||||
offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
|
||||
cmdq->dbell_csr_addr = NITROX_CSR_ADDR(ndev, offset);
|
||||
/* packet solicit port completion count address */
|
||||
offset = NPS_PKT_SLC_CNTSX(i);
|
||||
cmdq->compl_cnt_csr_addr = NITROX_CSR_ADDR(ndev, offset);
|
||||
|
||||
err = nitrox_cmdq_init(cmdq, PKTIN_Q_ALIGN_BYTES);
|
||||
if (err)
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include "nitrox_common.h"
|
||||
#include "nitrox_csr.h"
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_isr.h"
|
||||
|
||||
#define CNN55XX_DEV_ID 0x12
|
||||
#define MAX_PF_QUEUES 64
|
||||
@ -244,7 +245,7 @@ static int nitrox_pf_sw_init(struct nitrox_device *ndev)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = nitrox_pf_init_isr(ndev);
|
||||
err = nitrox_register_interrupts(ndev);
|
||||
if (err)
|
||||
nitrox_common_sw_cleanup(ndev);
|
||||
|
||||
@ -253,7 +254,7 @@ static int nitrox_pf_sw_init(struct nitrox_device *ndev)
|
||||
|
||||
static void nitrox_pf_sw_cleanup(struct nitrox_device *ndev)
|
||||
{
|
||||
nitrox_pf_cleanup_isr(ndev);
|
||||
nitrox_unregister_interrupts(ndev);
|
||||
nitrox_common_sw_cleanup(ndev);
|
||||
}
|
||||
|
||||
|
||||
@ -721,18 +721,18 @@ static void process_response_list(struct nitrox_cmdq *cmdq)
|
||||
}
|
||||
|
||||
/**
|
||||
* pkt_slc_resp_handler - post processing of SE responses
|
||||
* pkt_slc_resp_tasklet - post processing of SE responses
|
||||
*/
|
||||
void pkt_slc_resp_handler(unsigned long data)
|
||||
void pkt_slc_resp_tasklet(unsigned long data)
|
||||
{
|
||||
struct bh_data *bh = (void *)(uintptr_t)(data);
|
||||
struct nitrox_cmdq *cmdq = bh->cmdq;
|
||||
union nps_pkt_slc_cnts pkt_slc_cnts;
|
||||
struct nitrox_q_vector *qvec = (void *)(uintptr_t)(data);
|
||||
struct nitrox_cmdq *cmdq = qvec->cmdq;
|
||||
union nps_pkt_slc_cnts slc_cnts;
|
||||
|
||||
/* read completion count */
|
||||
pkt_slc_cnts.value = readq(bh->completion_cnt_csr_addr);
|
||||
slc_cnts.value = readq(cmdq->compl_cnt_csr_addr);
|
||||
/* resend the interrupt if more work to do */
|
||||
pkt_slc_cnts.s.resend = 1;
|
||||
slc_cnts.s.resend = 1;
|
||||
|
||||
process_response_list(cmdq);
|
||||
|
||||
@ -740,7 +740,7 @@ void pkt_slc_resp_handler(unsigned long data)
|
||||
* clear the interrupt with resend bit enabled,
|
||||
* MSI-X interrupt generates if Completion count > Threshold
|
||||
*/
|
||||
writeq(pkt_slc_cnts.value, bh->completion_cnt_csr_addr);
|
||||
writeq(slc_cnts.value, cmdq->compl_cnt_csr_addr);
|
||||
/* order the writes */
|
||||
mmiowb();
|
||||
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
#include "nitrox_dev.h"
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_common.h"
|
||||
#include "nitrox_isr.h"
|
||||
|
||||
static inline bool num_vfs_valid(int num_vfs)
|
||||
{
|
||||
@ -55,7 +56,7 @@ static void pf_sriov_cleanup(struct nitrox_device *ndev)
|
||||
nitrox_crypto_unregister();
|
||||
|
||||
/* cleanup PF resources */
|
||||
nitrox_pf_cleanup_isr(ndev);
|
||||
nitrox_unregister_interrupts(ndev);
|
||||
nitrox_common_sw_cleanup(ndev);
|
||||
}
|
||||
|
||||
@ -68,7 +69,7 @@ static int pf_sriov_init(struct nitrox_device *ndev)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = nitrox_pf_init_isr(ndev);
|
||||
err = nitrox_register_interrupts(ndev);
|
||||
if (err) {
|
||||
nitrox_common_sw_cleanup(ndev);
|
||||
return err;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user