PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip designware PCIe controller. To make that usable, this patch adds a wrapper driver based on existing designware driver. Adds bindings for this new driver and update MAINTAINERS as well. Cc: linux-pci@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Pratyush Anand
Viresh Kumar
parent
4c834452aa
commit
51b66a6ce1
14
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
Normal file
14
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
Normal file
@ -0,0 +1,14 @@
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SPEAr13XX PCIe DT detail:
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================================
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SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
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controller.
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Required properties:
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- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
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- phys : phandle to phy node associated with pcie controller
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- phy-names : must be "pcie-phy"
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- All other definitions as per generic PCI bindings
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Optional properties:
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- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
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@ -6820,6 +6820,12 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
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F: drivers/pci/host/pci-host-generic.c
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PCIE DRIVER FOR ST SPEAR13XX
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M: Mohit Kumar <mohit.kumar@st.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: drivers/pci/host/*spear*
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PCMCIA SUBSYSTEM
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P: Linux PCMCIA Team
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L: linux-pcmcia@lists.infradead.org
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@ -46,4 +46,12 @@ config PCI_HOST_GENERIC
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Say Y here if you want to support a simple generic PCI host
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controller, such as the one emulated by kvmtool.
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config PCIE_SPEAR13XX
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tristate "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX
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select PCIEPORTBUS
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select PCIE_DW
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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endmenu
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@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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405
drivers/pci/host/pcie-spear13xx.c
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405
drivers/pci/host/pcie-spear13xx.c
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@ -0,0 +1,405 @@
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/*
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* PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
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*
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* SPEAr13xx PCIe Glue Layer Source Code
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*
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* Copyright (C) 2010-2014 ST Microelectronics
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* Pratyush Anand <pratyush.anand@st.com>
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* Mohit Kumar <mohit.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-designware.h"
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struct spear13xx_pcie {
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void __iomem *app_base;
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struct phy *phy;
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struct clk *clk;
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struct pcie_port pp;
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bool is_gen1;
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};
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struct pcie_app_reg {
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u32 app_ctrl_0; /* cr0 */
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u32 app_ctrl_1; /* cr1 */
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u32 app_status_0; /* cr2 */
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u32 app_status_1; /* cr3 */
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u32 msg_status; /* cr4 */
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u32 msg_payload; /* cr5 */
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u32 int_sts; /* cr6 */
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u32 int_clr; /* cr7 */
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u32 int_mask; /* cr8 */
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u32 mst_bmisc; /* cr9 */
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u32 phy_ctrl; /* cr10 */
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u32 phy_status; /* cr11 */
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u32 cxpl_debug_info_0; /* cr12 */
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u32 cxpl_debug_info_1; /* cr13 */
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u32 ven_msg_ctrl_0; /* cr14 */
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u32 ven_msg_ctrl_1; /* cr15 */
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u32 ven_msg_data_0; /* cr16 */
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u32 ven_msg_data_1; /* cr17 */
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u32 ven_msi_0; /* cr18 */
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u32 ven_msi_1; /* cr19 */
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u32 mst_rmisc; /* cr20 */
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};
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/* CR0 ID */
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#define RX_LANE_FLIP_EN_ID 0
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#define TX_LANE_FLIP_EN_ID 1
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#define SYS_AUX_PWR_DET_ID 2
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#define APP_LTSSM_ENABLE_ID 3
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#define SYS_ATTEN_BUTTON_PRESSED_ID 4
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#define SYS_MRL_SENSOR_STATE_ID 5
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#define SYS_PWR_FAULT_DET_ID 6
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#define SYS_MRL_SENSOR_CHGED_ID 7
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#define SYS_PRE_DET_CHGED_ID 8
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#define SYS_CMD_CPLED_INT_ID 9
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#define APP_INIT_RST_0_ID 11
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#define APP_REQ_ENTR_L1_ID 12
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#define APP_READY_ENTR_L23_ID 13
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#define APP_REQ_EXIT_L1_ID 14
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#define DEVICE_TYPE_EP (0 << 25)
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#define DEVICE_TYPE_LEP (1 << 25)
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#define DEVICE_TYPE_RC (4 << 25)
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#define SYS_INT_ID 29
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#define MISCTRL_EN_ID 30
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#define REG_TRANSLATION_ENABLE 31
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/* CR1 ID */
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#define APPS_PM_XMT_TURNOFF_ID 2
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#define APPS_PM_XMT_PME_ID 5
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/* CR3 ID */
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#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
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#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
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#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
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#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
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#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
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#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
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#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
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#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
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#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
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#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
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#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
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#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
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#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
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#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
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#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
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#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
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#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
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#define XMLH_LTSSM_STATE_L0 0x11
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#define XMLH_LTSSM_STATE_L0S 0x12
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#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
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#define XMLH_LTSSM_STATE_L1_IDLE 0x14
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#define XMLH_LTSSM_STATE_L2_IDLE 0x15
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#define XMLH_LTSSM_STATE_L2_WAKE 0x16
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#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
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#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
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#define XMLH_LTSSM_STATE_DISABLED 0x19
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#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
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#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
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#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
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#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
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#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
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#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
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#define XMLH_LTSSM_STATE_MASK 0x3F
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#define XMLH_LINK_UP (1 << 6)
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/* CR4 ID */
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#define CFG_MSI_EN_ID 18
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/* CR6 */
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#define INTA_CTRL_INT (1 << 7)
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#define INTB_CTRL_INT (1 << 8)
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#define INTC_CTRL_INT (1 << 9)
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#define INTD_CTRL_INT (1 << 10)
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#define MSI_CTRL_INT (1 << 26)
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/* CR19 ID */
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#define VEN_MSI_REQ_ID 11
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#define VEN_MSI_FUN_NUM_ID 8
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#define VEN_MSI_TC_ID 5
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#define VEN_MSI_VECTOR_ID 0
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#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
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#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
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#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
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#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
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#define EXP_CAP_ID_OFFSET 0x70
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#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
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static int spear13xx_pcie_establish_link(struct pcie_port *pp)
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{
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u32 val;
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int count = 0;
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link already up\n");
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return 0;
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}
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dw_pcie_setup_rc(pp);
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/*
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* this controller support only 128 bytes read size, however its
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* default value in capability register is 512 bytes. So force
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* it to 128 here.
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*/
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dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
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val &= ~PCI_EXP_DEVCTL_READRQ;
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dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
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dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
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dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
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/*
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* if is_gen1 is set then handle it, so that some buggy card
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* also works
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*/
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if (spear13xx_pcie->is_gen1) {
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dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
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&val);
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if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
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PCI_EXP_LNKCAP, 4, val);
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}
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dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
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&val);
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if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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val &= ~((u32)PCI_EXP_LNKCAP_SLS);
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val |= PCI_EXP_LNKCAP_SLS_2_5GB;
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dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
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PCI_EXP_LNKCTL2, 4, val);
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}
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}
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/* enable ltssm */
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writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
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| (1 << APP_LTSSM_ENABLE_ID)
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| ((u32)1 << REG_TRANSLATION_ENABLE),
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&app_reg->app_ctrl_0);
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/* check if the link is up or not */
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while (!dw_pcie_link_up(pp)) {
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mdelay(100);
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count++;
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if (count == 10) {
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dev_err(pp->dev, "link Fail\n");
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return -EINVAL;
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}
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}
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dev_info(pp->dev, "link up\n");
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return 0;
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}
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static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
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{
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struct pcie_port *pp = arg;
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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unsigned int status;
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status = readl(&app_reg->int_sts);
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if (status & MSI_CTRL_INT) {
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if (!IS_ENABLED(CONFIG_PCI_MSI))
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BUG();
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dw_handle_msi_irq(pp);
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}
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writel(status, &app_reg->int_clr);
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return IRQ_HANDLED;
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}
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static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
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{
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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/* Enable MSI interrupt */
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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dw_pcie_msi_init(pp);
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writel(readl(&app_reg->int_mask) |
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MSI_CTRL_INT, &app_reg->int_mask);
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}
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}
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static int spear13xx_pcie_link_up(struct pcie_port *pp)
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{
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
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return 1;
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return 0;
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}
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static void spear13xx_pcie_host_init(struct pcie_port *pp)
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{
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spear13xx_pcie_establish_link(pp);
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spear13xx_pcie_enable_interrupts(pp);
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}
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static struct pcie_host_ops spear13xx_pcie_host_ops = {
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.link_up = spear13xx_pcie_link_up,
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.host_init = spear13xx_pcie_host_init,
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};
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static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret;
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pp->irq = platform_get_irq(pdev, 0);
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if (!pp->irq) {
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dev_err(dev, "failed to get irq\n");
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return -ENODEV;
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}
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ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
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IRQF_SHARED, "spear1340-pcie", pp);
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if (ret) {
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dev_err(dev, "failed to request irq %d\n", pp->irq);
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return ret;
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}
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pp->root_bus_nr = -1;
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pp->ops = &spear13xx_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init spear13xx_pcie_probe(struct platform_device *pdev)
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{
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struct spear13xx_pcie *spear13xx_pcie;
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struct pcie_port *pp;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct resource *dbi_base;
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int ret;
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spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
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if (!spear13xx_pcie) {
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dev_err(dev, "no memory for SPEAr13xx pcie\n");
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return -ENOMEM;
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}
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spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(spear13xx_pcie->phy)) {
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ret = PTR_ERR(spear13xx_pcie->phy);
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if (ret == -EPROBE_DEFER)
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dev_info(dev, "probe deferred\n");
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else
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dev_err(dev, "couldn't get pcie-phy\n");
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return ret;
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}
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phy_init(spear13xx_pcie->phy);
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spear13xx_pcie->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(spear13xx_pcie->clk)) {
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dev_err(dev, "couldn't get clk for pcie\n");
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return PTR_ERR(spear13xx_pcie->clk);
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}
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ret = clk_prepare_enable(spear13xx_pcie->clk);
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if (ret) {
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dev_err(dev, "couldn't enable clk for pcie\n");
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return ret;
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}
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pp = &spear13xx_pcie->pp;
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pp->dev = dev;
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dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pp->dbi_base)) {
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dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
|
||||
ret = PTR_ERR(pp->dbi_base);
|
||||
goto fail_clk;
|
||||
}
|
||||
spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
|
||||
|
||||
if (of_property_read_bool(np, "st,pcie-is-gen1"))
|
||||
spear13xx_pcie->is_gen1 = true;
|
||||
|
||||
ret = add_pcie_port(pp, pdev);
|
||||
if (ret < 0)
|
||||
goto fail_clk;
|
||||
|
||||
platform_set_drvdata(pdev, spear13xx_pcie);
|
||||
return 0;
|
||||
|
||||
fail_clk:
|
||||
clk_disable_unprepare(spear13xx_pcie->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(spear13xx_pcie->clk);
|
||||
|
||||
phy_exit(spear13xx_pcie->phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id spear13xx_pcie_of_match[] = {
|
||||
{ .compatible = "st,spear1340-pcie", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
|
||||
|
||||
static struct platform_driver spear13xx_pcie_driver = {
|
||||
.probe = spear13xx_pcie_probe,
|
||||
.remove = spear13xx_pcie_remove,
|
||||
.driver = {
|
||||
.name = "spear-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
/* SPEAr13xx PCIe driver does not allow module unload */
|
||||
|
||||
static int __init pcie_init(void)
|
||||
{
|
||||
return platform_driver_register(&spear13xx_pcie_driver);
|
||||
}
|
||||
module_init(pcie_init);
|
||||
|
||||
MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
|
||||
MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user