drm/amdgpu: add module parameter for async_gfx_ring enablement
0 means disable async_gfx_ring and is the default setting 1 means enable async_gfx_ring Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -158,6 +158,7 @@ extern uint amdgpu_dm_abm_level;
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extern struct amdgpu_mgpu_info mgpu_info;
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extern int amdgpu_ras_enable;
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extern uint amdgpu_ras_mask;
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extern int amdgpu_async_gfx_ring;
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#ifdef CONFIG_DRM_AMDGPU_SI
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extern int amdgpu_si_support;
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@ -136,6 +136,7 @@ int amdgpu_emu_mode = 0;
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uint amdgpu_smu_memory_pool_size = 0;
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/* FBC (bit 0) disabled by default*/
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uint amdgpu_dc_feature_mask = 0;
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int amdgpu_async_gfx_ring = 0;
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struct amdgpu_mgpu_info mgpu_info = {
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.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
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@ -565,6 +566,14 @@ MODULE_PARM_DESC(smu_memory_pool_size,
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"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
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module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
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/**
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* DOC: async_gfx_ring (int)
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* It is used to enable gfx rings that could be configured with different prioritites or equal priorities
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*/
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MODULE_PARM_DESC(async_gfx_ring,
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"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled (default), 1 = enabled)");
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module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
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#ifdef CONFIG_HSA_AMD
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/**
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* DOC: sched_policy (int)
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