drm/i915/bdw: WaProgramL3SqcReg1Default
Program the default initial value of the L3SqcReg1 on BDW for performance v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out. v3: Spec shows now a different value. It tells us to set to 0x784000 instead the 0x610000 that is there already. Also rebased after a long time so using WA_WRITE now. Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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committed by
Daniel Vetter
parent
474d1ec4a3
commit
51ce4db174
@ -5336,6 +5336,9 @@ enum skl_disp_power_wells {
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#define GEN7_L3SQCREG1 0xB010
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#define GEN7_L3SQCREG1 0xB010
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#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
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#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
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#define GEN8_L3SQCREG1 0xB100
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#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
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#define GEN7_L3CNTLREG1 0xB01C
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#define GEN7_L3CNTLREG1 0xB01C
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#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
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#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
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#define GEN7_L3AGDIS (1<<19)
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#define GEN7_L3AGDIS (1<<19)
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@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4);
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GEN6_WIZ_HASHING_16x4);
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/* WaProgramL3SqcReg1Default:bdw */
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WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
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return 0;
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return 0;
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}
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}
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