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drm/i915/dp: Avoid left shift of DSC output bpp by 4

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To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-12-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2023-08-17 19:54:52 +05:30
parent 2f4761c665
commit 51dda14868
2 changed files with 4 additions and 8 deletions
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10
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -814,11 +814,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
/*
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
* fractional part is 0
*/
return bits_per_pixel << 4;
return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@ -1208,7 +1204,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
bigjoiner,
output_format,
pipe_bpp, 64) >> 4;
pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@ -1811,7 +1807,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_compressed_bpp >> 4,
dsc_max_compressed_bpp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;

2
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
mode->hdisplay,
bigjoiner,
INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64) >> 4;
pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,