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mmc: sdhci-pci-o2micro: Fix SDR50 mode timing issue

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Change SDR50 mode clock source from DLL output clock to PLL open clock
1.HS200 and SDR104 mode select DLL output clock
2.SDR50 mode select PLL open clock

Signed-off-by: Fred <fred.ai@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230223120450.16858-1-fredaibayhubtech@126.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Fred 2023-02-23 20:04:50 +08:00 committed by Ulf Hansson
parent ca6b5fe277
commit 51dfc6142a
1 changed files with 16 additions and 14 deletions
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4
drivers/mmc/host/sdhci-pci-o2micro.c
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@ -339,6 +339,8 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
reg_val &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
if ((host->timing == MMC_TIMING_MMC_HS200) ||
(host->timing == MMC_TIMING_UHS_SDR104)) {
/* UnLock WP */
pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
scratch_8 &= 0x7f;
@ -354,7 +356,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
scratch_8 |= 0x80;
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
}
/* Start clk */
reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
reg_val |= SDHCI_CLOCK_CARD_EN;