- Mark requests for GuC virtual engines to avoid use-after-free (Andrzej).
-----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmTxBb8ACgkQ+mJfZA7r E8oO+wf+MCMDTGW5eFRsr0JFgUo6mvcKqrNQjAKro+BaHK/Y/uvbOK1/IAMBjsC2 H48G5Pnli2GVpSbsmjKlZgZwIcuZQmeiGktgHULDMlEpcL6703GJEHsaktlgDlEw EGsr6eE5ElWkAcQq/w5Hs2O0CsNbpT1SUjJXKFBMhX5BvhBmaK+oU4beenqfzyC8 ngxn65z0btZ2AtmQ8I56cxCUrLPjPY2epu10XIvr5euXG+Qzj5qr6smSHSyFbA+8 C5YK/vGxWxtppF2kdQc8hjCW5VSWzLLGttsEN+rgYufaHHcpGhAgTLpVH/KSF+iJ NbbIckdkacZOILFsnEEm0hLtIZXuLA== =CO5h -----END PGP SIGNATURE----- Merge tag 'drm-intel-next-fixes-2023-08-31' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Mark requests for GuC virtual engines to avoid use-after-free (Andrzej). Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZPEGEeP2EwCtx9hM@intel.com
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commit
51eed9d4ce
@ -58,6 +58,7 @@ struct i915_perf_group;
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typedef u32 intel_engine_mask_t;
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#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
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#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
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struct intel_hw_status_page {
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struct list_head timelines;
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@ -5470,6 +5470,9 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
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ve->base.flags = I915_ENGINE_IS_VIRTUAL;
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BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES);
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ve->base.mask = VIRTUAL_ENGINES;
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intel_context_init(&ve->context, &ve->base);
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for (n = 0; n < count; n++) {
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@ -134,9 +134,7 @@ static void i915_fence_release(struct dma_fence *fence)
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i915_sw_fence_fini(&rq->semaphore);
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/*
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* Keep one request on each engine for reserved use under mempressure
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* do not use with virtual engines as this really is only needed for
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* kernel contexts.
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* Keep one request on each engine for reserved use under mempressure.
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*
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* We do not hold a reference to the engine here and so have to be
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* very careful in what rq->engine we poke. The virtual engine is
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@ -166,8 +164,7 @@ static void i915_fence_release(struct dma_fence *fence)
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* know that if the rq->execution_mask is a single bit, rq->engine
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* can be a physical engine with the exact corresponding mask.
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*/
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if (!intel_engine_is_virtual(rq->engine) &&
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is_power_of_2(rq->execution_mask) &&
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if (is_power_of_2(rq->execution_mask) &&
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!cmpxchg(&rq->engine->request_pool, NULL, rq))
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return;
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