phy: add driver for Microsemi Ocelot SerDes muxing
The Microsemi Ocelot can mux SerDes lanes (aka macros) to different switch ports or even make it act as a PCIe interface. This adds support for the muxing of the SerDes. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Quentin Schulz
David S. Miller
parent
b68fc09be4
commit
51f6b410fc
@ -48,6 +48,7 @@ source "drivers/phy/lantiq/Kconfig"
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source "drivers/phy/marvell/Kconfig"
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source "drivers/phy/mediatek/Kconfig"
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source "drivers/phy/motorola/Kconfig"
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source "drivers/phy/mscc/Kconfig"
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source "drivers/phy/qualcomm/Kconfig"
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source "drivers/phy/ralink/Kconfig"
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source "drivers/phy/renesas/Kconfig"
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@ -18,6 +18,7 @@ obj-y += broadcom/ \
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hisilicon/ \
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marvell/ \
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motorola/ \
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mscc/ \
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qualcomm/ \
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ralink/ \
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samsung/ \
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11
drivers/phy/mscc/Kconfig
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11
drivers/phy/mscc/Kconfig
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@ -0,0 +1,11 @@
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#
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# Phy drivers for Microsemi devices
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#
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config PHY_OCELOT_SERDES
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tristate "SerDes PHY driver for Microsemi Ocelot"
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select GENERIC_PHY
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depends on OF
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depends on MFD_SYSCON
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help
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Enable this for supporting SerDes muxing with Microsemi Ocelot.
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5
drivers/phy/mscc/Makefile
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5
drivers/phy/mscc/Makefile
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@ -0,0 +1,5 @@
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#
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# Makefile for the Microsemi phy drivers.
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#
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obj-$(CONFIG_PHY_OCELOT_SERDES) := phy-ocelot-serdes.o
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295
drivers/phy/mscc/phy-ocelot-serdes.c
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295
drivers/phy/mscc/phy-ocelot-serdes.c
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@ -0,0 +1,295 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* SerDes PHY driver for Microsemi Ocelot
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*
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* Copyright (c) 2018 Microsemi
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*
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*/
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#include <linux/err.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <soc/mscc/ocelot_hsio.h>
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#include <dt-bindings/phy/phy-ocelot-serdes.h>
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struct serdes_ctrl {
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struct regmap *regs;
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struct device *dev;
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struct phy *phys[SERDES_MAX];
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};
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struct serdes_macro {
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u8 idx;
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/* Not used when in QSGMII or PCIe mode */
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int port;
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struct serdes_ctrl *ctrl;
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};
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#define MCB_S1G_CFG_TIMEOUT 50
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static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op)
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{
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unsigned int regval;
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regmap_write(regmap, HSIO_MCB_S1G_ADDR_CFG, op |
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HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro)));
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return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval,
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(regval & op) != op, 100,
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MCB_S1G_CFG_TIMEOUT * 1000);
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}
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static int serdes_commit_mcb_s1g(struct regmap *regmap, u8 macro)
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{
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return __serdes_write_mcb_s1g(regmap, macro,
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HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT);
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}
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static int serdes_update_mcb_s1g(struct regmap *regmap, u8 macro)
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{
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return __serdes_write_mcb_s1g(regmap, macro,
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HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT);
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}
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static int serdes_init_s1g(struct regmap *regmap, u8 serdes)
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{
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int ret;
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ret = serdes_update_mcb_s1g(regmap, serdes);
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if (ret)
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return ret;
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regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
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HSIO_S1G_COMMON_CFG_SYS_RST |
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HSIO_S1G_COMMON_CFG_ENA_LANE |
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HSIO_S1G_COMMON_CFG_ENA_ELOOP |
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HSIO_S1G_COMMON_CFG_ENA_FLOOP,
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HSIO_S1G_COMMON_CFG_ENA_LANE);
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regmap_update_bits(regmap, HSIO_S1G_PLL_CFG,
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HSIO_S1G_PLL_CFG_PLL_FSM_ENA |
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HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M,
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HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(200) |
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HSIO_S1G_PLL_CFG_PLL_FSM_ENA);
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regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
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HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA |
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HSIO_S1G_MISC_CFG_LANE_RST,
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HSIO_S1G_MISC_CFG_LANE_RST);
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ret = serdes_commit_mcb_s1g(regmap, serdes);
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if (ret)
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return ret;
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regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
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HSIO_S1G_COMMON_CFG_SYS_RST,
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HSIO_S1G_COMMON_CFG_SYS_RST);
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regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
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HSIO_S1G_MISC_CFG_LANE_RST, 0);
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ret = serdes_commit_mcb_s1g(regmap, serdes);
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if (ret)
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return ret;
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return 0;
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}
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struct serdes_mux {
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u8 idx;
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u8 port;
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enum phy_mode mode;
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u32 mask;
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u32 mux;
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};
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#define SERDES_MUX(_idx, _port, _mode, _mask, _mux) { \
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.idx = _idx, \
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.port = _port, \
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.mode = _mode, \
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.mask = _mask, \
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.mux = _mux, \
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}
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#define SERDES_MUX_SGMII(i, p, m, c) SERDES_MUX(i, p, PHY_MODE_SGMII, m, c)
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#define SERDES_MUX_QSGMII(i, p, m, c) SERDES_MUX(i, p, PHY_MODE_QSGMII, m, c)
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static const struct serdes_mux ocelot_serdes_muxes[] = {
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SERDES_MUX_SGMII(SERDES1G(0), 0, 0, 0),
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SERDES_MUX_SGMII(SERDES1G(1), 1, HSIO_HW_CFG_DEV1G_5_MODE, 0),
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SERDES_MUX_SGMII(SERDES1G(1), 5, HSIO_HW_CFG_QSGMII_ENA |
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HSIO_HW_CFG_DEV1G_5_MODE, HSIO_HW_CFG_DEV1G_5_MODE),
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SERDES_MUX_SGMII(SERDES1G(2), 2, HSIO_HW_CFG_DEV1G_4_MODE, 0),
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SERDES_MUX_SGMII(SERDES1G(2), 4, HSIO_HW_CFG_QSGMII_ENA |
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HSIO_HW_CFG_DEV1G_4_MODE, HSIO_HW_CFG_DEV1G_4_MODE),
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SERDES_MUX_SGMII(SERDES1G(3), 3, HSIO_HW_CFG_DEV1G_6_MODE, 0),
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SERDES_MUX_SGMII(SERDES1G(3), 6, HSIO_HW_CFG_QSGMII_ENA |
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HSIO_HW_CFG_DEV1G_6_MODE, HSIO_HW_CFG_DEV1G_6_MODE),
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SERDES_MUX_SGMII(SERDES1G(4), 4, HSIO_HW_CFG_QSGMII_ENA |
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HSIO_HW_CFG_DEV1G_4_MODE | HSIO_HW_CFG_DEV1G_9_MODE,
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0),
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SERDES_MUX_SGMII(SERDES1G(4), 9, HSIO_HW_CFG_DEV1G_4_MODE |
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HSIO_HW_CFG_DEV1G_9_MODE, HSIO_HW_CFG_DEV1G_4_MODE |
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HSIO_HW_CFG_DEV1G_9_MODE),
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SERDES_MUX_SGMII(SERDES1G(5), 5, HSIO_HW_CFG_QSGMII_ENA |
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HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
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0),
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SERDES_MUX_SGMII(SERDES1G(5), 10, HSIO_HW_CFG_PCIE_ENA |
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HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
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HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE),
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SERDES_MUX_QSGMII(SERDES6G(0), 4, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA),
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SERDES_MUX_QSGMII(SERDES6G(0), 5, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA),
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SERDES_MUX_QSGMII(SERDES6G(0), 6, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA),
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SERDES_MUX_SGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, 0),
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SERDES_MUX_QSGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA),
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SERDES_MUX_SGMII(SERDES6G(1), 8, 0, 0),
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SERDES_MUX_SGMII(SERDES6G(2), 10, HSIO_HW_CFG_PCIE_ENA |
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HSIO_HW_CFG_DEV2G5_10_MODE, 0),
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SERDES_MUX(SERDES6G(2), 10, PHY_MODE_PCIE, HSIO_HW_CFG_PCIE_ENA,
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HSIO_HW_CFG_PCIE_ENA),
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};
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static int serdes_set_mode(struct phy *phy, enum phy_mode mode)
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{
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struct serdes_macro *macro = phy_get_drvdata(phy);
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unsigned int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(ocelot_serdes_muxes); i++) {
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if (macro->idx != ocelot_serdes_muxes[i].idx ||
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mode != ocelot_serdes_muxes[i].mode)
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continue;
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if (mode != PHY_MODE_QSGMII &&
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macro->port != ocelot_serdes_muxes[i].port)
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continue;
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ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG,
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ocelot_serdes_muxes[i].mask,
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ocelot_serdes_muxes[i].mux);
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if (ret)
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return ret;
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if (macro->idx <= SERDES1G_MAX)
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return serdes_init_s1g(macro->ctrl->regs, macro->idx);
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/* SERDES6G and PCIe not supported yet */
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return -EOPNOTSUPP;
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}
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return -EINVAL;
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}
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static const struct phy_ops serdes_ops = {
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.set_mode = serdes_set_mode,
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.owner = THIS_MODULE,
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};
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static struct phy *serdes_simple_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
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unsigned int port, idx, i;
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if (args->args_count != 2)
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return ERR_PTR(-EINVAL);
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port = args->args[0];
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idx = args->args[1];
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for (i = 0; i <= SERDES_MAX; i++) {
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struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
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if (idx != macro->idx)
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continue;
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/* SERDES6G(0) is the only SerDes capable of QSGMII */
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if (idx != SERDES6G(0) && macro->port >= 0)
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return ERR_PTR(-EBUSY);
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macro->port = port;
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return ctrl->phys[i];
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}
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return ERR_PTR(-ENODEV);
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}
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static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
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{
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struct serdes_macro *macro;
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*phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
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if (IS_ERR(*phy))
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return PTR_ERR(*phy);
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macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
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if (!macro)
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return -ENOMEM;
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macro->idx = idx;
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macro->ctrl = ctrl;
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macro->port = -1;
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phy_set_drvdata(*phy, macro);
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return 0;
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}
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static int serdes_probe(struct platform_device *pdev)
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{
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struct phy_provider *provider;
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struct serdes_ctrl *ctrl;
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unsigned int i;
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int ret;
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ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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ctrl->dev = &pdev->dev;
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ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
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if (!ctrl->regs)
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return -ENODEV;
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for (i = 0; i <= SERDES_MAX; i++) {
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ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
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if (ret)
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return ret;
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}
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dev_set_drvdata(&pdev->dev, ctrl);
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provider = devm_of_phy_provider_register(ctrl->dev,
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serdes_simple_xlate);
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return PTR_ERR_OR_ZERO(provider);
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}
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static const struct of_device_id serdes_ids[] = {
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{ .compatible = "mscc,vsc7514-serdes", },
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{},
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};
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MODULE_DEVICE_TABLE(of, serdes_ids);
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static struct platform_driver mscc_ocelot_serdes = {
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.probe = serdes_probe,
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.driver = {
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.name = "mscc,ocelot-serdes",
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.of_match_table = of_match_ptr(serdes_ids),
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},
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};
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module_platform_driver(mscc_ocelot_serdes);
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MODULE_AUTHOR("Quentin Schulz <quentin.schulz@bootlin.com>");
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MODULE_DESCRIPTION("SerDes driver for Microsemi Ocelot");
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MODULE_LICENSE("Dual MIT/GPL");
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