Conversion to match_string helper of open-coded string comparison
and removal of the initial devicetree-based gate-clocks, which were deprecated since 2014. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlsGtG0QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgUE2B/9IoOlNNuueUyyinAcY0XyIzDcnXfqwAbYL +oVlUCyVoIne/Xu7kqk7P9lMoh6YAlzOuDzsIIxmC3Dm/fhrc2Imqj4mwXWGxa9Y hSndozhX642pRtvGbYthDXEY3OUfv11Ys6sq/maku8ssUvX81Lx288Q2sRwkjKQP pr2Qjxo0oqbaKo7nGsPAN7sgTmS+1yO4zoyc0cDLYMIZw6KT23R/LpCA/uuJhMv3 gbe2t8XCFP2/qjhNGcb+rs6znRRDbNwYPcoAImTBAKwUH2KD2LBWFpOBhDnSX5ZX jIHLrpWYK0HhxriqL0oPaME1paRV0FHBw1WHeJ79YPf5wkfdPwGl =VzkZ -----END PGP SIGNATURE----- Merge tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull rockchip clk driver updates from Heiko Stuebner: Conversion to match_string helper of open-coded string comparison and removal of the initial devicetree-based gate-clocks, which were deprecated since 2014. * tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper
This commit is contained in:
Stephen Boyd
commit
533dfd6050
@ -1,77 +0,0 @@
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Device Tree Clock bindings for arch-rockchip
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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== Gate clocks ==
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These bindings are deprecated!
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Please use the soc specific CRU bindings instead.
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The gate registers form a continuos block which makes the dt node
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structure a matter of taste, as either all gates can be put into
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one gate clock spanning all registers or they can be divided into
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the 10 individual gates containing 16 clocks each.
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The code supports both approaches.
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Required properties:
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- compatible : "rockchip,rk2928-gate-clk"
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- reg : shall be the control register address(es) for the clock.
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- #clock-cells : from common clock binding; shall be set to 1
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- clock-output-names : the corresponding gate names that the clock controls
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- clocks : should contain the parent clock for each individual gate,
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therefore the number of clocks elements should match the number of
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clock-output-names
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Example using multiple gate clocks:
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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@ -3,7 +3,6 @@
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# Rockchip Clock specific Makefile
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#
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obj-y += clk-rockchip.o
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-cpu.o
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@ -1,98 +0,0 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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static DEFINE_SPINLOCK(clk_lock);
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/*
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* Gate clocks
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*/
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static void __init rk2928_gate_clk_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void __iomem *reg;
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void __iomem *reg_idx;
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int flags;
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int qty;
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int reg_bit;
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int clkflags = CLK_SET_RATE_PARENT;
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int i;
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qty = of_property_count_strings(node, "clock-output-names");
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if (qty < 0) {
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pr_err("%s: error in clock-output-names %d\n", __func__, qty);
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return;
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}
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if (qty == 0) {
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pr_info("%s: nothing to do\n", __func__);
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return;
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}
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reg = of_iomap(node, 0);
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if (!reg)
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return;
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clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data) {
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iounmap(reg);
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return;
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}
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clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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iounmap(reg);
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return;
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}
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flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
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for (i = 0; i < qty; i++) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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/* ignore empty slots */
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if (!strcmp("reserved", clk_name))
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continue;
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clk_parent = of_clk_get_parent_name(node, i);
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/* keep all gates untouched for now */
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clkflags |= CLK_IGNORE_UNUSED;
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reg_idx = reg + (4 * (i / 16));
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reg_bit = (i % 16);
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, clkflags,
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reg_idx, reg_bit,
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flags,
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&clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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}
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clk_data->clk_num = qty;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
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@ -274,18 +274,10 @@ static struct clk *rockchip_clk_register_frac_branch(
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struct clk_mux *frac_mux = &frac->mux;
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struct clk_init_data init;
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struct clk *mux_clk;
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int i, ret;
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frac->mux_frac_idx = -1;
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for (i = 0; i < child->num_parents; i++) {
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if (!strcmp(name, child->parent_names[i])) {
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pr_debug("%s: found fractional parent in mux at pos %d\n",
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__func__, i);
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frac->mux_frac_idx = i;
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break;
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}
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}
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int ret;
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frac->mux_frac_idx = match_string(child->parent_names,
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child->num_parents, name);
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frac->mux_ops = &clk_mux_ops;
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frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
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@ -312,6 +304,8 @@ static struct clk *rockchip_clk_register_frac_branch(
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/* notifier on the fraction divider to catch rate changes */
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if (frac->mux_frac_idx >= 0) {
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pr_debug("%s: found fractional parent in mux at pos %d\n",
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__func__, frac->mux_frac_idx);
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ret = clk_notifier_register(clk, &frac->clk_nb);
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if (ret)
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pr_err("%s: failed to register clock notifier for %s\n",
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