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drm/xe/xe2: Handle fused-off CCS engines

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On Xe2 platforms, availability of the CCS engines is reflected in the
FUSE4 register.

Bspec: 62483
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-08-11 09:06:09 -07:00 committed by Rodrigo Vivi
parent c5fa58146e
commit 53497182dd
2 changed files with 29 additions and 1 deletions
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1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
View File

@ -152,6 +152,7 @@
/* Fuse readout registers for GT */
#define XEHP_FUSE4 XE_REG(0x9114)
#define CCS_EN_MASK REG_GENMASK(19, 16)
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
#define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140)

29
drivers/gpu/drm/xe/xe_hw_engine.c
View File

@ -550,7 +550,7 @@ static void read_copy_fuses(struct xe_gt *gt)
}
}
static void read_compute_fuses(struct xe_gt *gt)
static void read_compute_fuses_from_dss(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
@ -577,6 +577,33 @@ static void read_compute_fuses(struct xe_gt *gt)
}
}
static void read_compute_fuses_from_reg(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
u32 ccs_mask;
ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4);
ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);
for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
if (!(gt->info.engine_mask & BIT(i)))
continue;
if ((ccs_mask & BIT(j)) == 0) {
gt->info.engine_mask &= ~BIT(i);
drm_info(&xe->drm, "ccs%u fused off\n", j);
}
}
}
static void read_compute_fuses(struct xe_gt *gt)
{
if (GRAPHICS_VER(gt_to_xe(gt)) >= 20)
read_compute_fuses_from_reg(gt);
else
read_compute_fuses_from_dss(gt);
}
int xe_hw_engines_init_early(struct xe_gt *gt)
{
int i;