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drm/amd/display: Check pipe offset before setting vblank

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pipe_ctx has a size of MAX_PIPES so checking its index before accessing
the array.

This fixes an OVERRUN issue reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung 2024-04-22 18:07:17 -06:00 committed by Alex Deucher
parent bd31e5026d
commit 5396a70e8c
1 changed files with 6 additions and 2 deletions
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8
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
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@ -211,8 +211,12 @@ bool dce110_vblank_set(struct irq_service *irq_service,
info->ext_id);
uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
struct timing_generator *tg =
dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
struct timing_generator *tg;
if (pipe_offset >= MAX_PIPES)
return false;
tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
if (enable) {
if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {