arm: pxa: fixes for v4.0-rc5
There are only 2 fixes, one for the zeus board about the regulator changes, where a typo prevented the zeus board from having a working can regulator, and one regression triggered by the interrupts IRQ shift of 16 affecting all boards. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVBzpKAAoJEAP2et0duMsSVngP+wTxRklD/kyjRrB4edOGvnKj yCJdSbw6dK4IQd4K5BbnJKRSxUTZs9TrPA11IB9IznWcoRjHwKkSr6uk5h/bg+vl FwbH60iu7DJ4wyKjIzLCstZpONfFYB/bVOZti3lg+9u0A//YMg0/2PcfcfsUzfgi /SAaYuJe+A0XZNZYGwtBEDyYo9hkDzJPbYMRneQnL8XwjLJ9BvksoqBZ/4aIQXlb gTlUhlCo9wMngfS3Fbhpd+stw/zO1mt0xUXRXwWJYnUSS2x9mz0K/9zz8RWmodtx R4NNz3ZhQzMLHxjj3NpUDcId7faiZNVY0yvSVJU7O5/TLgXluNdH+vRTNiOrpVGu +s/+nxg0HKuK16Tz/0mlQH0uqWvtjJvtNTLS3yDgJKM3civ2Vl+i4DKYK0Ht8ynN ZSBDmARc6Tq8M9JHgzZFAI8ypKACYuIHJzWNF919BuodJ1N2gcexwKo3m6kPoobG WFDTzT+TDiFB0Z4VLOWtWKU9V/RrZqZnrF5rqqkpJ1NyOPdotj+9n2Q63JEdzhH7 eQKSK9P4FcLKtEmlMo/iRI9livkN81nIRRUTsxxrSTjHA8MJAQOBAU7JDs/ic3YX j1vyC/Brd0fPbCqnePfS2BO9G14fwHNb2AxoFgM9JI9zb8sIVxscM4s8uczFCIOs rd6bZsQ6mhKjrObS1iSe =r3W0 -----END PGP SIGNATURE----- Merge tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux into fixes arm: pxa: fixes for v4.0-rc5 There are only 2 fixes, one for the zeus board about the regulator changes, where a typo prevented the zeus board from having a working can regulator, and one regression triggered by the interrupts IRQ shift of 16 affecting all boards. * tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux: ARM: pxa: fix pxa interrupts handling in DT ARM: pxa: Fix typo in zeus.c Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
53b1a66398
@ -619,6 +619,7 @@ config ARCH_PXA
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select HAVE_IDE
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select PLAT_PXA
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select SPARSE_IRQ
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@ -11,6 +11,7 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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@ -40,7 +41,6 @@
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#define ICHP_VAL_IRQ (1 << 31)
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#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
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#define IPR_VALID (1 << 31)
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#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
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#define MAX_INTERNAL_IRQS 128
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@ -51,6 +51,7 @@
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static void __iomem *pxa_irq_base;
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static int pxa_internal_irq_nr;
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static bool cpu_has_ipr;
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static struct irq_domain *pxa_irq_domain;
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static inline void __iomem *irq_base(int i)
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{
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@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i)
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void pxa_mask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
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uint32_t icmr = __raw_readl(base + ICMR);
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icmr &= ~(1 << IRQ_BIT(d->irq));
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icmr &= ~BIT(irq & 0x1f);
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__raw_writel(icmr, base + ICMR);
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}
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void pxa_unmask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
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uint32_t icmr = __raw_readl(base + ICMR);
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icmr |= 1 << IRQ_BIT(d->irq);
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icmr |= BIT(irq & 0x1f);
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__raw_writel(icmr, base + ICMR);
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}
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@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
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} while (1);
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}
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void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
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static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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int irq, i, n;
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void __iomem *base = irq_base(hw / 32);
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BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
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/* initialize interrupt priority */
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if (cpu_has_ipr)
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__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
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irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
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handle_level_irq);
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irq_set_chip_data(virq, base);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops pxa_irq_ops = {
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.map = pxa_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static __init void
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pxa_init_irq_common(struct device_node *node, int irq_nr,
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int (*fn)(struct irq_data *, unsigned int))
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{
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int n;
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pxa_internal_irq_nr = irq_nr;
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cpu_has_ipr = !cpu_is_pxa25x();
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pxa_irq_base = io_p2v(0x40d00000);
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pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
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PXA_IRQ(0), 0,
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&pxa_irq_ops, NULL);
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if (!pxa_irq_domain)
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panic("Unable to add PXA IRQ domain\n");
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irq_set_default_host(pxa_irq_domain);
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for (n = 0; n < irq_nr; n += 32) {
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void __iomem *base = irq_base(n >> 5);
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__raw_writel(0, base + ICMR); /* disable all IRQs */
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__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
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for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
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/* initialize interrupt priority */
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if (cpu_has_ipr)
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__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
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irq = PXA_IRQ(i);
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irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, base);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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/* only unmasked interrupts kick us out of idle */
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__raw_writel(1, irq_base(0) + ICCR);
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pxa_internal_irq_chip.irq_set_wake = fn;
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}
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void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
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{
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BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
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pxa_irq_base = io_p2v(0x40d00000);
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cpu_has_ipr = !cpu_is_pxa25x();
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pxa_init_irq_common(NULL, irq_nr, fn);
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}
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#ifdef CONFIG_PM
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static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
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static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
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@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = {
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};
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#ifdef CONFIG_OF
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static struct irq_domain *pxa_irq_domain;
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static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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void __iomem *base = irq_base(hw / 32);
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/* initialize interrupt priority */
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if (cpu_has_ipr)
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__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
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irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
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handle_level_irq);
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irq_set_chip_data(hw, base);
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set_irq_flags(hw, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops pxa_irq_ops = {
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.map = pxa_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static const struct of_device_id intc_ids[] __initconst = {
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{ .compatible = "marvell,pxa-intc", },
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{}
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@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
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{
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struct device_node *node;
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struct resource res;
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int n, ret;
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int ret;
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node = of_find_matching_node(NULL, intc_ids);
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if (!node) {
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@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
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return;
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}
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pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
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&pxa_irq_ops, NULL);
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if (!pxa_irq_domain)
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panic("Unable to add PXA IRQ domain\n");
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irq_set_default_host(pxa_irq_domain);
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for (n = 0; n < pxa_internal_irq_nr; n += 32) {
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void __iomem *base = irq_base(n >> 5);
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__raw_writel(0, base + ICMR); /* disable all IRQs */
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__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
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}
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/* only unmasked interrupts kick us out of idle */
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__raw_writel(1, irq_base(0) + ICCR);
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pxa_internal_irq_chip.irq_set_wake = fn;
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pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
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}
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#endif /* CONFIG_OF */
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@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
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};
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static struct platform_device can_regulator_device = {
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.name = "reg-fixed-volage",
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.name = "reg-fixed-voltage",
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.id = 0,
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.dev = {
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.platform_data = &can_regulator_pdata,
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