clk: qcom: gcc-sc7280: use parent_hws where possible
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210405224743.590029-21-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Stephen Boyd
parent
041b893be4
commit
53ec3b325f
@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_gpll0_out_even",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_lucid_ops,
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@ -92,8 +92,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_gpll0_out_odd",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_lucid_ops,
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@ -175,8 +175,8 @@ static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_gpll0_main_div_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0_out_even.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0_out_even.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1244,8 +1244,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_cpuss_ahb_postdiv_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_cpuss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1259,8 +1259,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1274,8 +1274,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1379,8 +1379,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_ufs_phy_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_ufs_phy_axi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1399,8 +1399,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_usb3_prim_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_prim_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1419,8 +1419,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre_usb3_sec_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_sec_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1469,8 +1469,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cfg_noc_usb3_prim_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_prim_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1489,8 +1489,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cfg_noc_usb3_sec_axi_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_usb30_sec_master_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1510,8 +1510,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = {
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.enable_mask = BIT(21),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_cpuss_ahb_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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@ -1557,8 +1557,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src = {
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.enable_mask = BIT(7),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_disp_gpll0_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1605,8 +1605,8 @@ static struct clk_branch gcc_gp1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp1_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gp1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1623,8 +1623,8 @@ static struct clk_branch gcc_gp2_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gp2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1641,8 +1641,8 @@ static struct clk_branch gcc_gp3_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gp3_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gp3_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gp3_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1658,8 +1658,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_gpll0_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1675,8 +1675,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
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.enable_mask = BIT(16),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_gpll0_div_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_gpll0_out_even.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0_out_even.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1734,8 +1734,8 @@ static struct clk_branch gcc_pcie0_phy_rchng_clk = {
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.enable_mask = BIT(22),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie0_phy_rchng_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1752,8 +1752,8 @@ static struct clk_branch gcc_pcie1_phy_rchng_clk = {
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.enable_mask = BIT(23),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie1_phy_rchng_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1770,8 +1770,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
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.enable_mask = BIT(3),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_0_aux_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_0_aux_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1816,8 +1816,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_0_pipe_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_0_pipe_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1860,8 +1860,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
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.enable_mask = BIT(29),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_aux_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_1_aux_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1906,8 +1906,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
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.enable_mask = BIT(30),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pcie_1_pipe_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pcie_1_pipe_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1965,8 +1965,8 @@ static struct clk_branch gcc_pdm2_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_pdm2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_pdm2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_pdm2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2084,8 +2084,8 @@ static struct clk_branch gcc_qspi_core_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qspi_core_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qspi_core_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_qspi_core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2128,8 +2128,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
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.enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s0_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2146,8 +2146,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s1_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2164,8 +2164,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s2_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2182,8 +2182,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
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.enable_mask = BIT(13),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s3_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]){
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&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -2200,8 +2200,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
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.enable_mask = BIT(14),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_qupv3_wrap0_s4_clk",
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.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2218,8 +2218,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
|
||||
.enable_mask = BIT(15),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s5_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2236,8 +2236,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
|
||||
.enable_mask = BIT(16),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s6_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2254,8 +2254,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
|
||||
.enable_mask = BIT(17),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap0_s7_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2298,8 +2298,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
|
||||
.enable_mask = BIT(22),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2316,8 +2316,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
|
||||
.enable_mask = BIT(23),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2334,8 +2334,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
|
||||
.enable_mask = BIT(24),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s2_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2352,8 +2352,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
|
||||
.enable_mask = BIT(25),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s3_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2370,8 +2370,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
|
||||
.enable_mask = BIT(26),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s4_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2388,8 +2388,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
|
||||
.enable_mask = BIT(27),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s5_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2406,8 +2406,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
|
||||
.enable_mask = BIT(13),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s6_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2424,8 +2424,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
|
||||
.enable_mask = BIT(14),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_qupv3_wrap1_s7_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2515,8 +2515,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc1_apps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_sdcc1_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2535,8 +2535,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc1_ice_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2566,8 +2566,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc2_apps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_sdcc2_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2597,8 +2597,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sdcc4_apps_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_sdcc4_apps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2618,8 +2618,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_sys_noc_cpuss_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
|
||||
@ -2709,8 +2709,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_axi_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_axi_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2729,8 +2729,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_ice_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2749,8 +2749,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_phy_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2767,8 +2767,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_rx_symbol_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2785,8 +2785,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_rx_symbol_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2803,8 +2803,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_tx_symbol_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2823,8 +2823,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_ufs_phy_unipro_core_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2841,8 +2841,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_prim_master_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb30_prim_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2891,8 +2891,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb30_sec_master_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb30_sec_master_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2941,8 +2941,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2959,8 +2959,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_com_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2979,8 +2979,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_pipe_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -3076,8 +3076,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_sec_phy_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -3094,8 +3094,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_sec_phy_com_aux_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -3114,8 +3114,8 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_sec_phy_pipe_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
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Reference in New Issue
Block a user