diff --git a/.mailmap b/.mailmap index 02d261407683..67dc22ffc9a8 100644 --- a/.mailmap +++ b/.mailmap @@ -137,6 +137,7 @@ Ricardo Ribalda Delgado Rudolf Marek Rui Saraiva Sachin P Sant +Sarangdhar Joshi Sam Ravnborg Santosh Shilimkar Santosh Shilimkar @@ -150,10 +151,13 @@ Shuah Khan Simon Kelley Stéphane Witzmann Stephen Hemminger +Subash Abhinov Kasiviswanathan +Subhash Jadavani Sudeep Holla Sudeep KarkadaNagesha Sumit Semwal Tejun Heo Thomas Graf +Thomas Pedersen Tony Luck Tsuneo Yoshioka Uwe Kleine-König diff --git a/CREDITS b/CREDITS index 10a9eee807b6..c58560701d13 100644 --- a/CREDITS +++ b/CREDITS @@ -3949,8 +3949,6 @@ E: gwingerde@gmail.com D: Ralink rt2x00 WLAN driver D: Minix V2 file-system D: Misc fixes -S: Geessinkweg 177 -S: 7544 TX Enschede S: The Netherlands N: Lars Wirzenius diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 5bd4b07c2f90..c8a8eb1a2b11 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -152,8 +152,6 @@ driver-model/ - directory with info about Linux driver model. early-userspace/ - info about initramfs, klibc, and userspace early during boot. -edac.txt - - information on EDAC - Error Detection And Correction efi-stub.txt - How to use the EFI boot stub to bypass GRUB or elilo on EFI systems. eisa.txt diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index b3bc50f650ee..5a1732b78707 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -294,3 +294,10 @@ Description: a firmware bug to the system vendor. Writing to this file taints the kernel with TAINT_FIRMWARE_WORKAROUND, which reduces the supportability of your system. + +What: /sys/bus/pci/devices/.../revision +Date: November 2016 +Contact: Emil Velikov +Description: + This file contains the revision field of the the PCI device. + The value comes from device config space. The file is read only. diff --git a/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration b/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration index 4cf1e72222d9..ec950c93e5c6 100644 --- a/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration +++ b/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration @@ -1,8 +1,9 @@ -What: Attribute for calibrating ST-Ericsson AB8500 Real Time Clock +What: /sys/class/rtc/rtc0/device/rtc_calibration Date: Oct 2011 KernelVersion: 3.0 Contact: Mark Godfrey -Description: The rtc_calibration attribute allows the userspace to +Description: Attribute for calibrating ST-Ericsson AB8500 Real Time Clock + The rtc_calibration attribute allows the userspace to calibrate the AB8500.s 32KHz Real Time Clock. Every 60 seconds the AB8500 will correct the RTC's value by adding to it the value of this attribute. diff --git a/Documentation/ABI/testing/sysfs-devices-deferred_probe b/Documentation/ABI/testing/sysfs-devices-deferred_probe deleted file mode 100644 index 58553d7a321f..000000000000 --- a/Documentation/ABI/testing/sysfs-devices-deferred_probe +++ /dev/null @@ -1,12 +0,0 @@ -What: /sys/devices/.../deferred_probe -Date: August 2016 -Contact: Ben Hutchings -Description: - The /sys/devices/.../deferred_probe attribute is - present for all devices. If a driver detects during - probing a device that a related device is not yet - ready, it may defer probing of the first device. The - kernel will retry probing the first device after any - other device is successfully probed. This attribute - reads as 1 if probing of this device is currently - deferred, or 0 otherwise. diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 498741737055..2a4a423d08e0 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes the modified cache line is written to main memory only when it is replaced + +What: /sys/devices/system/cpu/cpu*/cache/index*/id +Date: September 2016 +Contact: Linux kernel mailing list +Description: Cache id + + The id provides a unique number for a specific instance of + a cache of a particular type. E.g. there may be a level + 3 unified cache on each socket in a server and we may + assign them ids 0, 1, 2, ... + + Note that id value can be non-contiguous. E.g. level 1 + caches typically exist per core, but there may not be a + power of two cores on a socket, so these caches may be + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ... + What: /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub_turbo_stat diff --git a/Documentation/ABI/testing/sysfs-platform-sst-atom b/Documentation/ABI/testing/sysfs-platform-sst-atom new file mode 100644 index 000000000000..0d07c0395660 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-sst-atom @@ -0,0 +1,17 @@ +What: /sys/devices/platform/8086%x:00/firmware_version +Date: November 2016 +KernelVersion: 4.10 +Contact: "Sebastien Guiriec" +Description: + LPE Firmware version for SST driver on all atom + plaforms (BYT/CHT/Merrifield/BSW). + If the FW has never been loaded it will display: + "FW not yet loaded" + If FW has been loaded it will display: + "v01.aa.bb.cc" + aa: Major version is reflecting SoC version: + 0d: BYT FW + 0b: BSW FW + 07: Merrifield FW + bb: Minor version + cc: Build version diff --git a/Documentation/Changes b/Documentation/Changes new file mode 120000 index 000000000000..7564ae1682ba --- /dev/null +++ b/Documentation/Changes @@ -0,0 +1 @@ +process/changes.rst \ No newline at end of file diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile index caab9039362f..a6eb7dcd4dd5 100644 --- a/Documentation/DocBook/Makefile +++ b/Documentation/DocBook/Makefile @@ -12,8 +12,8 @@ DOCBOOKS := z8530book.xml \ kernel-api.xml filesystems.xml lsm.xml kgdb.xml \ gadget.xml libata.xml mtdnand.xml librs.xml rapidio.xml \ genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \ - 80211.xml sh.xml regulator.xml w1.xml \ - writing_musb_glue_layer.xml crypto-API.xml iio.xml + sh.xml regulator.xml w1.xml \ + writing_musb_glue_layer.xml iio.xml ifeq ($(DOCBOOKS),) diff --git a/Documentation/DocBook/crypto-API.tmpl b/Documentation/DocBook/crypto-API.tmpl deleted file mode 100644 index 088b79c341ff..000000000000 --- a/Documentation/DocBook/crypto-API.tmpl +++ /dev/null @@ -1,2092 +0,0 @@ - - - - - - Linux Kernel Crypto API - - - - Stephan - Mueller - -
- smueller@chronox.de -
- - - - Marek - Vasut - -
- marek@denx.de -
- - - - - - 2014 - Stephan Mueller - - - - - - This documentation is free software; you can redistribute - it and/or modify it under the terms of the GNU General Public - License as published by the Free Software Foundation; either - version 2 of the License, or (at your option) any later - version. - - - - This program is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU General Public License for more details. - - - - You should have received a copy of the GNU General Public - License along with this program; if not, write to the Free - Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, - MA 02111-1307 USA - - - - For more details see the file COPYING in the source - distribution of Linux. - - - - - - - - Kernel Crypto API Interface Specification - - Introduction - - - The kernel crypto API offers a rich set of cryptographic ciphers as - well as other data transformation mechanisms and methods to invoke - these. This document contains a description of the API and provides - example code. - - - - To understand and properly use the kernel crypto API a brief - explanation of its structure is given. Based on the architecture, - the API can be separated into different components. Following the - architecture specification, hints to developers of ciphers are - provided. Pointers to the API function call documentation are - given at the end. - - - - The kernel crypto API refers to all algorithms as "transformations". - Therefore, a cipher handle variable usually has the name "tfm". - Besides cryptographic operations, the kernel crypto API also knows - compression transformations and handles them the same way as ciphers. - - - - The kernel crypto API serves the following entity types: - - - - consumers requesting cryptographic services - - - data transformation implementations (typically ciphers) - that can be called by consumers using the kernel crypto - API - - - - - - This specification is intended for consumers of the kernel crypto - API as well as for developers implementing ciphers. This API - specification, however, does not discuss all API calls available - to data transformation implementations (i.e. implementations of - ciphers and other transformations (such as CRC or even compression - algorithms) that can register with the kernel crypto API). - - - - Note: The terms "transformation" and cipher algorithm are used - interchangeably. - - - - Terminology - - The transformation implementation is an actual code or interface - to hardware which implements a certain transformation with precisely - defined behavior. - - - - The transformation object (TFM) is an instance of a transformation - implementation. There can be multiple transformation objects - associated with a single transformation implementation. Each of - those transformation objects is held by a crypto API consumer or - another transformation. Transformation object is allocated when a - crypto API consumer requests a transformation implementation. - The consumer is then provided with a structure, which contains - a transformation object (TFM). - - - - The structure that contains transformation objects may also be - referred to as a "cipher handle". Such a cipher handle is always - subject to the following phases that are reflected in the API calls - applicable to such a cipher handle: - - - - - Initialization of a cipher handle. - - - Execution of all intended cipher operations applicable - for the handle where the cipher handle must be furnished to - every API call. - - - Destruction of a cipher handle. - - - - - When using the initialization API calls, a cipher handle is - created and returned to the consumer. Therefore, please refer - to all initialization API calls that refer to the data - structure type a consumer is expected to receive and subsequently - to use. The initialization API calls have all the same naming - conventions of crypto_alloc_*. - - - - The transformation context is private data associated with - the transformation object. - - - - - Kernel Crypto API Architecture - Cipher algorithm types - - The kernel crypto API provides different API calls for the - following cipher types: - - - Symmetric ciphers - AEAD ciphers - Message digest, including keyed message digest - Random number generation - User space interface - - - - - Ciphers And Templates - - The kernel crypto API provides implementations of single block - ciphers and message digests. In addition, the kernel crypto API - provides numerous "templates" that can be used in conjunction - with the single block ciphers and message digests. Templates - include all types of block chaining mode, the HMAC mechanism, etc. - - - - Single block ciphers and message digests can either be directly - used by a caller or invoked together with a template to form - multi-block ciphers or keyed message digests. - - - - A single block cipher may even be called with multiple templates. - However, templates cannot be used without a single cipher. - - - - See /proc/crypto and search for "name". For example: - - - aes - ecb(aes) - cmac(aes) - ccm(aes) - rfc4106(gcm(aes)) - sha1 - hmac(sha1) - authenc(hmac(sha1),cbc(aes)) - - - - - In these examples, "aes" and "sha1" are the ciphers and all - others are the templates. - - - - Synchronous And Asynchronous Operation - - The kernel crypto API provides synchronous and asynchronous - API operations. - - - - When using the synchronous API operation, the caller invokes - a cipher operation which is performed synchronously by the - kernel crypto API. That means, the caller waits until the - cipher operation completes. Therefore, the kernel crypto API - calls work like regular function calls. For synchronous - operation, the set of API calls is small and conceptually - similar to any other crypto library. - - - - Asynchronous operation is provided by the kernel crypto API - which implies that the invocation of a cipher operation will - complete almost instantly. That invocation triggers the - cipher operation but it does not signal its completion. Before - invoking a cipher operation, the caller must provide a callback - function the kernel crypto API can invoke to signal the - completion of the cipher operation. Furthermore, the caller - must ensure it can handle such asynchronous events by applying - appropriate locking around its data. The kernel crypto API - does not perform any special serialization operation to protect - the caller's data integrity. - - - - Crypto API Cipher References And Priority - - A cipher is referenced by the caller with a string. That string - has the following semantics: - - - template(single block cipher) - - - where "template" and "single block cipher" is the aforementioned - template and single block cipher, respectively. If applicable, - additional templates may enclose other templates, such as - - - template1(template2(single block cipher))) - - - - - The kernel crypto API may provide multiple implementations of a - template or a single block cipher. For example, AES on newer - Intel hardware has the following implementations: AES-NI, - assembler implementation, or straight C. Now, when using the - string "aes" with the kernel crypto API, which cipher - implementation is used? The answer to that question is the - priority number assigned to each cipher implementation by the - kernel crypto API. When a caller uses the string to refer to a - cipher during initialization of a cipher handle, the kernel - crypto API looks up all implementations providing an - implementation with that name and selects the implementation - with the highest priority. - - - - Now, a caller may have the need to refer to a specific cipher - implementation and thus does not want to rely on the - priority-based selection. To accommodate this scenario, the - kernel crypto API allows the cipher implementation to register - a unique name in addition to common names. When using that - unique name, a caller is therefore always sure to refer to - the intended cipher implementation. - - - - The list of available ciphers is given in /proc/crypto. However, - that list does not specify all possible permutations of - templates and ciphers. Each block listed in /proc/crypto may - contain the following information -- if one of the components - listed as follows are not applicable to a cipher, it is not - displayed: - - - - - name: the generic name of the cipher that is subject - to the priority-based selection -- this name can be used by - the cipher allocation API calls (all names listed above are - examples for such generic names) - - - driver: the unique name of the cipher -- this name can - be used by the cipher allocation API calls - - - module: the kernel module providing the cipher - implementation (or "kernel" for statically linked ciphers) - - - priority: the priority value of the cipher implementation - - - refcnt: the reference count of the respective cipher - (i.e. the number of current consumers of this cipher) - - - selftest: specification whether the self test for the - cipher passed - - - type: - - - skcipher for symmetric key ciphers - - - cipher for single block ciphers that may be used with - an additional template - - - shash for synchronous message digest - - - ahash for asynchronous message digest - - - aead for AEAD cipher type - - - compression for compression type transformations - - - rng for random number generator - - - givcipher for cipher with associated IV generator - (see the geniv entry below for the specification of the - IV generator type used by the cipher implementation) - - - - - - blocksize: blocksize of cipher in bytes - - - keysize: key size in bytes - - - ivsize: IV size in bytes - - - seedsize: required size of seed data for random number - generator - - - digestsize: output size of the message digest - - - geniv: IV generation type: - - - eseqiv for encrypted sequence number based IV - generation - - - seqiv for sequence number based IV generation - - - chainiv for chain iv generation - - - <builtin> is a marker that the cipher implements - IV generation and handling as it is specific to the given - cipher - - - - - - - - Key Sizes - - When allocating a cipher handle, the caller only specifies the - cipher type. Symmetric ciphers, however, typically support - multiple key sizes (e.g. AES-128 vs. AES-192 vs. AES-256). - These key sizes are determined with the length of the provided - key. Thus, the kernel crypto API does not provide a separate - way to select the particular symmetric cipher key size. - - - - Cipher Allocation Type And Masks - - The different cipher handle allocation functions allow the - specification of a type and mask flag. Both parameters have - the following meaning (and are therefore not covered in the - subsequent sections). - - - - The type flag specifies the type of the cipher algorithm. - The caller usually provides a 0 when the caller wants the - default handling. Otherwise, the caller may provide the - following selections which match the aforementioned cipher - types: - - - - - CRYPTO_ALG_TYPE_CIPHER Single block cipher - - - CRYPTO_ALG_TYPE_COMPRESS Compression - - - CRYPTO_ALG_TYPE_AEAD Authenticated Encryption with - Associated Data (MAC) - - - CRYPTO_ALG_TYPE_BLKCIPHER Synchronous multi-block cipher - - - CRYPTO_ALG_TYPE_ABLKCIPHER Asynchronous multi-block cipher - - - CRYPTO_ALG_TYPE_GIVCIPHER Asynchronous multi-block - cipher packed together with an IV generator (see geniv field - in the /proc/crypto listing for the known IV generators) - - - CRYPTO_ALG_TYPE_DIGEST Raw message digest - - - CRYPTO_ALG_TYPE_HASH Alias for CRYPTO_ALG_TYPE_DIGEST - - - CRYPTO_ALG_TYPE_SHASH Synchronous multi-block hash - - - CRYPTO_ALG_TYPE_AHASH Asynchronous multi-block hash - - - CRYPTO_ALG_TYPE_RNG Random Number Generation - - - CRYPTO_ALG_TYPE_AKCIPHER Asymmetric cipher - - - CRYPTO_ALG_TYPE_PCOMPRESS Enhanced version of - CRYPTO_ALG_TYPE_COMPRESS allowing for segmented compression / - decompression instead of performing the operation on one - segment only. CRYPTO_ALG_TYPE_PCOMPRESS is intended to replace - CRYPTO_ALG_TYPE_COMPRESS once existing consumers are converted. - - - - - The mask flag restricts the type of cipher. The only allowed - flag is CRYPTO_ALG_ASYNC to restrict the cipher lookup function - to asynchronous ciphers. Usually, a caller provides a 0 for the - mask flag. - - - - When the caller provides a mask and type specification, the - caller limits the search the kernel crypto API can perform for - a suitable cipher implementation for the given cipher name. - That means, even when a caller uses a cipher name that exists - during its initialization call, the kernel crypto API may not - select it due to the used type and mask field. - - - - Internal Structure of Kernel Crypto API - - - The kernel crypto API has an internal structure where a cipher - implementation may use many layers and indirections. This section - shall help to clarify how the kernel crypto API uses - various components to implement the complete cipher. - - - - The following subsections explain the internal structure based - on existing cipher implementations. The first section addresses - the most complex scenario where all other scenarios form a logical - subset. - - - Generic AEAD Cipher Structure - - - The following ASCII art decomposes the kernel crypto API layers - when using the AEAD cipher with the automated IV generation. The - shown example is used by the IPSEC layer. - - - - For other use cases of AEAD ciphers, the ASCII art applies as - well, but the caller may not use the AEAD cipher with a separate - IV generator. In this case, the caller must generate the IV. - - - - The depicted example decomposes the AEAD cipher of GCM(AES) based - on the generic C implementations (gcm.c, aes-generic.c, ctr.c, - ghash-generic.c, seqiv.c). The generic implementation serves as an - example showing the complete logic of the kernel crypto API. - - - - It is possible that some streamlined cipher implementations (like - AES-NI) provide implementations merging aspects which in the view - of the kernel crypto API cannot be decomposed into layers any more. - In case of the AES-NI implementation, the CTR mode, the GHASH - implementation and the AES cipher are all merged into one cipher - implementation registered with the kernel crypto API. In this case, - the concept described by the following ASCII art applies too. However, - the decomposition of GCM into the individual sub-components - by the kernel crypto API is not done any more. - - - - Each block in the following ASCII art is an independent cipher - instance obtained from the kernel crypto API. Each block - is accessed by the caller or by other blocks using the API functions - defined by the kernel crypto API for the cipher implementation type. - - - - The blocks below indicate the cipher type as well as the specific - logic implemented in the cipher. - - - - The ASCII art picture also indicates the call structure, i.e. who - calls which component. The arrows point to the invoked block - where the caller uses the API applicable to the cipher type - specified for the block. - - - - - - - - The following call sequence is applicable when the IPSEC layer - triggers an encryption operation with the esp_output function. During - configuration, the administrator set up the use of rfc4106(gcm(aes)) as - the cipher for ESP. The following call sequence is now depicted in the - ASCII art above: - - - - - - esp_output() invokes crypto_aead_encrypt() to trigger an encryption - operation of the AEAD cipher with IV generator. - - - - In case of GCM, the SEQIV implementation is registered as GIVCIPHER - in crypto_rfc4106_alloc(). - - - - The SEQIV performs its operation to generate an IV where the core - function is seqiv_geniv(). - - - - - - Now, SEQIV uses the AEAD API function calls to invoke the associated - AEAD cipher. In our case, during the instantiation of SEQIV, the - cipher handle for GCM is provided to SEQIV. This means that SEQIV - invokes AEAD cipher operations with the GCM cipher handle. - - - - During instantiation of the GCM handle, the CTR(AES) and GHASH - ciphers are instantiated. The cipher handles for CTR(AES) and GHASH - are retained for later use. - - - - The GCM implementation is responsible to invoke the CTR mode AES and - the GHASH cipher in the right manner to implement the GCM - specification. - - - - - - The GCM AEAD cipher type implementation now invokes the SKCIPHER API - with the instantiated CTR(AES) cipher handle. - - - - During instantiation of the CTR(AES) cipher, the CIPHER type - implementation of AES is instantiated. The cipher handle for AES is - retained. - - - - That means that the SKCIPHER implementation of CTR(AES) only - implements the CTR block chaining mode. After performing the block - chaining operation, the CIPHER implementation of AES is invoked. - - - - - - The SKCIPHER of CTR(AES) now invokes the CIPHER API with the AES - cipher handle to encrypt one block. - - - - - - The GCM AEAD implementation also invokes the GHASH cipher - implementation via the AHASH API. - - - - - - When the IPSEC layer triggers the esp_input() function, the same call - sequence is followed with the only difference that the operation starts - with step (2). - - - - Generic Block Cipher Structure - - Generic block ciphers follow the same concept as depicted with the ASCII - art picture above. - - - - For example, CBC(AES) is implemented with cbc.c, and aes-generic.c. The - ASCII art picture above applies as well with the difference that only - step (4) is used and the SKCIPHER block chaining mode is CBC. - - - - Generic Keyed Message Digest Structure - - Keyed message digest implementations again follow the same concept as - depicted in the ASCII art picture above. - - - - For example, HMAC(SHA256) is implemented with hmac.c and - sha256_generic.c. The following ASCII art illustrates the - implementation: - - - - - - - - The following call sequence is applicable when a caller triggers - an HMAC operation: - - - - - - The AHASH API functions are invoked by the caller. The HMAC - implementation performs its operation as needed. - - - - During initialization of the HMAC cipher, the SHASH cipher type of - SHA256 is instantiated. The cipher handle for the SHA256 instance is - retained. - - - - At one time, the HMAC implementation requires a SHA256 operation - where the SHA256 cipher handle is used. - - - - - - The HMAC instance now invokes the SHASH API with the SHA256 - cipher handle to calculate the message digest. - - - - - - - - Developing Cipher Algorithms - Registering And Unregistering Transformation - - There are three distinct types of registration functions in - the Crypto API. One is used to register a generic cryptographic - transformation, while the other two are specific to HASH - transformations and COMPRESSion. We will discuss the latter - two in a separate chapter, here we will only look at the - generic ones. - - - - Before discussing the register functions, the data structure - to be filled with each, struct crypto_alg, must be considered - -- see below for a description of this data structure. - - - - The generic registration functions can be found in - include/linux/crypto.h and their definition can be seen below. - The former function registers a single transformation, while - the latter works on an array of transformation descriptions. - The latter is useful when registering transformations in bulk, - for example when a driver implements multiple transformations. - - - - int crypto_register_alg(struct crypto_alg *alg); - int crypto_register_algs(struct crypto_alg *algs, int count); - - - - The counterparts to those functions are listed below. - - - - int crypto_unregister_alg(struct crypto_alg *alg); - int crypto_unregister_algs(struct crypto_alg *algs, int count); - - - - Notice that both registration and unregistration functions - do return a value, so make sure to handle errors. A return - code of zero implies success. Any return code < 0 implies - an error. - - - - The bulk registration/unregistration functions - register/unregister each transformation in the given array of - length count. They handle errors as follows: - - - - - crypto_register_algs() succeeds if and only if it - successfully registers all the given transformations. If an - error occurs partway through, then it rolls back successful - registrations before returning the error code. Note that if - a driver needs to handle registration errors for individual - transformations, then it will need to use the non-bulk - function crypto_register_alg() instead. - - - - - crypto_unregister_algs() tries to unregister all the given - transformations, continuing on error. It logs errors and - always returns zero. - - - - - - - Single-Block Symmetric Ciphers [CIPHER] - - Example of transformations: aes, arc4, ... - - - - This section describes the simplest of all transformation - implementations, that being the CIPHER type used for symmetric - ciphers. The CIPHER type is used for transformations which - operate on exactly one block at a time and there are no - dependencies between blocks at all. - - - Registration specifics - - The registration of [CIPHER] algorithm is specific in that - struct crypto_alg field .cra_type is empty. The .cra_u.cipher - has to be filled in with proper callbacks to implement this - transformation. - - - - See struct cipher_alg below. - - - - Cipher Definition With struct cipher_alg - - Struct cipher_alg defines a single block cipher. - - - - Here are schematics of how these functions are called when - operated from other part of the kernel. Note that the - .cia_setkey() call might happen before or after any of these - schematics happen, but must not happen during any of these - are in-flight. - - - - - KEY ---. PLAINTEXT ---. - v v - .cia_setkey() -> .cia_encrypt() - | - '-----> CIPHERTEXT - - - - - Please note that a pattern where .cia_setkey() is called - multiple times is also valid: - - - - - - KEY1 --. PLAINTEXT1 --. KEY2 --. PLAINTEXT2 --. - v v v v - .cia_setkey() -> .cia_encrypt() -> .cia_setkey() -> .cia_encrypt() - | | - '---> CIPHERTEXT1 '---> CIPHERTEXT2 - - - - - - - Multi-Block Ciphers - - Example of transformations: cbc(aes), ecb(arc4), ... - - - - This section describes the multi-block cipher transformation - implementations. The multi-block ciphers are - used for transformations which operate on scatterlists of - data supplied to the transformation functions. They output - the result into a scatterlist of data as well. - - - Registration Specifics - - - The registration of multi-block cipher algorithms - is one of the most standard procedures throughout the crypto API. - - - - Note, if a cipher implementation requires a proper alignment - of data, the caller should use the functions of - crypto_skcipher_alignmask() to identify a memory alignment mask. - The kernel crypto API is able to process requests that are unaligned. - This implies, however, additional overhead as the kernel - crypto API needs to perform the realignment of the data which - may imply moving of data. - - - - Cipher Definition With struct blkcipher_alg and ablkcipher_alg - - Struct blkcipher_alg defines a synchronous block cipher whereas - struct ablkcipher_alg defines an asynchronous block cipher. - - - - Please refer to the single block cipher description for schematics - of the block cipher usage. - - - - Specifics Of Asynchronous Multi-Block Cipher - - There are a couple of specifics to the asynchronous interface. - - - - First of all, some of the drivers will want to use the - Generic ScatterWalk in case the hardware needs to be fed - separate chunks of the scatterlist which contains the - plaintext and will contain the ciphertext. Please refer - to the ScatterWalk interface offered by the Linux kernel - scatter / gather list implementation. - - - - - Hashing [HASH] - - - Example of transformations: crc32, md5, sha1, sha256,... - - - Registering And Unregistering The Transformation - - - There are multiple ways to register a HASH transformation, - depending on whether the transformation is synchronous [SHASH] - or asynchronous [AHASH] and the amount of HASH transformations - we are registering. You can find the prototypes defined in - include/crypto/internal/hash.h: - - - - int crypto_register_ahash(struct ahash_alg *alg); - - int crypto_register_shash(struct shash_alg *alg); - int crypto_register_shashes(struct shash_alg *algs, int count); - - - - The respective counterparts for unregistering the HASH - transformation are as follows: - - - - int crypto_unregister_ahash(struct ahash_alg *alg); - - int crypto_unregister_shash(struct shash_alg *alg); - int crypto_unregister_shashes(struct shash_alg *algs, int count); - - - - Cipher Definition With struct shash_alg and ahash_alg - - Here are schematics of how these functions are called when - operated from other part of the kernel. Note that the .setkey() - call might happen before or after any of these schematics happen, - but must not happen during any of these are in-flight. Please note - that calling .init() followed immediately by .finish() is also a - perfectly valid transformation. - - - - I) DATA -----------. - v - .init() -> .update() -> .final() ! .update() might not be called - ^ | | at all in this scenario. - '----' '---> HASH - - II) DATA -----------.-----------. - v v - .init() -> .update() -> .finup() ! .update() may not be called - ^ | | at all in this scenario. - '----' '---> HASH - - III) DATA -----------. - v - .digest() ! The entire process is handled - | by the .digest() call. - '---------------> HASH - - - - Here is a schematic of how the .export()/.import() functions are - called when used from another part of the kernel. - - - - KEY--. DATA--. - v v ! .update() may not be called - .setkey() -> .init() -> .update() -> .export() at all in this scenario. - ^ | | - '-----' '--> PARTIAL_HASH - - ----------- other transformations happen here ----------- - - PARTIAL_HASH--. DATA1--. - v v - .import -> .update() -> .final() ! .update() may not be called - ^ | | at all in this scenario. - '----' '--> HASH1 - - PARTIAL_HASH--. DATA2-. - v v - .import -> .finup() - | - '---------------> HASH2 - - - - Specifics Of Asynchronous HASH Transformation - - Some of the drivers will want to use the Generic ScatterWalk - in case the implementation needs to be fed separate chunks of the - scatterlist which contains the input data. The buffer containing - the resulting hash will always be properly aligned to - .cra_alignmask so there is no need to worry about this. - - - - - - User Space Interface - Introduction - - The concepts of the kernel crypto API visible to kernel space is fully - applicable to the user space interface as well. Therefore, the kernel - crypto API high level discussion for the in-kernel use cases applies - here as well. - - - - The major difference, however, is that user space can only act as a - consumer and never as a provider of a transformation or cipher algorithm. - - - - The following covers the user space interface exported by the kernel - crypto API. A working example of this description is libkcapi that - can be obtained from [1]. That library can be used by user space - applications that require cryptographic services from the kernel. - - - - Some details of the in-kernel kernel crypto API aspects do not - apply to user space, however. This includes the difference between - synchronous and asynchronous invocations. The user space API call - is fully synchronous. - - - - [1] http://www.chronox.de/libkcapi.html - - - - - User Space API General Remarks - - The kernel crypto API is accessible from user space. Currently, - the following ciphers are accessible: - - - - - Message digest including keyed message digest (HMAC, CMAC) - - - - Symmetric ciphers - - - - AEAD ciphers - - - - Random Number Generators - - - - - The interface is provided via socket type using the type AF_ALG. - In addition, the setsockopt option type is SOL_ALG. In case the - user space header files do not export these flags yet, use the - following macros: - - - -#ifndef AF_ALG -#define AF_ALG 38 -#endif -#ifndef SOL_ALG -#define SOL_ALG 279 -#endif - - - - A cipher is accessed with the same name as done for the in-kernel - API calls. This includes the generic vs. unique naming schema for - ciphers as well as the enforcement of priorities for generic names. - - - - To interact with the kernel crypto API, a socket must be - created by the user space application. User space invokes the cipher - operation with the send()/write() system call family. The result of the - cipher operation is obtained with the read()/recv() system call family. - - - - The following API calls assume that the socket descriptor - is already opened by the user space application and discusses only - the kernel crypto API specific invocations. - - - - To initialize the socket interface, the following sequence has to - be performed by the consumer: - - - - - - Create a socket of type AF_ALG with the struct sockaddr_alg - parameter specified below for the different cipher types. - - - - - - Invoke bind with the socket descriptor - - - - - - Invoke accept with the socket descriptor. The accept system call - returns a new file descriptor that is to be used to interact with - the particular cipher instance. When invoking send/write or recv/read - system calls to send data to the kernel or obtain data from the - kernel, the file descriptor returned by accept must be used. - - - - - - In-place Cipher operation - - Just like the in-kernel operation of the kernel crypto API, the user - space interface allows the cipher operation in-place. That means that - the input buffer used for the send/write system call and the output - buffer used by the read/recv system call may be one and the same. - This is of particular interest for symmetric cipher operations where a - copying of the output data to its final destination can be avoided. - - - - If a consumer on the other hand wants to maintain the plaintext and - the ciphertext in different memory locations, all a consumer needs - to do is to provide different memory pointers for the encryption and - decryption operation. - - - - Message Digest API - - The message digest type to be used for the cipher operation is - selected when invoking the bind syscall. bind requires the caller - to provide a filled struct sockaddr data structure. This data - structure must be filled as follows: - - - -struct sockaddr_alg sa = { - .salg_family = AF_ALG, - .salg_type = "hash", /* this selects the hash logic in the kernel */ - .salg_name = "sha1" /* this is the cipher name */ -}; - - - - The salg_type value "hash" applies to message digests and keyed - message digests. Though, a keyed message digest is referenced by - the appropriate salg_name. Please see below for the setsockopt - interface that explains how the key can be set for a keyed message - digest. - - - - Using the send() system call, the application provides the data that - should be processed with the message digest. The send system call - allows the following flags to be specified: - - - - - - MSG_MORE: If this flag is set, the send system call acts like a - message digest update function where the final hash is not - yet calculated. If the flag is not set, the send system call - calculates the final message digest immediately. - - - - - - With the recv() system call, the application can read the message - digest from the kernel crypto API. If the buffer is too small for the - message digest, the flag MSG_TRUNC is set by the kernel. - - - - In order to set a message digest key, the calling application must use - the setsockopt() option of ALG_SET_KEY. If the key is not set the HMAC - operation is performed without the initial HMAC state change caused by - the key. - - - - Symmetric Cipher API - - The operation is very similar to the message digest discussion. - During initialization, the struct sockaddr data structure must be - filled as follows: - - - -struct sockaddr_alg sa = { - .salg_family = AF_ALG, - .salg_type = "skcipher", /* this selects the symmetric cipher */ - .salg_name = "cbc(aes)" /* this is the cipher name */ -}; - - - - Before data can be sent to the kernel using the write/send system - call family, the consumer must set the key. The key setting is - described with the setsockopt invocation below. - - - - Using the sendmsg() system call, the application provides the data that should be processed for encryption or decryption. In addition, the IV is - specified with the data structure provided by the sendmsg() system call. - - - - The sendmsg system call parameter of struct msghdr is embedded into the - struct cmsghdr data structure. See recv(2) and cmsg(3) for more - information on how the cmsghdr data structure is used together with the - send/recv system call family. That cmsghdr data structure holds the - following information specified with a separate header instances: - - - - - - specification of the cipher operation type with one of these flags: - - - - ALG_OP_ENCRYPT - encryption of data - - - ALG_OP_DECRYPT - decryption of data - - - - - - - specification of the IV information marked with the flag ALG_SET_IV - - - - - - The send system call family allows the following flag to be specified: - - - - - - MSG_MORE: If this flag is set, the send system call acts like a - cipher update function where more input data is expected - with a subsequent invocation of the send system call. - - - - - - Note: The kernel reports -EINVAL for any unexpected data. The caller - must make sure that all data matches the constraints given in - /proc/crypto for the selected cipher. - - - - With the recv() system call, the application can read the result of - the cipher operation from the kernel crypto API. The output buffer - must be at least as large as to hold all blocks of the encrypted or - decrypted data. If the output data size is smaller, only as many - blocks are returned that fit into that output buffer size. - - - - AEAD Cipher API - - The operation is very similar to the symmetric cipher discussion. - During initialization, the struct sockaddr data structure must be - filled as follows: - - - -struct sockaddr_alg sa = { - .salg_family = AF_ALG, - .salg_type = "aead", /* this selects the symmetric cipher */ - .salg_name = "gcm(aes)" /* this is the cipher name */ -}; - - - - Before data can be sent to the kernel using the write/send system - call family, the consumer must set the key. The key setting is - described with the setsockopt invocation below. - - - - In addition, before data can be sent to the kernel using the - write/send system call family, the consumer must set the authentication - tag size. To set the authentication tag size, the caller must use the - setsockopt invocation described below. - - - - Using the sendmsg() system call, the application provides the data that should be processed for encryption or decryption. In addition, the IV is - specified with the data structure provided by the sendmsg() system call. - - - - The sendmsg system call parameter of struct msghdr is embedded into the - struct cmsghdr data structure. See recv(2) and cmsg(3) for more - information on how the cmsghdr data structure is used together with the - send/recv system call family. That cmsghdr data structure holds the - following information specified with a separate header instances: - - - - - - specification of the cipher operation type with one of these flags: - - - - ALG_OP_ENCRYPT - encryption of data - - - ALG_OP_DECRYPT - decryption of data - - - - - - - specification of the IV information marked with the flag ALG_SET_IV - - - - - - specification of the associated authentication data (AAD) with the - flag ALG_SET_AEAD_ASSOCLEN. The AAD is sent to the kernel together - with the plaintext / ciphertext. See below for the memory structure. - - - - - - The send system call family allows the following flag to be specified: - - - - - - MSG_MORE: If this flag is set, the send system call acts like a - cipher update function where more input data is expected - with a subsequent invocation of the send system call. - - - - - - Note: The kernel reports -EINVAL for any unexpected data. The caller - must make sure that all data matches the constraints given in - /proc/crypto for the selected cipher. - - - - With the recv() system call, the application can read the result of - the cipher operation from the kernel crypto API. The output buffer - must be at least as large as defined with the memory structure below. - If the output data size is smaller, the cipher operation is not performed. - - - - The authenticated decryption operation may indicate an integrity error. - Such breach in integrity is marked with the -EBADMSG error code. - - - AEAD Memory Structure - - The AEAD cipher operates with the following information that - is communicated between user and kernel space as one data stream: - - - - - plaintext or ciphertext - - - - associated authentication data (AAD) - - - - authentication tag - - - - - The sizes of the AAD and the authentication tag are provided with - the sendmsg and setsockopt calls (see there). As the kernel knows - the size of the entire data stream, the kernel is now able to - calculate the right offsets of the data components in the data - stream. - - - - The user space caller must arrange the aforementioned information - in the following order: - - - - - - AEAD encryption input: AAD || plaintext - - - - - - AEAD decryption input: AAD || ciphertext || authentication tag - - - - - - The output buffer the user space caller provides must be at least as - large to hold the following data: - - - - - - AEAD encryption output: ciphertext || authentication tag - - - - - - AEAD decryption output: plaintext - - - - - - - Random Number Generator API - - Again, the operation is very similar to the other APIs. - During initialization, the struct sockaddr data structure must be - filled as follows: - - - -struct sockaddr_alg sa = { - .salg_family = AF_ALG, - .salg_type = "rng", /* this selects the symmetric cipher */ - .salg_name = "drbg_nopr_sha256" /* this is the cipher name */ -}; - - - - Depending on the RNG type, the RNG must be seeded. The seed is provided - using the setsockopt interface to set the key. For example, the - ansi_cprng requires a seed. The DRBGs do not require a seed, but - may be seeded. - - - - Using the read()/recvmsg() system calls, random numbers can be obtained. - The kernel generates at most 128 bytes in one call. If user space - requires more data, multiple calls to read()/recvmsg() must be made. - - - - WARNING: The user space caller may invoke the initially mentioned - accept system call multiple times. In this case, the returned file - descriptors have the same state. - - - - - Zero-Copy Interface - - In addition to the send/write/read/recv system call family, the AF_ALG - interface can be accessed with the zero-copy interface of splice/vmsplice. - As the name indicates, the kernel tries to avoid a copy operation into - kernel space. - - - - The zero-copy operation requires data to be aligned at the page boundary. - Non-aligned data can be used as well, but may require more operations of - the kernel which would defeat the speed gains obtained from the zero-copy - interface. - - - - The system-interent limit for the size of one zero-copy operation is - 16 pages. If more data is to be sent to AF_ALG, user space must slice - the input into segments with a maximum size of 16 pages. - - - - Zero-copy can be used with the following code example (a complete working - example is provided with libkcapi): - - - -int pipes[2]; - -pipe(pipes); -/* input data in iov */ -vmsplice(pipes[1], iov, iovlen, SPLICE_F_GIFT); -/* opfd is the file descriptor returned from accept() system call */ -splice(pipes[0], NULL, opfd, NULL, ret, 0); -read(opfd, out, outlen); - - - - - Setsockopt Interface - - In addition to the read/recv and send/write system call handling - to send and retrieve data subject to the cipher operation, a consumer - also needs to set the additional information for the cipher operation. - This additional information is set using the setsockopt system call - that must be invoked with the file descriptor of the open cipher - (i.e. the file descriptor returned by the accept system call). - - - - Each setsockopt invocation must use the level SOL_ALG. - - - - The setsockopt interface allows setting the following data using - the mentioned optname: - - - - - - ALG_SET_KEY -- Setting the key. Key setting is applicable to: - - - - the skcipher cipher type (symmetric ciphers) - - - the hash cipher type (keyed message digests) - - - the AEAD cipher type - - - the RNG cipher type to provide the seed - - - - - - - ALG_SET_AEAD_AUTHSIZE -- Setting the authentication tag size - for AEAD ciphers. For a encryption operation, the authentication - tag of the given size will be generated. For a decryption operation, - the provided ciphertext is assumed to contain an authentication tag - of the given size (see section about AEAD memory layout below). - - - - - - - User space API example - - Please see [1] for libkcapi which provides an easy-to-use wrapper - around the aforementioned Netlink kernel interface. [1] also contains - a test application that invokes all libkcapi API calls. - - - - [1] http://www.chronox.de/libkcapi.html - - - - - - - Programming Interface - - Please note that the kernel crypto API contains the AEAD givcrypt - API (crypto_aead_giv* and aead_givcrypt_* function calls in - include/crypto/aead.h). This API is obsolete and will be removed - in the future. To obtain the functionality of an AEAD cipher with - internal IV generation, use the IV generator as a regular cipher. - For example, rfc4106(gcm(aes)) is the AEAD cipher with external - IV generation and seqniv(rfc4106(gcm(aes))) implies that the kernel - crypto API generates the IV. Different IV generators are available. - - Block Cipher Context Data Structures -!Pinclude/linux/crypto.h Block Cipher Context Data Structures -!Finclude/crypto/aead.h aead_request - - Block Cipher Algorithm Definitions -!Pinclude/linux/crypto.h Block Cipher Algorithm Definitions -!Finclude/linux/crypto.h crypto_alg -!Finclude/linux/crypto.h ablkcipher_alg -!Finclude/crypto/aead.h aead_alg -!Finclude/linux/crypto.h blkcipher_alg -!Finclude/linux/crypto.h cipher_alg -!Finclude/crypto/rng.h rng_alg - - Symmetric Key Cipher API -!Pinclude/crypto/skcipher.h Symmetric Key Cipher API -!Finclude/crypto/skcipher.h crypto_alloc_skcipher -!Finclude/crypto/skcipher.h crypto_free_skcipher -!Finclude/crypto/skcipher.h crypto_has_skcipher -!Finclude/crypto/skcipher.h crypto_skcipher_ivsize -!Finclude/crypto/skcipher.h crypto_skcipher_blocksize -!Finclude/crypto/skcipher.h crypto_skcipher_setkey -!Finclude/crypto/skcipher.h crypto_skcipher_reqtfm -!Finclude/crypto/skcipher.h crypto_skcipher_encrypt -!Finclude/crypto/skcipher.h crypto_skcipher_decrypt - - Symmetric Key Cipher Request Handle -!Pinclude/crypto/skcipher.h Symmetric Key Cipher Request Handle -!Finclude/crypto/skcipher.h crypto_skcipher_reqsize -!Finclude/crypto/skcipher.h skcipher_request_set_tfm -!Finclude/crypto/skcipher.h skcipher_request_alloc -!Finclude/crypto/skcipher.h skcipher_request_free -!Finclude/crypto/skcipher.h skcipher_request_set_callback -!Finclude/crypto/skcipher.h skcipher_request_set_crypt - - Asynchronous Block Cipher API - Deprecated -!Pinclude/linux/crypto.h Asynchronous Block Cipher API -!Finclude/linux/crypto.h crypto_alloc_ablkcipher -!Finclude/linux/crypto.h crypto_free_ablkcipher -!Finclude/linux/crypto.h crypto_has_ablkcipher -!Finclude/linux/crypto.h crypto_ablkcipher_ivsize -!Finclude/linux/crypto.h crypto_ablkcipher_blocksize -!Finclude/linux/crypto.h crypto_ablkcipher_setkey -!Finclude/linux/crypto.h crypto_ablkcipher_reqtfm -!Finclude/linux/crypto.h crypto_ablkcipher_encrypt -!Finclude/linux/crypto.h crypto_ablkcipher_decrypt - - Asynchronous Cipher Request Handle - Deprecated -!Pinclude/linux/crypto.h Asynchronous Cipher Request Handle -!Finclude/linux/crypto.h crypto_ablkcipher_reqsize -!Finclude/linux/crypto.h ablkcipher_request_set_tfm -!Finclude/linux/crypto.h ablkcipher_request_alloc -!Finclude/linux/crypto.h ablkcipher_request_free -!Finclude/linux/crypto.h ablkcipher_request_set_callback -!Finclude/linux/crypto.h ablkcipher_request_set_crypt - - Authenticated Encryption With Associated Data (AEAD) Cipher API -!Pinclude/crypto/aead.h Authenticated Encryption With Associated Data (AEAD) Cipher API -!Finclude/crypto/aead.h crypto_alloc_aead -!Finclude/crypto/aead.h crypto_free_aead -!Finclude/crypto/aead.h crypto_aead_ivsize -!Finclude/crypto/aead.h crypto_aead_authsize -!Finclude/crypto/aead.h crypto_aead_blocksize -!Finclude/crypto/aead.h crypto_aead_setkey -!Finclude/crypto/aead.h crypto_aead_setauthsize -!Finclude/crypto/aead.h crypto_aead_encrypt -!Finclude/crypto/aead.h crypto_aead_decrypt - - Asynchronous AEAD Request Handle -!Pinclude/crypto/aead.h Asynchronous AEAD Request Handle -!Finclude/crypto/aead.h crypto_aead_reqsize -!Finclude/crypto/aead.h aead_request_set_tfm -!Finclude/crypto/aead.h aead_request_alloc -!Finclude/crypto/aead.h aead_request_free -!Finclude/crypto/aead.h aead_request_set_callback -!Finclude/crypto/aead.h aead_request_set_crypt -!Finclude/crypto/aead.h aead_request_set_ad - - Synchronous Block Cipher API - Deprecated -!Pinclude/linux/crypto.h Synchronous Block Cipher API -!Finclude/linux/crypto.h crypto_alloc_blkcipher -!Finclude/linux/crypto.h crypto_free_blkcipher -!Finclude/linux/crypto.h crypto_has_blkcipher -!Finclude/linux/crypto.h crypto_blkcipher_name -!Finclude/linux/crypto.h crypto_blkcipher_ivsize -!Finclude/linux/crypto.h crypto_blkcipher_blocksize -!Finclude/linux/crypto.h crypto_blkcipher_setkey -!Finclude/linux/crypto.h crypto_blkcipher_encrypt -!Finclude/linux/crypto.h crypto_blkcipher_encrypt_iv -!Finclude/linux/crypto.h crypto_blkcipher_decrypt -!Finclude/linux/crypto.h crypto_blkcipher_decrypt_iv -!Finclude/linux/crypto.h crypto_blkcipher_set_iv -!Finclude/linux/crypto.h crypto_blkcipher_get_iv - - Single Block Cipher API -!Pinclude/linux/crypto.h Single Block Cipher API -!Finclude/linux/crypto.h crypto_alloc_cipher -!Finclude/linux/crypto.h crypto_free_cipher -!Finclude/linux/crypto.h crypto_has_cipher -!Finclude/linux/crypto.h crypto_cipher_blocksize -!Finclude/linux/crypto.h crypto_cipher_setkey -!Finclude/linux/crypto.h crypto_cipher_encrypt_one -!Finclude/linux/crypto.h crypto_cipher_decrypt_one - - Message Digest Algorithm Definitions -!Pinclude/crypto/hash.h Message Digest Algorithm Definitions -!Finclude/crypto/hash.h hash_alg_common -!Finclude/crypto/hash.h ahash_alg -!Finclude/crypto/hash.h shash_alg - - Asynchronous Message Digest API -!Pinclude/crypto/hash.h Asynchronous Message Digest API -!Finclude/crypto/hash.h crypto_alloc_ahash -!Finclude/crypto/hash.h crypto_free_ahash -!Finclude/crypto/hash.h crypto_ahash_init -!Finclude/crypto/hash.h crypto_ahash_digestsize -!Finclude/crypto/hash.h crypto_ahash_reqtfm -!Finclude/crypto/hash.h crypto_ahash_reqsize -!Finclude/crypto/hash.h crypto_ahash_setkey -!Finclude/crypto/hash.h crypto_ahash_finup -!Finclude/crypto/hash.h crypto_ahash_final -!Finclude/crypto/hash.h crypto_ahash_digest -!Finclude/crypto/hash.h crypto_ahash_export -!Finclude/crypto/hash.h crypto_ahash_import - - Asynchronous Hash Request Handle -!Pinclude/crypto/hash.h Asynchronous Hash Request Handle -!Finclude/crypto/hash.h ahash_request_set_tfm -!Finclude/crypto/hash.h ahash_request_alloc -!Finclude/crypto/hash.h ahash_request_free -!Finclude/crypto/hash.h ahash_request_set_callback -!Finclude/crypto/hash.h ahash_request_set_crypt - - Synchronous Message Digest API -!Pinclude/crypto/hash.h Synchronous Message Digest API -!Finclude/crypto/hash.h crypto_alloc_shash -!Finclude/crypto/hash.h crypto_free_shash -!Finclude/crypto/hash.h crypto_shash_blocksize -!Finclude/crypto/hash.h crypto_shash_digestsize -!Finclude/crypto/hash.h crypto_shash_descsize -!Finclude/crypto/hash.h crypto_shash_setkey -!Finclude/crypto/hash.h crypto_shash_digest -!Finclude/crypto/hash.h crypto_shash_export -!Finclude/crypto/hash.h crypto_shash_import -!Finclude/crypto/hash.h crypto_shash_init -!Finclude/crypto/hash.h crypto_shash_update -!Finclude/crypto/hash.h crypto_shash_final -!Finclude/crypto/hash.h crypto_shash_finup - - Crypto API Random Number API -!Pinclude/crypto/rng.h Random number generator API -!Finclude/crypto/rng.h crypto_alloc_rng -!Finclude/crypto/rng.h crypto_rng_alg -!Finclude/crypto/rng.h crypto_free_rng -!Finclude/crypto/rng.h crypto_rng_generate -!Finclude/crypto/rng.h crypto_rng_get_bytes -!Finclude/crypto/rng.h crypto_rng_reset -!Finclude/crypto/rng.h crypto_rng_seedsize -!Cinclude/crypto/rng.h - - Asymmetric Cipher API -!Pinclude/crypto/akcipher.h Generic Public Key API -!Finclude/crypto/akcipher.h akcipher_alg -!Finclude/crypto/akcipher.h akcipher_request -!Finclude/crypto/akcipher.h crypto_alloc_akcipher -!Finclude/crypto/akcipher.h crypto_free_akcipher -!Finclude/crypto/akcipher.h crypto_akcipher_set_pub_key -!Finclude/crypto/akcipher.h crypto_akcipher_set_priv_key - - Asymmetric Cipher Request Handle -!Finclude/crypto/akcipher.h akcipher_request_alloc -!Finclude/crypto/akcipher.h akcipher_request_free -!Finclude/crypto/akcipher.h akcipher_request_set_callback -!Finclude/crypto/akcipher.h akcipher_request_set_crypt -!Finclude/crypto/akcipher.h crypto_akcipher_maxsize -!Finclude/crypto/akcipher.h crypto_akcipher_encrypt -!Finclude/crypto/akcipher.h crypto_akcipher_decrypt -!Finclude/crypto/akcipher.h crypto_akcipher_sign -!Finclude/crypto/akcipher.h crypto_akcipher_verify - - - - Code Examples - Code Example For Symmetric Key Cipher Operation - - -struct tcrypt_result { - struct completion completion; - int err; -}; - -/* tie all data structures together */ -struct skcipher_def { - struct scatterlist sg; - struct crypto_skcipher *tfm; - struct skcipher_request *req; - struct tcrypt_result result; -}; - -/* Callback function */ -static void test_skcipher_cb(struct crypto_async_request *req, int error) -{ - struct tcrypt_result *result = req->data; - - if (error == -EINPROGRESS) - return; - result->err = error; - complete(&result->completion); - pr_info("Encryption finished successfully\n"); -} - -/* Perform cipher operation */ -static unsigned int test_skcipher_encdec(struct skcipher_def *sk, - int enc) -{ - int rc = 0; - - if (enc) - rc = crypto_skcipher_encrypt(sk->req); - else - rc = crypto_skcipher_decrypt(sk->req); - - switch (rc) { - case 0: - break; - case -EINPROGRESS: - case -EBUSY: - rc = wait_for_completion_interruptible( - &sk->result.completion); - if (!rc && !sk->result.err) { - reinit_completion(&sk->result.completion); - break; - } - default: - pr_info("skcipher encrypt returned with %d result %d\n", - rc, sk->result.err); - break; - } - init_completion(&sk->result.completion); - - return rc; -} - -/* Initialize and trigger cipher operation */ -static int test_skcipher(void) -{ - struct skcipher_def sk; - struct crypto_skcipher *skcipher = NULL; - struct skcipher_request *req = NULL; - char *scratchpad = NULL; - char *ivdata = NULL; - unsigned char key[32]; - int ret = -EFAULT; - - skcipher = crypto_alloc_skcipher("cbc-aes-aesni", 0, 0); - if (IS_ERR(skcipher)) { - pr_info("could not allocate skcipher handle\n"); - return PTR_ERR(skcipher); - } - - req = skcipher_request_alloc(skcipher, GFP_KERNEL); - if (!req) { - pr_info("could not allocate skcipher request\n"); - ret = -ENOMEM; - goto out; - } - - skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, - test_skcipher_cb, - &sk.result); - - /* AES 256 with random key */ - get_random_bytes(&key, 32); - if (crypto_skcipher_setkey(skcipher, key, 32)) { - pr_info("key could not be set\n"); - ret = -EAGAIN; - goto out; - } - - /* IV will be random */ - ivdata = kmalloc(16, GFP_KERNEL); - if (!ivdata) { - pr_info("could not allocate ivdata\n"); - goto out; - } - get_random_bytes(ivdata, 16); - - /* Input data will be random */ - scratchpad = kmalloc(16, GFP_KERNEL); - if (!scratchpad) { - pr_info("could not allocate scratchpad\n"); - goto out; - } - get_random_bytes(scratchpad, 16); - - sk.tfm = skcipher; - sk.req = req; - - /* We encrypt one block */ - sg_init_one(&sk.sg, scratchpad, 16); - skcipher_request_set_crypt(req, &sk.sg, &sk.sg, 16, ivdata); - init_completion(&sk.result.completion); - - /* encrypt data */ - ret = test_skcipher_encdec(&sk, 1); - if (ret) - goto out; - - pr_info("Encryption triggered successfully\n"); - -out: - if (skcipher) - crypto_free_skcipher(skcipher); - if (req) - skcipher_request_free(req); - if (ivdata) - kfree(ivdata); - if (scratchpad) - kfree(scratchpad); - return ret; -} - - - - Code Example For Use of Operational State Memory With SHASH - - -struct sdesc { - struct shash_desc shash; - char ctx[]; -}; - -static struct sdescinit_sdesc(struct crypto_shash *alg) -{ - struct sdescsdesc; - int size; - - size = sizeof(struct shash_desc) + crypto_shash_descsize(alg); - sdesc = kmalloc(size, GFP_KERNEL); - if (!sdesc) - return ERR_PTR(-ENOMEM); - sdesc->shash.tfm = alg; - sdesc->shash.flags = 0x0; - return sdesc; -} - -static int calc_hash(struct crypto_shashalg, - const unsigned chardata, unsigned int datalen, - unsigned chardigest) { - struct sdescsdesc; - int ret; - - sdesc = init_sdesc(alg); - if (IS_ERR(sdesc)) { - pr_info("trusted_key: can't alloc %s\n", hash_alg); - return PTR_ERR(sdesc); - } - - ret = crypto_shash_digest(&sdesc->shash, data, datalen, digest); - kfree(sdesc); - return ret; -} - - - - Code Example For Random Number Generator Usage - - -static int get_random_numbers(u8 *buf, unsigned int len) -{ - struct crypto_rngrng = NULL; - chardrbg = "drbg_nopr_sha256"; /* Hash DRBG with SHA-256, no PR */ - int ret; - - if (!buf || !len) { - pr_debug("No output buffer provided\n"); - return -EINVAL; - } - - rng = crypto_alloc_rng(drbg, 0, 0); - if (IS_ERR(rng)) { - pr_debug("could not allocate RNG handle for %s\n", drbg); - return -PTR_ERR(rng); - } - - ret = crypto_rng_get_bytes(rng, buf, len); - if (ret < 0) - pr_debug("generation of random numbers failed\n"); - else if (ret == 0) - pr_debug("RNG returned no data"); - else - pr_debug("RNG returned %d bytes of data\n", ret); - -out: - crypto_free_rng(rng); - return ret; -} - - - - diff --git a/Documentation/IPMI.txt b/Documentation/IPMI.txt index c0d8788e75d3..72292308d0f5 100644 --- a/Documentation/IPMI.txt +++ b/Documentation/IPMI.txt @@ -111,6 +111,8 @@ ipmi_ssif - A driver for accessing BMCs on the SMBus. It uses the I2C kernel driver's SMBus interfaces to send and receive IPMI messages over the SMBus. +ipmi_powernv - A driver for access BMCs on POWERNV systems. + ipmi_watchdog - IPMI requires systems to have a very capable watchdog timer. This driver implements the standard Linux watchdog timer interface on top of the IPMI message handler. @@ -118,17 +120,15 @@ interface on top of the IPMI message handler. ipmi_poweroff - Some systems support the ability to be turned off via IPMI commands. -These are all individually selectable via configuration options. +bt-bmc - This is not part of the main driver, but instead a driver for +accessing a BMC-side interface of a BT interface. It is used on BMCs +running Linux to provide an interface to the host. -Note that the KCS-only interface has been removed. The af_ipmi driver -is no longer supported and has been removed because it was impossible -to do 32 bit emulation on 64-bit kernels with it. +These are all individually selectable via configuration options. Much documentation for the interface is in the include files. The IPMI include files are: -net/af_ipmi.h - Contains the socket interface. - linux/ipmi.h - Contains the user interface and IOCTL interface for IPMI. linux/ipmi_smi.h - Contains the interface for system management interfaces @@ -245,6 +245,16 @@ addressed (because some boards actually have multiple BMCs on them) and the user should not have to care what type of SMI is below them. +Watching For Interfaces + +When your code comes up, the IPMI driver may or may not have detected +if IPMI devices exist. So you might have to defer your setup until +the device is detected, or you might be able to do it immediately. +To handle this, and to allow for discovery, you register an SMI +watcher with ipmi_smi_watcher_register() to iterate over interfaces +and tell you when they come and go. + + Creating the User To user the message handler, you must first create a user using @@ -263,7 +273,7 @@ closing the device automatically destroys the user. Messaging -To send a message from kernel-land, the ipmi_request() call does +To send a message from kernel-land, the ipmi_request_settime() call does pretty much all message handling. Most of the parameter are self-explanatory. However, it takes a "msgid" parameter. This is NOT the sequence number of messages. It is simply a long value that is @@ -352,11 +362,12 @@ that for more details. The SI Driver ------------- -The SI driver allows up to 4 KCS or SMIC interfaces to be configured -in the system. By default, scan the ACPI tables for interfaces, and -if it doesn't find any the driver will attempt to register one KCS -interface at the spec-specified I/O port 0xca2 without interrupts. -You can change this at module load time (for a module) with: +The SI driver allows KCS, BT, and SMIC interfaces to be configured +in the system. It discovers interfaces through a host of different +methods, depending on the system. + +You can specify up to four interfaces on the module load line and +control some module parameters: modprobe ipmi_si.o type=,.... ports=,... addrs=,... @@ -367,7 +378,7 @@ You can change this at module load time (for a module) with: force_kipmid=,,... kipmid_max_busy_us=,,... unload_when_empty=[0|1] - trydefaults=[0|1] trydmi=[0|1] tryacpi=[0|1] + trydmi=[0|1] tryacpi=[0|1] tryplatform=[0|1] trypci=[0|1] Each of these except try... items is a list, the first item for the @@ -386,10 +397,6 @@ use the I/O port given as the device address. If you specify irqs as non-zero for an interface, the driver will attempt to use the given interrupt for the device. -trydefaults sets whether the standard IPMI interface at 0xca2 and -any interfaces specified by ACPE are tried. By default, the driver -tries it, set this value to zero to turn this off. - The other try... items disable discovery by their corresponding names. These are all enabled by default, set them to zero to disable them. The tryplatform disables openfirmware. @@ -434,7 +441,7 @@ kernel command line as: ipmi_si.type=,... ipmi_si.ports=,... ipmi_si.addrs=,... - ipmi_si.irqs=,... ipmi_si.trydefaults=[0|1] + ipmi_si.irqs=,... ipmi_si.regspacings=,,... ipmi_si.regsizes=,,... ipmi_si.regshifts=,,... @@ -444,11 +451,6 @@ kernel command line as: It works the same as the module parameters of the same names. -By default, the driver will attempt to detect any device specified by -ACPI, and if none of those then a KCS device at the spec-specified -0xca2. If you want to turn this off, set the "trydefaults" option to -false. - If your IPMI interface does not support interrupts and is a KCS or SMIC interface, the IPMI driver will start a kernel thread for the interface to help speed things up. This is a low-priority kernel @@ -500,7 +502,8 @@ at module load time (for a module) with: addr=[,[,...]] adapter=[,[...]] dbg=,... - slave_addrs=,,... + slave_addrs=,,... + tryacpi=[0|1] trydmi=[0|1] [dbg_probe=1] The addresses are normal I2C addresses. The adapter is the string @@ -513,6 +516,9 @@ spaces in kernel parameters. The debug flags are bit flags for each BMC found, they are: IPMI messages: 1, driver state: 2, timing: 4, I2C probe: 8 +The tryxxx parameters can be used to disable detecting interfaces +from various sources. + Setting dbg_probe to 1 will enable debugging of the probing and detection process for BMCs on the SMBusses. @@ -535,7 +541,8 @@ kernel command line as: ipmi_ssif.adapter=[,[...]] ipmi_ssif.dbg=[,[...]] ipmi_ssif.dbg_probe=1 - ipmi_ssif.slave_addrs=[,[...]] + ipmi_ssif.slave_addrs=[,[...]] + ipmi_ssif.tryacpi=[0|1] ipmi_ssif.trydmi=[0|1] These are the same options as on the module command line. diff --git a/Documentation/admin-guide/index.rst b/Documentation/admin-guide/index.rst index 2681cbd24cdd..8ddae4e4299a 100644 --- a/Documentation/admin-guide/index.rst +++ b/Documentation/admin-guide/index.rst @@ -59,6 +59,7 @@ configure specific aspects of kernel behavior to your liking. binfmt-misc mono java + ras .. only:: subproject and html diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index be2d6d0a03a4..be7c0d9506b1 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -106,6 +106,16 @@ use by PCI Format: ,... + acpi_mask_gpe= [HW,ACPI] + Due to the existence of _Lxx/_Exx, some GPEs triggered + by unsupported hardware/firmware features can result in + GPE floodings that cannot be automatically disabled by + the GPE dispatcher. + This facility can be used to prevent such uncontrolled + GPE floodings. + Format: + Support masking of GPEs numbered from 0x00 to 0x7f. + acpi_no_auto_serialize [HW,ACPI] Disable auto-serialization of AML methods AML control methods that contain the opcodes to create @@ -1441,6 +1451,10 @@ The builtin appraise policy appraises all files owned by uid=0. + ima_canonical_fmt [IMA] + Use the canonical format for the binary runtime + measurements, instead of host native format. + ima_hash= [IMA] Format: { md5 | sha1 | rmd160 | sha256 | sha384 | sha512 | ... } @@ -3807,10 +3821,11 @@ it if 0 is given (See Documentation/cgroup-v1/memory.txt) swiotlb= [ARM,IA-64,PPC,MIPS,X86] - Format: { | force } + Format: { | force | noforce } -- Number of I/O TLB slabs force -- force using of bounce buffers even if they wouldn't be automatically used by the kernel + noforce -- Never use bounce buffers (for debugging) switches= [HW,M68k] diff --git a/Documentation/admin-guide/ras.rst b/Documentation/admin-guide/ras.rst new file mode 100644 index 000000000000..d71340e86c27 --- /dev/null +++ b/Documentation/admin-guide/ras.rst @@ -0,0 +1,1190 @@ +.. include:: + +============================================ +Reliability, Availability and Serviceability +============================================ + +RAS concepts +************ + +Reliability, Availability and Serviceability (RAS) is a concept used on +servers meant to measure their robusteness. + +Reliability + is the probability that a system will produce correct outputs. + + * Generally measured as Mean Time Between Failures (MTBF) + * Enhanced by features that help to avoid, detect and repair hardware faults + +Availability + is the probability that a system is operational at a given time + + * Generally measured as a percentage of downtime per a period of time + * Often uses mechanisms to detect and correct hardware faults in + runtime; + +Serviceability (or maintainability) + is the simplicity and speed with which a system can be repaired or + maintained + + * Generally measured on Mean Time Between Repair (MTBR) + +Improving RAS +------------- + +In order to reduce systems downtime, a system should be capable of detecting +hardware errors, and, when possible correcting them in runtime. It should +also provide mechanisms to detect hardware degradation, in order to warn +the system administrator to take the action of replacing a component before +it causes data loss or system downtime. + +Among the monitoring measures, the most usual ones include: + +* CPU – detect errors at instruction execution and at L1/L2/L3 caches; +* Memory – add error correction logic (ECC) to detect and correct errors; +* I/O – add CRC checksums for tranfered data; +* Storage – RAID, journal file systems, checksums, + Self-Monitoring, Analysis and Reporting Technology (SMART). + +By monitoring the number of occurrences of error detections, it is possible +to identify if the probability of hardware errors is increasing, and, on such +case, do a preventive maintainance to replace a degrated component while +those errors are correctable. + +Types of errors +--------------- + +Most mechanisms used on modern systems use use technologies like Hamming +Codes that allow error correction when the number of errors on a bit packet +is below a threshold. If the number of errors is above, those mechanisms +can indicate with a high degree of confidence that an error happened, but +they can't correct. + +Also, sometimes an error occur on a component that it is not used. For +example, a part of the memory that it is not currently allocated. + +That defines some categories of errors: + +* **Correctable Error (CE)** - the error detection mechanism detected and + corrected the error. Such errors are usually not fatal, although some + Kernel mechanisms allow the system administrator to consider them as fatal. + +* **Uncorrected Error (UE)** - the amount of errors happened above the error + correction threshold, and the system was unable to auto-correct. + +* **Fatal Error** - when an UE error happens on a critical component of the + system (for example, a piece of the Kernel got corrupted by an UE), the + only reliable way to avoid data corruption is to hang or reboot the machine. + +* **Non-fatal Error** - when an UE error happens on an unused component, + like a CPU in power down state or an unused memory bank, the system may + still run, eventually replacing the affected hardware by a hot spare, + if available. + + Also, when an error happens on an userspace process, it is also possible to + kill such process and let userspace restart it. + +The mechanism for handling non-fatal errors is usually complex and may +require the help of some userspace application, in order to apply the +policy desired by the system administrator. + +Identifying a bad hardware component +------------------------------------ + +Just detecting a hardware flaw is usually not enough, as the system needs +to pinpoint to the minimal replaceable unit (MRU) that should be exchanged +to make the hardware reliable again. + +So, it requires not only error logging facilities, but also mechanisms that +will translate the error message to the silkscreen or component label for +the MRU. + +Typically, it is very complex for memory, as modern CPUs interlace memory +from different memory modules, in order to provide a better performance. The +DMI BIOS usually have a list of memory module labels, with can be obtained +using the ``dmidecode`` tool. For example, on a desktop machine, it shows:: + + Memory Device + Total Width: 64 bits + Data Width: 64 bits + Size: 16384 MB + Form Factor: SODIMM + Set: None + Locator: ChannelA-DIMM0 + Bank Locator: BANK 0 + Type: DDR4 + Type Detail: Synchronous + Speed: 2133 MHz + Rank: 2 + Configured Clock Speed: 2133 MHz + +On the above example, a DDR4 SO-DIMM memory module is located at the +system's memory labeled as "BANK 0", as given by the *bank locator* field. +Please notice that, on such system, the *total width* is equal to the +*data witdh*. It means that such memory module doesn't have error +detection/correction mechanisms. + +Unfortunately, not all systems use the same field to specify the memory +bank. On this example, from an older server, ``dmidecode`` shows:: + + Memory Device + Array Handle: 0x1000 + Error Information Handle: Not Provided + Total Width: 72 bits + Data Width: 64 bits + Size: 8192 MB + Form Factor: DIMM + Set: 1 + Locator: DIMM_A1 + Bank Locator: Not Specified + Type: DDR3 + Type Detail: Synchronous Registered (Buffered) + Speed: 1600 MHz + Rank: 2 + Configured Clock Speed: 1600 MHz + +There, the DDR3 RDIMM memory module is located at the system's memory labeled +as "DIMM_A1", as given by the *locator* field. Please notice that this +memory module has 64 bits of *data witdh* and 72 bits of *total width*. So, +it has 8 extra bits to be used by error detection and correction mechanisms. +Such kind of memory is called Error-correcting code memory (ECC memory). + +To make things even worse, it is not uncommon that systems with different +labels on their system's board to use exactly the same BIOS, meaning that +the labels provided by the BIOS won't match the real ones. + +ECC memory +---------- + +As mentioned on the previous section, ECC memory has extra bits to be +used for error correction. So, on 64 bit systems, a memory module +has 64 bits of *data width*, and 74 bits of *total width*. So, there are +8 bits extra bits to be used for the error detection and correction +mechanisms. Those extra bits are called *syndrome*\ [#f1]_\ [#f2]_. + +So, when the cpu requests the memory controller to write a word with +*data width*, the memory controller calculates the *syndrome* in real time, +using Hamming code, or some other error correction code, like SECDED+, +producing a code with *total width* size. Such code is then written +on the memory modules. + +At read, the *total width* bits code is converted back, using the same +ECC code used on write, producing a word with *data width* and a *syndrome*. +The word with *data width* is sent to the CPU, even when errors happen. + +The memory controller also looks at the *syndrome* in order to check if +there was an error, and if the ECC code was able to fix such error. +If the error was corrected, a Corrected Error (CE) happened. If not, an +Uncorrected Error (UE) happened. + +The information about the CE/UE errors is stored on some special registers +at the memory controller and can be accessed by reading such registers, +either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64 +bit CPUs, such errors can also be retrieved via the Machine Check +Architecture (MCA)\ [#f3]_. + +.. [#f1] Please notice that several memory controllers allow operation on a + mode called "Lock-Step", where it groups two memory modules together, + doing 128-bit reads/writes. That gives 16 bits for error correction, with + significatively improves the error correction mechanism, at the expense + that, when an error happens, there's no way to know what memory module is + to blame. So, it has to blame both memory modules. + +.. [#f2] Some memory controllers also allow using memory in mirror mode. + On such mode, the same data is written to two memory modules. At read, + the system checks both memory modules, in order to check if both provide + identical data. On such configuration, when an error happens, there's no + way to know what memory module is to blame. So, it has to blame both + memory modules (or 4 memory modules, if the system is also on Lock-step + mode). + +.. [#f3] For more details about the Machine Check Architecture (MCA), + please read Documentation/x86/x86_64/machinecheck at the Kernel tree. + +EDAC - Error Detection And Correction +************************************* + +.. note:: + + "bluesmoke" was the name for this device driver subsystem when it + was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net. + That site is mostly archaic now and can be used only for historical + purposes. + + When the subsystem was pushed upstream for the first time, on + Kernel 2.6.16, for the first time, it was renamed to ``EDAC``. + +Purpose +------- + +The ``edac`` kernel module's goal is to detect and report hardware errors +that occur within the computer system running under linux. + +Memory +------ + +Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the +primary errors being harvested. These types of errors are harvested by +the ``edac_mc`` device. + +Detecting CE events, then harvesting those events and reporting them, +**can** but must not necessarily be a predictor of future UE events. With +CE events only, the system can and will continue to operate as no data +has been damaged yet. + +However, preventive maintenance and proactive part replacement of memory +modules exhibiting CEs can reduce the likelihood of the dreaded UE events +and system panics. + +Other hardware elements +----------------------- + +A new feature for EDAC, the ``edac_device`` class of device, was added in +the 2.6.23 version of the kernel. + +This new device type allows for non-memory type of ECC hardware detectors +to have their states harvested and presented to userspace via the sysfs +interface. + +Some architectures have ECC detectors for L1, L2 and L3 caches, +along with DMA engines, fabric switches, main data path switches, +interconnections, and various other hardware data paths. If the hardware +reports it, then a edac_device device probably can be constructed to +harvest and present that to userspace. + + +PCI bus scanning +---------------- + +In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors +in order to determine if errors are occurring during data transfers. + +The presence of PCI Parity errors must be examined with a grain of salt. +There are several add-in adapters that do **not** follow the PCI specification +with regards to Parity generation and reporting. The specification says +the vendor should tie the parity status bits to 0 if they do not intend +to generate parity. Some vendors do not do this, and thus the parity bit +can "float" giving false positives. + +There is a PCI device attribute located in sysfs that is checked by +the EDAC PCI scanning code. If that attribute is set, PCI parity/error +scanning is skipped for that device. The attribute is:: + + broken_parity_status + +and is located in ``/sys/devices/pci/0000:XX:YY.Z`` directories for +PCI devices. + + +Versioning +---------- + +EDAC is composed of a "core" module (``edac_core.ko``) and several Memory +Controller (MC) driver modules. On a given system, the CORE is loaded +and one MC driver will be loaded. Both the CORE and the MC driver (or +``edac_device`` driver) have individual versions that reflect current +release level of their respective modules. + +Thus, to "report" on what version a system is running, one must report +both the CORE's and the MC driver's versions. + + +Loading +------- + +If ``edac`` was statically linked with the kernel then no loading +is necessary. If ``edac`` was built as modules then simply modprobe +the ``edac`` pieces that you need. You should be able to modprobe +hardware-specific modules and have the dependencies load the necessary +core modules. + +Example:: + + $ modprobe amd76x_edac + +loads both the ``amd76x_edac.ko`` memory controller module and the +``edac_mc.ko`` core module. + + +Sysfs interface +--------------- + +EDAC presents a ``sysfs`` interface for control and reporting purposes. It +lives in the /sys/devices/system/edac directory. + +Within this directory there currently reside 2 components: + + ======= ============================== + mc memory controller(s) system + pci PCI control and status system + ======= ============================== + + + +Memory Controller (mc) Model +---------------------------- + +Each ``mc`` device controls a set of memory modules [#f4]_. These modules +are laid out in a Chip-Select Row (``csrowX``) and Channel table (``chX``). +There can be multiple csrows and multiple channels. + +.. [#f4] Nowadays, the term DIMM (Dual In-line Memory Module) is widely + used to refer to a memory module, although there are other memory + packaging alternatives, like SO-DIMM, SIMM, etc. Along this document, + and inside the EDAC system, the term "dimm" is used for all memory + modules, even when they use a different kind of packaging. + +Memory controllers allow for several csrows, with 8 csrows being a +typical value. Yet, the actual number of csrows depends on the layout of +a given motherboard, memory controller and memory module characteristics. + +Dual channels allow for dual data length (e. g. 128 bits, on 64 bit systems) +data transfers to/from the CPU from/to memory. Some newer chipsets allow +for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory +controllers. The following example will assume 2 channels: + + +------------+-----------------------+ + | Chip | Channels | + | Select +-----------+-----------+ + | rows | ``ch0`` | ``ch1`` | + +============+===========+===========+ + | ``csrow0`` | DIMM_A0 | DIMM_B0 | + +------------+ | | + | ``csrow1`` | | | + +------------+-----------+-----------+ + | ``csrow2`` | DIMM_A1 | DIMM_B1 | + +------------+ | | + | ``csrow3`` | | | + +------------+-----------+-----------+ + +In the above example, there are 4 physical slots on the motherboard +for memory DIMMs: + + +---------+---------+ + | DIMM_A0 | DIMM_B0 | + +---------+---------+ + | DIMM_A1 | DIMM_B1 | + +---------+---------+ + +Labels for these slots are usually silk-screened on the motherboard. +Slots labeled ``A`` are channel 0 in this example. Slots labeled ``B`` are +channel 1. Notice that there are two csrows possible on a physical DIMM. +These csrows are allocated their csrow assignment based on the slot into +which the memory DIMM is placed. Thus, when 1 DIMM is placed in each +Channel, the csrows cross both DIMMs. + +Memory DIMMs come single or dual "ranked". A rank is a populated csrow. +Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above +will have just one csrow (csrow0). csrow1 will be empty. On the other +hand, when 2 dual ranked DIMMs are similarly placed, then both csrow0 +and csrow1 will be populated. The pattern repeats itself for csrow2 and +csrow3. + +The representation of the above is reflected in the directory +tree in EDAC's sysfs interface. Starting in directory +``/sys/devices/system/edac/mc``, each memory controller will be +represented by its own ``mcX`` directory, where ``X`` is the +index of the MC:: + + ..../edac/mc/ + | + |->mc0 + |->mc1 + |->mc2 + .... + +Under each ``mcX`` directory each ``csrowX`` is again represented by a +``csrowX``, where ``X`` is the csrow index:: + + .../mc/mc0/ + | + |->csrow0 + |->csrow2 + |->csrow3 + .... + +Notice that there is no csrow1, which indicates that csrow0 is composed +of a single ranked DIMMs. This should also apply in both Channels, in +order to have dual-channel mode be operational. Since both csrow2 and +csrow3 are populated, this indicates a dual ranked set of DIMMs for +channels 0 and 1. + +Within each of the ``mcX`` and ``csrowX`` directories are several EDAC +control and attribute files. + +``mcX`` directories +------------------- + +In ``mcX`` directories are EDAC control and attribute files for +this ``X`` instance of the memory controllers. + +For a description of the sysfs API, please see: + + Documentation/ABI/testing/sysfs-devices-edac + + +``dimmX`` or ``rankX`` directories +---------------------------------- + +The recommended way to use the EDAC subsystem is to look at the information +provided by the ``dimmX`` or ``rankX`` directories [#f5]_. + +A typical EDAC system has the following structure under +``/sys/devices/system/edac/``\ [#f6]_:: + + /sys/devices/system/edac/ + ├── mc + │   ├── mc0 + │   │   ├── ce_count + │   │   ├── ce_noinfo_count + │   │   ├── dimm0 + │   │   │   ├── dimm_dev_type + │   │   │   ├── dimm_edac_mode + │   │   │   ├── dimm_label + │   │   │   ├── dimm_location + │   │   │   ├── dimm_mem_type + │   │   │   ├── size + │   │   │   └── uevent + │   │   ├── max_location + │   │   ├── mc_name + │   │   ├── reset_counters + │   │   ├── seconds_since_reset + │   │   ├── size_mb + │   │   ├── ue_count + │   │   ├── ue_noinfo_count + │   │   └── uevent + │   ├── mc1 + │   │   ├── ce_count + │   │   ├── ce_noinfo_count + │   │   ├── dimm0 + │   │   │   ├── dimm_dev_type + │   │   │   ├── dimm_edac_mode + │   │   │   ├── dimm_label + │   │   │   ├── dimm_location + │   │   │   ├── dimm_mem_type + │   │   │   ├── size + │   │   │   └── uevent + │   │   ├── max_location + │   │   ├── mc_name + │   │   ├── reset_counters + │   │   ├── seconds_since_reset + │   │   ├── size_mb + │   │   ├── ue_count + │   │   ├── ue_noinfo_count + │   │   └── uevent + │   └── uevent + └── uevent + +In the ``dimmX`` directories are EDAC control and attribute files for +this ``X`` memory module: + +- ``size`` - Total memory managed by this csrow attribute file + + This attribute file displays, in count of megabytes, the memory + that this csrow contains. + +- ``dimm_dev_type`` - Device type attribute file + + This attribute file will display what type of DRAM device is + being utilized on this DIMM. + Examples: + + - x1 + - x2 + - x4 + - x8 + +- ``dimm_edac_mode`` - EDAC Mode of operation attribute file + + This attribute file will display what type of Error detection + and correction is being utilized. + +- ``dimm_label`` - memory module label control file + + This control file allows this DIMM to have a label assigned + to it. With this label in the module, when errors occur + the output can provide the DIMM label in the system log. + This becomes vital for panic events to isolate the + cause of the UE event. + + DIMM Labels must be assigned after booting, with information + that correctly identifies the physical slot with its + silk screen label. This information is currently very + motherboard specific and determination of this information + must occur in userland at this time. + +- ``dimm_location`` - location of the memory module + + The location can have up to 3 levels, and describe how the + memory controller identifies the location of a memory module. + Depending on the type of memory and memory controller, it + can be: + + - *csrow* and *channel* - used when the memory controller + doesn't identify a single DIMM - e. g. in ``rankX`` dir; + - *branch*, *channel*, *slot* - typically used on FB-DIMM memory + controllers; + - *channel*, *slot* - used on Nehalem and newer Intel drivers. + +- ``dimm_mem_type`` - Memory Type attribute file + + This attribute file will display what type of memory is currently + on this csrow. Normally, either buffered or unbuffered memory. + Examples: + + - Registered-DDR + - Unbuffered-DDR + +.. [#f5] On some systems, the memory controller doesn't have any logic + to identify the memory module. On such systems, the directory is called ``rankX`` and works on a similar way as the ``csrowX`` directories. + On modern Intel memory controllers, the memory controller identifies the + memory modules directly. On such systems, the directory is called ``dimmX``. + +.. [#f6] There are also some ``power`` directories and ``subsystem`` + symlinks inside the sysfs mapping that are automatically created by + the sysfs subsystem. Currently, they serve no purpose. + +``csrowX`` directories +---------------------- + +When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the ``csrowX`` +directories. As this API doesn't work properly for Rambus, FB-DIMMs and +modern Intel Memory Controllers, this is being deprecated in favor of +``dimmX`` directories. + +In the ``csrowX`` directories are EDAC control and attribute files for +this ``X`` instance of csrow: + + +- ``ue_count`` - Total Uncorrectable Errors count attribute file + + This attribute file displays the total count of uncorrectable + errors that have occurred on this csrow. If panic_on_ue is set + this counter will not have a chance to increment, since EDAC + will panic the system. + + +- ``ce_count`` - Total Correctable Errors count attribute file + + This attribute file displays the total count of correctable + errors that have occurred on this csrow. This count is very + important to examine. CEs provide early indications that a + DIMM is beginning to fail. This count field should be + monitored for non-zero values and report such information + to the system administrator. + + +- ``size_mb`` - Total memory managed by this csrow attribute file + + This attribute file displays, in count of megabytes, the memory + that this csrow contains. + + +- ``mem_type`` - Memory Type attribute file + + This attribute file will display what type of memory is currently + on this csrow. Normally, either buffered or unbuffered memory. + Examples: + + - Registered-DDR + - Unbuffered-DDR + + +- ``edac_mode`` - EDAC Mode of operation attribute file + + This attribute file will display what type of Error detection + and correction is being utilized. + + +- ``dev_type`` - Device type attribute file + + This attribute file will display what type of DRAM device is + being utilized on this DIMM. + Examples: + + - x1 + - x2 + - x4 + - x8 + + +- ``ch0_ce_count`` - Channel 0 CE Count attribute file + + This attribute file will display the count of CEs on this + DIMM located in channel 0. + + +- ``ch0_ue_count`` - Channel 0 UE Count attribute file + + This attribute file will display the count of UEs on this + DIMM located in channel 0. + + +- ``ch0_dimm_label`` - Channel 0 DIMM Label control file + + + This control file allows this DIMM to have a label assigned + to it. With this label in the module, when errors occur + the output can provide the DIMM label in the system log. + This becomes vital for panic events to isolate the + cause of the UE event. + + DIMM Labels must be assigned after booting, with information + that correctly identifies the physical slot with its + silk screen label. This information is currently very + motherboard specific and determination of this information + must occur in userland at this time. + + +- ``ch1_ce_count`` - Channel 1 CE Count attribute file + + + This attribute file will display the count of CEs on this + DIMM located in channel 1. + + +- ``ch1_ue_count`` - Channel 1 UE Count attribute file + + + This attribute file will display the count of UEs on this + DIMM located in channel 0. + + +- ``ch1_dimm_label`` - Channel 1 DIMM Label control file + + This control file allows this DIMM to have a label assigned + to it. With this label in the module, when errors occur + the output can provide the DIMM label in the system log. + This becomes vital for panic events to isolate the + cause of the UE event. + + DIMM Labels must be assigned after booting, with information + that correctly identifies the physical slot with its + silk screen label. This information is currently very + motherboard specific and determination of this information + must occur in userland at this time. + + +System Logging +-------------- + +If logging for UEs and CEs is enabled, then system logs will contain +information indicating that errors have been detected:: + + EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac + EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac + + +The structure of the message is: + + +---------------------------------------+-------------+ + | Content + Example | + +=======================================+=============+ + | The memory controller | MC0 | + +---------------------------------------+-------------+ + | Error type | CE | + +---------------------------------------+-------------+ + | Memory page | 0x283 | + +---------------------------------------+-------------+ + | Offset in the page | 0xce0 | + +---------------------------------------+-------------+ + | The byte granularity | grain 8 | + | or resolution of the error | | + +---------------------------------------+-------------+ + | The error syndrome | 0xb741 | + +---------------------------------------+-------------+ + | Memory row | row 0 + + +---------------------------------------+-------------+ + | Memory channel | channel 1 | + +---------------------------------------+-------------+ + | DIMM label, if set prior | DIMM B1 | + +---------------------------------------+-------------+ + | And then an optional, driver-specific | | + | message that may have additional | | + | information. | | + +---------------------------------------+-------------+ + +Both UEs and CEs with no info will lack all but memory controller, error +type, a notice of "no info" and then an optional, driver-specific error +message. + + +PCI Bus Parity Detection +------------------------ + +On Header Type 00 devices, the primary status is looked at for any +parity error regardless of whether parity is enabled on the device or +not. (The spec indicates parity is generated in some cases). On Header +Type 01 bridges, the secondary status register is also looked at to see +if parity occurred on the bus on the other side of the bridge. + + +Sysfs configuration +------------------- + +Under ``/sys/devices/system/edac/pci`` are control and attribute files as +follows: + + +- ``check_pci_parity`` - Enable/Disable PCI Parity checking control file + + This control file enables or disables the PCI Bus Parity scanning + operation. Writing a 1 to this file enables the scanning. Writing + a 0 to this file disables the scanning. + + Enable:: + + echo "1" >/sys/devices/system/edac/pci/check_pci_parity + + Disable:: + + echo "0" >/sys/devices/system/edac/pci/check_pci_parity + + +- ``pci_parity_count`` - Parity Count + + This attribute file will display the number of parity errors that + have been detected. + + +Module parameters +----------------- + +- ``edac_mc_panic_on_ue`` - Panic on UE control file + + An uncorrectable error will cause a machine panic. This is usually + desirable. It is a bad idea to continue when an uncorrectable error + occurs - it is indeterminate what was uncorrected and the operating + system context might be so mangled that continuing will lead to further + corruption. If the kernel has MCE configured, then EDAC will never + notice the UE. + + LOAD TIME:: + + module/kernel parameter: edac_mc_panic_on_ue=[0|1] + + RUN TIME:: + + echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue + + +- ``edac_mc_log_ue`` - Log UE control file + + + Generate kernel messages describing uncorrectable errors. These errors + are reported through the system message log system. UE statistics + will be accumulated even when UE logging is disabled. + + LOAD TIME:: + + module/kernel parameter: edac_mc_log_ue=[0|1] + + RUN TIME:: + + echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue + + +- ``edac_mc_log_ce`` - Log CE control file + + + Generate kernel messages describing correctable errors. These + errors are reported through the system message log system. + CE statistics will be accumulated even when CE logging is disabled. + + LOAD TIME:: + + module/kernel parameter: edac_mc_log_ce=[0|1] + + RUN TIME:: + + echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce + + +- ``edac_mc_poll_msec`` - Polling period control file + + + The time period, in milliseconds, for polling for error information. + Too small a value wastes resources. Too large a value might delay + necessary handling of errors and might loose valuable information for + locating the error. 1000 milliseconds (once each second) is the current + default. Systems which require all the bandwidth they can get, may + increase this. + + LOAD TIME:: + + module/kernel parameter: edac_mc_poll_msec=[0|1] + + RUN TIME:: + + echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec + + +- ``panic_on_pci_parity`` - Panic on PCI PARITY Error + + + This control file enables or disables panicking when a parity + error has been detected. + + + module/kernel parameter:: + + edac_panic_on_pci_pe=[0|1] + + Enable:: + + echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe + + Disable:: + + echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe + + + +EDAC device type +---------------- + +In the header file, edac_pci.h, there is a series of edac_device structures +and APIs for the EDAC_DEVICE. + +User space access to an edac_device is through the sysfs interface. + +At the location ``/sys/devices/system/edac`` (sysfs) new edac_device devices +will appear. + +There is a three level tree beneath the above ``edac`` directory. For example, +the ``test_device_edac`` device (found at the http://bluesmoke.sourceforget.net +website) installs itself as:: + + /sys/devices/system/edac/test-instance + +in this directory are various controls, a symlink and one or more ``instance`` +directories. + +The standard default controls are: + + ============== ======================================================= + log_ce boolean to log CE events + log_ue boolean to log UE events + panic_on_ue boolean to ``panic`` the system if an UE is encountered + (default off, can be set true via startup script) + poll_msec time period between POLL cycles for events + ============== ======================================================= + +The test_device_edac device adds at least one of its own custom control: + + ============== ================================================== + test_bits which in the current test driver does nothing but + show how it is installed. A ported driver can + add one or more such controls and/or attributes + for specific uses. + One out-of-tree driver uses controls here to allow + for ERROR INJECTION operations to hardware + injection registers + ============== ================================================== + +The symlink points to the 'struct dev' that is registered for this edac_device. + +Instances +--------- + +One or more instance directories are present. For the ``test_device_edac`` +case: + + +----------------+ + | test-instance0 | + +----------------+ + + +In this directory there are two default counter attributes, which are totals of +counter in deeper subdirectories. + + ============== ==================================== + ce_count total of CE events of subdirectories + ue_count total of UE events of subdirectories + ============== ==================================== + +Blocks +------ + +At the lowest directory level is the ``block`` directory. There can be 0, 1 +or more blocks specified in each instance: + + +-------------+ + | test-block0 | + +-------------+ + +In this directory the default attributes are: + + ============== ================================================ + ce_count which is counter of CE events for this ``block`` + of hardware being monitored + ue_count which is counter of UE events for this ``block`` + of hardware being monitored + ============== ================================================ + + +The ``test_device_edac`` device adds 4 attributes and 1 control: + + ================== ==================================================== + test-block-bits-0 for every POLL cycle this counter + is incremented + test-block-bits-1 every 10 cycles, this counter is bumped once, + and test-block-bits-0 is set to 0 + test-block-bits-2 every 100 cycles, this counter is bumped once, + and test-block-bits-1 is set to 0 + test-block-bits-3 every 1000 cycles, this counter is bumped once, + and test-block-bits-2 is set to 0 + ================== ==================================================== + + + ================== ==================================================== + reset-counters writing ANY thing to this control will + reset all the above counters. + ================== ==================================================== + + +Use of the ``test_device_edac`` driver should enable any others to create their own +unique drivers for their hardware systems. + +The ``test_device_edac`` sample driver is located at the +http://bluesmoke.sourceforge.net project site for EDAC. + + +Usage of EDAC APIs on Nehalem and newer Intel CPUs +-------------------------------------------------- + +On older Intel architectures, the memory controller was part of the North +Bridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake and +newer Intel architectures integrated an enhanced version of the memory +controller (MC) inside the CPUs. + +This chapter will cover the differences of the enhanced memory controllers +found on newer Intel CPUs, such as ``i7core_edac``, ``sb_edac`` and +``sbx_edac`` drivers. + +.. note:: + + The Xeon E7 processor families use a separate chip for the memory + controller, called Intel Scalable Memory Buffer. This section doesn't + apply for such families. + +1) There is one Memory Controller per Quick Patch Interconnect + (QPI). At the driver, the term "socket" means one QPI. This is + associated with a physical CPU socket. + + Each MC have 3 physical read channels, 3 physical write channels and + 3 logic channels. The driver currently sees it as just 3 channels. + Each channel can have up to 3 DIMMs. + + The minimum known unity is DIMMs. There are no information about csrows. + As EDAC API maps the minimum unity is csrows, the driver sequentially + maps channel/DIMM into different csrows. + + For example, supposing the following layout:: + + Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs + dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 + dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400 + Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs + dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 + Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs + dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 + + The driver will map it as:: + + csrow0: channel 0, dimm0 + csrow1: channel 0, dimm1 + csrow2: channel 1, dimm0 + csrow3: channel 2, dimm0 + + exports one DIMM per csrow. + + Each QPI is exported as a different memory controller. + +2) The MC has the ability to inject errors to test drivers. The drivers + implement this functionality via some error injection nodes: + + For injecting a memory error, there are some sysfs nodes, under + ``/sys/devices/system/edac/mc/mc?/``: + + - ``inject_addrmatch/*``: + Controls the error injection mask register. It is possible to specify + several characteristics of the address to match an error code:: + + dimm = the affected dimm. Numbers are relative to a channel; + rank = the memory rank; + channel = the channel that will generate an error; + bank = the affected bank; + page = the page address; + column (or col) = the address column. + + each of the above values can be set to "any" to match any valid value. + + At driver init, all values are set to any. + + For example, to generate an error at rank 1 of dimm 2, for any channel, + any bank, any page, any column:: + + echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm + echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank + + To return to the default behaviour of matching any, you can do:: + + echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm + echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank + + - ``inject_eccmask``: + specifies what bits will have troubles, + + - ``inject_section``: + specifies what ECC cache section will get the error:: + + 3 for both + 2 for the highest + 1 for the lowest + + - ``inject_type``: + specifies the type of error, being a combination of the following bits:: + + bit 0 - repeat + bit 1 - ecc + bit 2 - parity + + - ``inject_enable``: + starts the error generation when something different than 0 is written. + + All inject vars can be read. root permission is needed for write. + + Datasheet states that the error will only be generated after a write on an + address that matches inject_addrmatch. It seems, however, that reading will + also produce an error. + + For example, the following code will generate an error for any write access + at socket 0, on any DIMM/address on channel 2:: + + echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel + echo 2 >/sys/devices/system/edac/mc/mc0/inject_type + echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask + echo 3 >/sys/devices/system/edac/mc/mc0/inject_section + echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable + dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null + + For socket 1, it is needed to replace "mc0" by "mc1" at the above + commands. + + The generated error message will look like:: + + EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error)) + +3) Corrected Error memory register counters + + Those newer MCs have some registers to count memory errors. The driver + uses those registers to report Corrected Errors on devices with Registered + DIMMs. + + However, those counters don't work with Unregistered DIMM. As the chipset + offers some counters that also work with UDIMMs (but with a worse level of + granularity than the default ones), the driver exposes those registers for + UDIMM memories. + + They can be read by looking at the contents of ``all_channel_counts/``:: + + $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done + /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 + 0 + /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 + 0 + /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 + 0 + + What happens here is that errors on different csrows, but at the same + dimm number will increment the same counter. + So, in this memory mapping:: + + csrow0: channel 0, dimm0 + csrow1: channel 0, dimm1 + csrow2: channel 1, dimm0 + csrow3: channel 2, dimm0 + + The hardware will increment udimm0 for an error at the first dimm at either + csrow0, csrow2 or csrow3; + + The hardware will increment udimm1 for an error at the second dimm at either + csrow0, csrow2 or csrow3; + + The hardware will increment udimm2 for an error at the third dimm at either + csrow0, csrow2 or csrow3; + +4) Standard error counters + + The standard error counters are generated when an mcelog error is received + by the driver. Since, with UDIMM, this is counted by software, it is + possible that some errors could be lost. With RDIMM's, they display the + contents of the registers + +Reference documents used on ``amd64_edac`` +------------------------------------------ + +``amd64_edac`` module is based on the following documents +(available from http://support.amd.com/en-us/search/tech-docs): + +1. :Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD + Opteron Processors + :AMD publication #: 26094 + :Revision: 3.26 + :Link: http://support.amd.com/TechDocs/26094.PDF + +2. :Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh + Processors + :AMD publication #: 32559 + :Revision: 3.00 + :Issue Date: May 2006 + :Link: http://support.amd.com/TechDocs/32559.pdf + +3. :Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h + Processors + :AMD publication #: 31116 + :Revision: 3.00 + :Issue Date: September 07, 2007 + :Link: http://support.amd.com/TechDocs/31116.pdf + +4. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h + Models 30h-3Fh Processors + :AMD publication #: 49125 + :Revision: 3.06 + :Issue Date: 2/12/2015 (latest release) + :Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf + +5. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h + Models 60h-6Fh Processors + :AMD publication #: 50742 + :Revision: 3.01 + :Issue Date: 7/23/2015 (latest release) + :Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf + +6. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h + Models 00h-0Fh Processors + :AMD publication #: 48751 + :Revision: 3.03 + :Issue Date: 2/23/2015 (latest release) + :Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf + +Credits +======= + +* Written by Doug Thompson + + - 7 Dec 2005 + - 17 Jul 2007 Updated + +* |copy| Mauro Carvalho Chehab + + - 05 Aug 2009 Nehalem interface + - 26 Oct 2016 Converted to ReST and cleanups at the Nehalem section + +* EDAC authors/maintainers: + + - Doug Thompson, Dave Jiang, Dave Peterson et al, + - Mauro Carvalho Chehab + - Borislav Petkov + - original author: Thayne Harbaugh diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt index 09aed5588d7c..a03b0357c017 100644 --- a/Documentation/arm/stm32/overview.txt +++ b/Documentation/arm/stm32/overview.txt @@ -5,7 +5,8 @@ Introduction ------------ The STMicroelectronics family of Cortex-M based MCUs are supported by the - 'STM32' platform of ARM Linux. Currently only the STM32F429 is supported. + 'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4) + and STM32F746 (Cortex-M7) are supported. Configuration diff --git a/Documentation/arm/stm32/stm32f746-overview.txt b/Documentation/arm/stm32/stm32f746-overview.txt new file mode 100644 index 000000000000..cffd2b1ccd6f --- /dev/null +++ b/Documentation/arm/stm32/stm32f746-overview.txt @@ -0,0 +1,34 @@ + STM32F746 Overview + ================== + + Introduction + ------------ + The STM32F746 is a Cortex-M7 MCU aimed at various applications. + It features: + - Cortex-M7 core running up to @216MHz + - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM) + - FMC controller to connect SDRAM, NOR and NAND memories + - Dual mode QSPI + - SD/MMC/SDIO support + - Ethernet controller + - USB OTFG FS & HS controllers + - I2C, SPI, CAN busses support + - Several 16 & 32 bits general purpose timers + - Serial Audio interface + - LCD controller + - HDMI-CEC + - SPDIFRX + + Resources + --------- + Datasheet and reference manual are publicly available on ST website: + - http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html + + Document Author + --------------- + Alexandre Torgue + + + + + diff --git a/Documentation/block/queue-sysfs.txt b/Documentation/block/queue-sysfs.txt index 51642159aedb..c0a3bb5a6e4e 100644 --- a/Documentation/block/queue-sysfs.txt +++ b/Documentation/block/queue-sysfs.txt @@ -54,9 +54,9 @@ This is the hardware sector size of the device, in bytes. io_poll (RW) ------------ -When read, this file shows the total number of block IO polls and how -many returned success. Writing '0' to this file will disable polling -for this device. Writing any non-zero value will enable this feature. +When read, this file shows whether polling is enabled (1) or disabled +(0). Writing '0' to this file will disable polling for this device. +Writing any non-zero value will enable this feature. io_poll_delay (RW) ------------------ diff --git a/Documentation/crypto/api-aead.rst b/Documentation/crypto/api-aead.rst new file mode 100644 index 000000000000..d15256f1ae36 --- /dev/null +++ b/Documentation/crypto/api-aead.rst @@ -0,0 +1,23 @@ +Authenticated Encryption With Associated Data (AEAD) Algorithm Definitions +-------------------------------------------------------------------------- + +.. kernel-doc:: include/crypto/aead.h + :doc: Authenticated Encryption With Associated Data (AEAD) Cipher API + +.. kernel-doc:: include/crypto/aead.h + :functions: aead_request aead_alg + +Authenticated Encryption With Associated Data (AEAD) Cipher API +--------------------------------------------------------------- + +.. kernel-doc:: include/crypto/aead.h + :functions: crypto_alloc_aead crypto_free_aead crypto_aead_ivsize crypto_aead_authsize crypto_aead_blocksize crypto_aead_setkey crypto_aead_setauthsize crypto_aead_encrypt crypto_aead_decrypt + +Asynchronous AEAD Request Handle +-------------------------------- + +.. kernel-doc:: include/crypto/aead.h + :doc: Asynchronous AEAD Request Handle + +.. kernel-doc:: include/crypto/aead.h + :functions: crypto_aead_reqsize aead_request_set_tfm aead_request_alloc aead_request_free aead_request_set_callback aead_request_set_crypt aead_request_set_ad diff --git a/Documentation/crypto/api-akcipher.rst b/Documentation/crypto/api-akcipher.rst new file mode 100644 index 000000000000..40aa8746e2a1 --- /dev/null +++ b/Documentation/crypto/api-akcipher.rst @@ -0,0 +1,20 @@ +Asymmetric Cipher Algorithm Definitions +--------------------------------------- + +.. kernel-doc:: include/crypto/akcipher.h + :functions: akcipher_alg akcipher_request + +Asymmetric Cipher API +--------------------- + +.. kernel-doc:: include/crypto/akcipher.h + :doc: Generic Public Key API + +.. kernel-doc:: include/crypto/akcipher.h + :functions: crypto_alloc_akcipher crypto_free_akcipher crypto_akcipher_set_pub_key crypto_akcipher_set_priv_key crypto_akcipher_maxsize crypto_akcipher_encrypt crypto_akcipher_decrypt crypto_akcipher_sign crypto_akcipher_verify + +Asymmetric Cipher Request Handle +-------------------------------- + +.. kernel-doc:: include/crypto/akcipher.h + :functions: akcipher_request_alloc akcipher_request_free akcipher_request_set_callback akcipher_request_set_crypt diff --git a/Documentation/crypto/api-digest.rst b/Documentation/crypto/api-digest.rst new file mode 100644 index 000000000000..07356fa99200 --- /dev/null +++ b/Documentation/crypto/api-digest.rst @@ -0,0 +1,35 @@ +Message Digest Algorithm Definitions +------------------------------------ + +.. kernel-doc:: include/crypto/hash.h + :doc: Message Digest Algorithm Definitions + +.. kernel-doc:: include/crypto/hash.h + :functions: hash_alg_common ahash_alg shash_alg + +Asynchronous Message Digest API +------------------------------- + +.. kernel-doc:: include/crypto/hash.h + :doc: Asynchronous Message Digest API + +.. kernel-doc:: include/crypto/hash.h + :functions: crypto_alloc_ahash crypto_free_ahash crypto_ahash_init crypto_ahash_digestsize crypto_ahash_reqtfm crypto_ahash_reqsize crypto_ahash_setkey crypto_ahash_finup crypto_ahash_final crypto_ahash_digest crypto_ahash_export crypto_ahash_import + +Asynchronous Hash Request Handle +-------------------------------- + +.. kernel-doc:: include/crypto/hash.h + :doc: Asynchronous Hash Request Handle + +.. kernel-doc:: include/crypto/hash.h + :functions: ahash_request_set_tfm ahash_request_alloc ahash_request_free ahash_request_set_callback ahash_request_set_crypt + +Synchronous Message Digest API +------------------------------ + +.. kernel-doc:: include/crypto/hash.h + :doc: Synchronous Message Digest API + +.. kernel-doc:: include/crypto/hash.h + :functions: crypto_alloc_shash crypto_free_shash crypto_shash_blocksize crypto_shash_digestsize crypto_shash_descsize crypto_shash_setkey crypto_shash_digest crypto_shash_export crypto_shash_import crypto_shash_init crypto_shash_update crypto_shash_final crypto_shash_finup diff --git a/Documentation/crypto/api-intro.txt b/Documentation/crypto/api-intro.txt index beda682e8d77..45d943fcae5b 100644 --- a/Documentation/crypto/api-intro.txt +++ b/Documentation/crypto/api-intro.txt @@ -44,12 +44,9 @@ one block while the former can operate on an arbitrary amount of data, subject to block size requirements (i.e., non-stream ciphers can only process multiples of blocks). -Support for hardware crypto devices via an asynchronous interface is -under development. - Here's an example of how to use the API: - #include + #include #include #include diff --git a/Documentation/crypto/api-kpp.rst b/Documentation/crypto/api-kpp.rst new file mode 100644 index 000000000000..7d86ab906bdf --- /dev/null +++ b/Documentation/crypto/api-kpp.rst @@ -0,0 +1,38 @@ +Key-agreement Protocol Primitives (KPP) Cipher Algorithm Definitions +-------------------------------------------------------------------- + +.. kernel-doc:: include/crypto/kpp.h + :functions: kpp_request crypto_kpp kpp_alg kpp_secret + +Key-agreement Protocol Primitives (KPP) Cipher API +-------------------------------------------------- + +.. kernel-doc:: include/crypto/kpp.h + :doc: Generic Key-agreement Protocol Primitives API + +.. kernel-doc:: include/crypto/kpp.h + :functions: crypto_alloc_kpp crypto_free_kpp crypto_kpp_set_secret crypto_kpp_generate_public_key crypto_kpp_compute_shared_secret crypto_kpp_maxsize + +Key-agreement Protocol Primitives (KPP) Cipher Request Handle +------------------------------------------------------------- + +.. kernel-doc:: include/crypto/kpp.h + :functions: kpp_request_alloc kpp_request_free kpp_request_set_callback kpp_request_set_input kpp_request_set_output + +ECDH Helper Functions +--------------------- + +.. kernel-doc:: include/crypto/ecdh.h + :doc: ECDH Helper Functions + +.. kernel-doc:: include/crypto/ecdh.h + :functions: ecdh crypto_ecdh_key_len crypto_ecdh_encode_key crypto_ecdh_decode_key + +DH Helper Functions +------------------- + +.. kernel-doc:: include/crypto/dh.h + :doc: DH Helper Functions + +.. kernel-doc:: include/crypto/dh.h + :functions: dh crypto_dh_key_len crypto_dh_encode_key crypto_dh_decode_key diff --git a/Documentation/crypto/api-rng.rst b/Documentation/crypto/api-rng.rst new file mode 100644 index 000000000000..10ba7436cee4 --- /dev/null +++ b/Documentation/crypto/api-rng.rst @@ -0,0 +1,14 @@ +Random Number Algorithm Definitions +----------------------------------- + +.. kernel-doc:: include/crypto/rng.h + :functions: rng_alg + +Crypto API Random Number API +---------------------------- + +.. kernel-doc:: include/crypto/rng.h + :doc: Random number generator API + +.. kernel-doc:: include/crypto/rng.h + :functions: crypto_alloc_rng crypto_rng_alg crypto_free_rng crypto_rng_generate crypto_rng_get_bytes crypto_rng_reset crypto_rng_seedsize diff --git a/Documentation/crypto/api-samples.rst b/Documentation/crypto/api-samples.rst new file mode 100644 index 000000000000..0a10819f6107 --- /dev/null +++ b/Documentation/crypto/api-samples.rst @@ -0,0 +1,224 @@ +Code Examples +============= + +Code Example For Symmetric Key Cipher Operation +----------------------------------------------- + +:: + + + struct tcrypt_result { + struct completion completion; + int err; + }; + + /* tie all data structures together */ + struct skcipher_def { + struct scatterlist sg; + struct crypto_skcipher *tfm; + struct skcipher_request *req; + struct tcrypt_result result; + }; + + /* Callback function */ + static void test_skcipher_cb(struct crypto_async_request *req, int error) + { + struct tcrypt_result *result = req->data; + + if (error == -EINPROGRESS) + return; + result->err = error; + complete(&result->completion); + pr_info("Encryption finished successfully\n"); + } + + /* Perform cipher operation */ + static unsigned int test_skcipher_encdec(struct skcipher_def *sk, + int enc) + { + int rc = 0; + + if (enc) + rc = crypto_skcipher_encrypt(sk->req); + else + rc = crypto_skcipher_decrypt(sk->req); + + switch (rc) { + case 0: + break; + case -EINPROGRESS: + case -EBUSY: + rc = wait_for_completion_interruptible( + &sk->result.completion); + if (!rc && !sk->result.err) { + reinit_completion(&sk->result.completion); + break; + } + default: + pr_info("skcipher encrypt returned with %d result %d\n", + rc, sk->result.err); + break; + } + init_completion(&sk->result.completion); + + return rc; + } + + /* Initialize and trigger cipher operation */ + static int test_skcipher(void) + { + struct skcipher_def sk; + struct crypto_skcipher *skcipher = NULL; + struct skcipher_request *req = NULL; + char *scratchpad = NULL; + char *ivdata = NULL; + unsigned char key[32]; + int ret = -EFAULT; + + skcipher = crypto_alloc_skcipher("cbc-aes-aesni", 0, 0); + if (IS_ERR(skcipher)) { + pr_info("could not allocate skcipher handle\n"); + return PTR_ERR(skcipher); + } + + req = skcipher_request_alloc(skcipher, GFP_KERNEL); + if (!req) { + pr_info("could not allocate skcipher request\n"); + ret = -ENOMEM; + goto out; + } + + skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + test_skcipher_cb, + &sk.result); + + /* AES 256 with random key */ + get_random_bytes(&key, 32); + if (crypto_skcipher_setkey(skcipher, key, 32)) { + pr_info("key could not be set\n"); + ret = -EAGAIN; + goto out; + } + + /* IV will be random */ + ivdata = kmalloc(16, GFP_KERNEL); + if (!ivdata) { + pr_info("could not allocate ivdata\n"); + goto out; + } + get_random_bytes(ivdata, 16); + + /* Input data will be random */ + scratchpad = kmalloc(16, GFP_KERNEL); + if (!scratchpad) { + pr_info("could not allocate scratchpad\n"); + goto out; + } + get_random_bytes(scratchpad, 16); + + sk.tfm = skcipher; + sk.req = req; + + /* We encrypt one block */ + sg_init_one(&sk.sg, scratchpad, 16); + skcipher_request_set_crypt(req, &sk.sg, &sk.sg, 16, ivdata); + init_completion(&sk.result.completion); + + /* encrypt data */ + ret = test_skcipher_encdec(&sk, 1); + if (ret) + goto out; + + pr_info("Encryption triggered successfully\n"); + + out: + if (skcipher) + crypto_free_skcipher(skcipher); + if (req) + skcipher_request_free(req); + if (ivdata) + kfree(ivdata); + if (scratchpad) + kfree(scratchpad); + return ret; + } + + +Code Example For Use of Operational State Memory With SHASH +----------------------------------------------------------- + +:: + + + struct sdesc { + struct shash_desc shash; + char ctx[]; + }; + + static struct sdescinit_sdesc(struct crypto_shash *alg) + { + struct sdescsdesc; + int size; + + size = sizeof(struct shash_desc) + crypto_shash_descsize(alg); + sdesc = kmalloc(size, GFP_KERNEL); + if (!sdesc) + return ERR_PTR(-ENOMEM); + sdesc->shash.tfm = alg; + sdesc->shash.flags = 0x0; + return sdesc; + } + + static int calc_hash(struct crypto_shashalg, + const unsigned chardata, unsigned int datalen, + unsigned chardigest) { + struct sdescsdesc; + int ret; + + sdesc = init_sdesc(alg); + if (IS_ERR(sdesc)) { + pr_info("trusted_key: can't alloc %s\n", hash_alg); + return PTR_ERR(sdesc); + } + + ret = crypto_shash_digest(&sdesc->shash, data, datalen, digest); + kfree(sdesc); + return ret; + } + + +Code Example For Random Number Generator Usage +---------------------------------------------- + +:: + + + static int get_random_numbers(u8 *buf, unsigned int len) + { + struct crypto_rngrng = NULL; + chardrbg = "drbg_nopr_sha256"; /* Hash DRBG with SHA-256, no PR */ + int ret; + + if (!buf || !len) { + pr_debug("No output buffer provided\n"); + return -EINVAL; + } + + rng = crypto_alloc_rng(drbg, 0, 0); + if (IS_ERR(rng)) { + pr_debug("could not allocate RNG handle for %s\n", drbg); + return -PTR_ERR(rng); + } + + ret = crypto_rng_get_bytes(rng, buf, len); + if (ret < 0) + pr_debug("generation of random numbers failed\n"); + else if (ret == 0) + pr_debug("RNG returned no data"); + else + pr_debug("RNG returned %d bytes of data\n", ret); + + out: + crypto_free_rng(rng); + return ret; + } diff --git a/Documentation/crypto/api-skcipher.rst b/Documentation/crypto/api-skcipher.rst new file mode 100644 index 000000000000..b20028a361a9 --- /dev/null +++ b/Documentation/crypto/api-skcipher.rst @@ -0,0 +1,62 @@ +Block Cipher Algorithm Definitions +---------------------------------- + +.. kernel-doc:: include/linux/crypto.h + :doc: Block Cipher Algorithm Definitions + +.. kernel-doc:: include/linux/crypto.h + :functions: crypto_alg ablkcipher_alg blkcipher_alg cipher_alg + +Symmetric Key Cipher API +------------------------ + +.. kernel-doc:: include/crypto/skcipher.h + :doc: Symmetric Key Cipher API + +.. kernel-doc:: include/crypto/skcipher.h + :functions: crypto_alloc_skcipher crypto_free_skcipher crypto_has_skcipher crypto_skcipher_ivsize crypto_skcipher_blocksize crypto_skcipher_setkey crypto_skcipher_reqtfm crypto_skcipher_encrypt crypto_skcipher_decrypt + +Symmetric Key Cipher Request Handle +----------------------------------- + +.. kernel-doc:: include/crypto/skcipher.h + :doc: Symmetric Key Cipher Request Handle + +.. kernel-doc:: include/crypto/skcipher.h + :functions: crypto_skcipher_reqsize skcipher_request_set_tfm skcipher_request_alloc skcipher_request_free skcipher_request_set_callback skcipher_request_set_crypt + +Single Block Cipher API +----------------------- + +.. kernel-doc:: include/linux/crypto.h + :doc: Single Block Cipher API + +.. kernel-doc:: include/linux/crypto.h + :functions: crypto_alloc_cipher crypto_free_cipher crypto_has_cipher crypto_cipher_blocksize crypto_cipher_setkey crypto_cipher_encrypt_one crypto_cipher_decrypt_one + +Asynchronous Block Cipher API - Deprecated +------------------------------------------ + +.. kernel-doc:: include/linux/crypto.h + :doc: Asynchronous Block Cipher API + +.. kernel-doc:: include/linux/crypto.h + :functions: crypto_free_ablkcipher crypto_has_ablkcipher crypto_ablkcipher_ivsize crypto_ablkcipher_blocksize crypto_ablkcipher_setkey crypto_ablkcipher_reqtfm crypto_ablkcipher_encrypt crypto_ablkcipher_decrypt + +Asynchronous Cipher Request Handle - Deprecated +----------------------------------------------- + +.. kernel-doc:: include/linux/crypto.h + :doc: Asynchronous Cipher Request Handle + +.. kernel-doc:: include/linux/crypto.h + :functions: crypto_ablkcipher_reqsize ablkcipher_request_set_tfm ablkcipher_request_alloc ablkcipher_request_free ablkcipher_request_set_callback ablkcipher_request_set_crypt + +Synchronous Block Cipher API - Deprecated +----------------------------------------- + +.. kernel-doc:: include/linux/crypto.h + :doc: Synchronous Block Cipher API + +.. kernel-doc:: include/linux/crypto.h + :functions: crypto_alloc_blkcipher rypto_free_blkcipher crypto_has_blkcipher crypto_blkcipher_name crypto_blkcipher_ivsize crypto_blkcipher_blocksize crypto_blkcipher_setkey crypto_blkcipher_encrypt crypto_blkcipher_encrypt_iv crypto_blkcipher_decrypt crypto_blkcipher_decrypt_iv crypto_blkcipher_set_iv crypto_blkcipher_get_iv diff --git a/Documentation/crypto/api.rst b/Documentation/crypto/api.rst new file mode 100644 index 000000000000..2e519193ab4a --- /dev/null +++ b/Documentation/crypto/api.rst @@ -0,0 +1,25 @@ +Programming Interface +===================== + +Please note that the kernel crypto API contains the AEAD givcrypt API +(crypto_aead_giv\* and aead_givcrypt\* function calls in +include/crypto/aead.h). This API is obsolete and will be removed in the +future. To obtain the functionality of an AEAD cipher with internal IV +generation, use the IV generator as a regular cipher. For example, +rfc4106(gcm(aes)) is the AEAD cipher with external IV generation and +seqniv(rfc4106(gcm(aes))) implies that the kernel crypto API generates +the IV. Different IV generators are available. + +.. class:: toc-title + + Table of contents + +.. toctree:: + :maxdepth: 2 + + api-skcipher + api-aead + api-digest + api-rng + api-akcipher + api-kpp diff --git a/Documentation/crypto/architecture.rst b/Documentation/crypto/architecture.rst new file mode 100644 index 000000000000..ca2d09b991f5 --- /dev/null +++ b/Documentation/crypto/architecture.rst @@ -0,0 +1,441 @@ +Kernel Crypto API Architecture +============================== + +Cipher algorithm types +---------------------- + +The kernel crypto API provides different API calls for the following +cipher types: + +- Symmetric ciphers + +- AEAD ciphers + +- Message digest, including keyed message digest + +- Random number generation + +- User space interface + +Ciphers And Templates +--------------------- + +The kernel crypto API provides implementations of single block ciphers +and message digests. In addition, the kernel crypto API provides +numerous "templates" that can be used in conjunction with the single +block ciphers and message digests. Templates include all types of block +chaining mode, the HMAC mechanism, etc. + +Single block ciphers and message digests can either be directly used by +a caller or invoked together with a template to form multi-block ciphers +or keyed message digests. + +A single block cipher may even be called with multiple templates. +However, templates cannot be used without a single cipher. + +See /proc/crypto and search for "name". For example: + +- aes + +- ecb(aes) + +- cmac(aes) + +- ccm(aes) + +- rfc4106(gcm(aes)) + +- sha1 + +- hmac(sha1) + +- authenc(hmac(sha1),cbc(aes)) + +In these examples, "aes" and "sha1" are the ciphers and all others are +the templates. + +Synchronous And Asynchronous Operation +-------------------------------------- + +The kernel crypto API provides synchronous and asynchronous API +operations. + +When using the synchronous API operation, the caller invokes a cipher +operation which is performed synchronously by the kernel crypto API. +That means, the caller waits until the cipher operation completes. +Therefore, the kernel crypto API calls work like regular function calls. +For synchronous operation, the set of API calls is small and +conceptually similar to any other crypto library. + +Asynchronous operation is provided by the kernel crypto API which +implies that the invocation of a cipher operation will complete almost +instantly. That invocation triggers the cipher operation but it does not +signal its completion. Before invoking a cipher operation, the caller +must provide a callback function the kernel crypto API can invoke to +signal the completion of the cipher operation. Furthermore, the caller +must ensure it can handle such asynchronous events by applying +appropriate locking around its data. The kernel crypto API does not +perform any special serialization operation to protect the caller's data +integrity. + +Crypto API Cipher References And Priority +----------------------------------------- + +A cipher is referenced by the caller with a string. That string has the +following semantics: + +:: + + template(single block cipher) + + +where "template" and "single block cipher" is the aforementioned +template and single block cipher, respectively. If applicable, +additional templates may enclose other templates, such as + +:: + + template1(template2(single block cipher))) + + +The kernel crypto API may provide multiple implementations of a template +or a single block cipher. For example, AES on newer Intel hardware has +the following implementations: AES-NI, assembler implementation, or +straight C. Now, when using the string "aes" with the kernel crypto API, +which cipher implementation is used? The answer to that question is the +priority number assigned to each cipher implementation by the kernel +crypto API. When a caller uses the string to refer to a cipher during +initialization of a cipher handle, the kernel crypto API looks up all +implementations providing an implementation with that name and selects +the implementation with the highest priority. + +Now, a caller may have the need to refer to a specific cipher +implementation and thus does not want to rely on the priority-based +selection. To accommodate this scenario, the kernel crypto API allows +the cipher implementation to register a unique name in addition to +common names. When using that unique name, a caller is therefore always +sure to refer to the intended cipher implementation. + +The list of available ciphers is given in /proc/crypto. However, that +list does not specify all possible permutations of templates and +ciphers. Each block listed in /proc/crypto may contain the following +information -- if one of the components listed as follows are not +applicable to a cipher, it is not displayed: + +- name: the generic name of the cipher that is subject to the + priority-based selection -- this name can be used by the cipher + allocation API calls (all names listed above are examples for such + generic names) + +- driver: the unique name of the cipher -- this name can be used by the + cipher allocation API calls + +- module: the kernel module providing the cipher implementation (or + "kernel" for statically linked ciphers) + +- priority: the priority value of the cipher implementation + +- refcnt: the reference count of the respective cipher (i.e. the number + of current consumers of this cipher) + +- selftest: specification whether the self test for the cipher passed + +- type: + + - skcipher for symmetric key ciphers + + - cipher for single block ciphers that may be used with an + additional template + + - shash for synchronous message digest + + - ahash for asynchronous message digest + + - aead for AEAD cipher type + + - compression for compression type transformations + + - rng for random number generator + + - givcipher for cipher with associated IV generator (see the geniv + entry below for the specification of the IV generator type used by + the cipher implementation) + + - kpp for a Key-agreement Protocol Primitive (KPP) cipher such as + an ECDH or DH implementation + +- blocksize: blocksize of cipher in bytes + +- keysize: key size in bytes + +- ivsize: IV size in bytes + +- seedsize: required size of seed data for random number generator + +- digestsize: output size of the message digest + +- geniv: IV generation type: + + - eseqiv for encrypted sequence number based IV generation + + - seqiv for sequence number based IV generation + + - chainiv for chain iv generation + + - is a marker that the cipher implements IV generation and + handling as it is specific to the given cipher + +Key Sizes +--------- + +When allocating a cipher handle, the caller only specifies the cipher +type. Symmetric ciphers, however, typically support multiple key sizes +(e.g. AES-128 vs. AES-192 vs. AES-256). These key sizes are determined +with the length of the provided key. Thus, the kernel crypto API does +not provide a separate way to select the particular symmetric cipher key +size. + +Cipher Allocation Type And Masks +-------------------------------- + +The different cipher handle allocation functions allow the specification +of a type and mask flag. Both parameters have the following meaning (and +are therefore not covered in the subsequent sections). + +The type flag specifies the type of the cipher algorithm. The caller +usually provides a 0 when the caller wants the default handling. +Otherwise, the caller may provide the following selections which match +the aforementioned cipher types: + +- CRYPTO_ALG_TYPE_CIPHER Single block cipher + +- CRYPTO_ALG_TYPE_COMPRESS Compression + +- CRYPTO_ALG_TYPE_AEAD Authenticated Encryption with Associated Data + (MAC) + +- CRYPTO_ALG_TYPE_BLKCIPHER Synchronous multi-block cipher + +- CRYPTO_ALG_TYPE_ABLKCIPHER Asynchronous multi-block cipher + +- CRYPTO_ALG_TYPE_GIVCIPHER Asynchronous multi-block cipher packed + together with an IV generator (see geniv field in the /proc/crypto + listing for the known IV generators) + +- CRYPTO_ALG_TYPE_KPP Key-agreement Protocol Primitive (KPP) such as + an ECDH or DH implementation + +- CRYPTO_ALG_TYPE_DIGEST Raw message digest + +- CRYPTO_ALG_TYPE_HASH Alias for CRYPTO_ALG_TYPE_DIGEST + +- CRYPTO_ALG_TYPE_SHASH Synchronous multi-block hash + +- CRYPTO_ALG_TYPE_AHASH Asynchronous multi-block hash + +- CRYPTO_ALG_TYPE_RNG Random Number Generation + +- CRYPTO_ALG_TYPE_AKCIPHER Asymmetric cipher + +- CRYPTO_ALG_TYPE_PCOMPRESS Enhanced version of + CRYPTO_ALG_TYPE_COMPRESS allowing for segmented compression / + decompression instead of performing the operation on one segment + only. CRYPTO_ALG_TYPE_PCOMPRESS is intended to replace + CRYPTO_ALG_TYPE_COMPRESS once existing consumers are converted. + +The mask flag restricts the type of cipher. The only allowed flag is +CRYPTO_ALG_ASYNC to restrict the cipher lookup function to +asynchronous ciphers. Usually, a caller provides a 0 for the mask flag. + +When the caller provides a mask and type specification, the caller +limits the search the kernel crypto API can perform for a suitable +cipher implementation for the given cipher name. That means, even when a +caller uses a cipher name that exists during its initialization call, +the kernel crypto API may not select it due to the used type and mask +field. + +Internal Structure of Kernel Crypto API +--------------------------------------- + +The kernel crypto API has an internal structure where a cipher +implementation may use many layers and indirections. This section shall +help to clarify how the kernel crypto API uses various components to +implement the complete cipher. + +The following subsections explain the internal structure based on +existing cipher implementations. The first section addresses the most +complex scenario where all other scenarios form a logical subset. + +Generic AEAD Cipher Structure +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following ASCII art decomposes the kernel crypto API layers when +using the AEAD cipher with the automated IV generation. The shown +example is used by the IPSEC layer. + +For other use cases of AEAD ciphers, the ASCII art applies as well, but +the caller may not use the AEAD cipher with a separate IV generator. In +this case, the caller must generate the IV. + +The depicted example decomposes the AEAD cipher of GCM(AES) based on the +generic C implementations (gcm.c, aes-generic.c, ctr.c, ghash-generic.c, +seqiv.c). The generic implementation serves as an example showing the +complete logic of the kernel crypto API. + +It is possible that some streamlined cipher implementations (like +AES-NI) provide implementations merging aspects which in the view of the +kernel crypto API cannot be decomposed into layers any more. In case of +the AES-NI implementation, the CTR mode, the GHASH implementation and +the AES cipher are all merged into one cipher implementation registered +with the kernel crypto API. In this case, the concept described by the +following ASCII art applies too. However, the decomposition of GCM into +the individual sub-components by the kernel crypto API is not done any +more. + +Each block in the following ASCII art is an independent cipher instance +obtained from the kernel crypto API. Each block is accessed by the +caller or by other blocks using the API functions defined by the kernel +crypto API for the cipher implementation type. + +The blocks below indicate the cipher type as well as the specific logic +implemented in the cipher. + +The ASCII art picture also indicates the call structure, i.e. who calls +which component. The arrows point to the invoked block where the caller +uses the API applicable to the cipher type specified for the block. + +:: + + + kernel crypto API | IPSEC Layer + | + +-----------+ | + | | (1) + | aead | <----------------------------------- esp_output + | (seqiv) | ---+ + +-----------+ | + | (2) + +-----------+ | + | | <--+ (2) + | aead | <----------------------------------- esp_input + | (gcm) | ------------+ + +-----------+ | + | (3) | (5) + v v + +-----------+ +-----------+ + | | | | + | skcipher | | ahash | + | (ctr) | ---+ | (ghash) | + +-----------+ | +-----------+ + | + +-----------+ | (4) + | | <--+ + | cipher | + | (aes) | + +-----------+ + + + +The following call sequence is applicable when the IPSEC layer triggers +an encryption operation with the esp_output function. During +configuration, the administrator set up the use of rfc4106(gcm(aes)) as +the cipher for ESP. The following call sequence is now depicted in the +ASCII art above: + +1. esp_output() invokes crypto_aead_encrypt() to trigger an + encryption operation of the AEAD cipher with IV generator. + + In case of GCM, the SEQIV implementation is registered as GIVCIPHER + in crypto_rfc4106_alloc(). + + The SEQIV performs its operation to generate an IV where the core + function is seqiv_geniv(). + +2. Now, SEQIV uses the AEAD API function calls to invoke the associated + AEAD cipher. In our case, during the instantiation of SEQIV, the + cipher handle for GCM is provided to SEQIV. This means that SEQIV + invokes AEAD cipher operations with the GCM cipher handle. + + During instantiation of the GCM handle, the CTR(AES) and GHASH + ciphers are instantiated. The cipher handles for CTR(AES) and GHASH + are retained for later use. + + The GCM implementation is responsible to invoke the CTR mode AES and + the GHASH cipher in the right manner to implement the GCM + specification. + +3. The GCM AEAD cipher type implementation now invokes the SKCIPHER API + with the instantiated CTR(AES) cipher handle. + + During instantiation of the CTR(AES) cipher, the CIPHER type + implementation of AES is instantiated. The cipher handle for AES is + retained. + + That means that the SKCIPHER implementation of CTR(AES) only + implements the CTR block chaining mode. After performing the block + chaining operation, the CIPHER implementation of AES is invoked. + +4. The SKCIPHER of CTR(AES) now invokes the CIPHER API with the AES + cipher handle to encrypt one block. + +5. The GCM AEAD implementation also invokes the GHASH cipher + implementation via the AHASH API. + +When the IPSEC layer triggers the esp_input() function, the same call +sequence is followed with the only difference that the operation starts +with step (2). + +Generic Block Cipher Structure +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Generic block ciphers follow the same concept as depicted with the ASCII +art picture above. + +For example, CBC(AES) is implemented with cbc.c, and aes-generic.c. The +ASCII art picture above applies as well with the difference that only +step (4) is used and the SKCIPHER block chaining mode is CBC. + +Generic Keyed Message Digest Structure +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Keyed message digest implementations again follow the same concept as +depicted in the ASCII art picture above. + +For example, HMAC(SHA256) is implemented with hmac.c and +sha256_generic.c. The following ASCII art illustrates the +implementation: + +:: + + + kernel crypto API | Caller + | + +-----------+ (1) | + | | <------------------ some_function + | ahash | + | (hmac) | ---+ + +-----------+ | + | (2) + +-----------+ | + | | <--+ + | shash | + | (sha256) | + +-----------+ + + + +The following call sequence is applicable when a caller triggers an HMAC +operation: + +1. The AHASH API functions are invoked by the caller. The HMAC + implementation performs its operation as needed. + + During initialization of the HMAC cipher, the SHASH cipher type of + SHA256 is instantiated. The cipher handle for the SHA256 instance is + retained. + + At one time, the HMAC implementation requires a SHA256 operation + where the SHA256 cipher handle is used. + +2. The HMAC instance now invokes the SHASH API with the SHA256 cipher + handle to calculate the message digest. diff --git a/Documentation/crypto/devel-algos.rst b/Documentation/crypto/devel-algos.rst new file mode 100644 index 000000000000..66f50d32dcec --- /dev/null +++ b/Documentation/crypto/devel-algos.rst @@ -0,0 +1,247 @@ +Developing Cipher Algorithms +============================ + +Registering And Unregistering Transformation +-------------------------------------------- + +There are three distinct types of registration functions in the Crypto +API. One is used to register a generic cryptographic transformation, +while the other two are specific to HASH transformations and +COMPRESSion. We will discuss the latter two in a separate chapter, here +we will only look at the generic ones. + +Before discussing the register functions, the data structure to be +filled with each, struct crypto_alg, must be considered -- see below +for a description of this data structure. + +The generic registration functions can be found in +include/linux/crypto.h and their definition can be seen below. The +former function registers a single transformation, while the latter +works on an array of transformation descriptions. The latter is useful +when registering transformations in bulk, for example when a driver +implements multiple transformations. + +:: + + int crypto_register_alg(struct crypto_alg *alg); + int crypto_register_algs(struct crypto_alg *algs, int count); + + +The counterparts to those functions are listed below. + +:: + + int crypto_unregister_alg(struct crypto_alg *alg); + int crypto_unregister_algs(struct crypto_alg *algs, int count); + + +Notice that both registration and unregistration functions do return a +value, so make sure to handle errors. A return code of zero implies +success. Any return code < 0 implies an error. + +The bulk registration/unregistration functions register/unregister each +transformation in the given array of length count. They handle errors as +follows: + +- crypto_register_algs() succeeds if and only if it successfully + registers all the given transformations. If an error occurs partway + through, then it rolls back successful registrations before returning + the error code. Note that if a driver needs to handle registration + errors for individual transformations, then it will need to use the + non-bulk function crypto_register_alg() instead. + +- crypto_unregister_algs() tries to unregister all the given + transformations, continuing on error. It logs errors and always + returns zero. + +Single-Block Symmetric Ciphers [CIPHER] +--------------------------------------- + +Example of transformations: aes, arc4, ... + +This section describes the simplest of all transformation +implementations, that being the CIPHER type used for symmetric ciphers. +The CIPHER type is used for transformations which operate on exactly one +block at a time and there are no dependencies between blocks at all. + +Registration specifics +~~~~~~~~~~~~~~~~~~~~~~ + +The registration of [CIPHER] algorithm is specific in that struct +crypto_alg field .cra_type is empty. The .cra_u.cipher has to be +filled in with proper callbacks to implement this transformation. + +See struct cipher_alg below. + +Cipher Definition With struct cipher_alg +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Struct cipher_alg defines a single block cipher. + +Here are schematics of how these functions are called when operated from +other part of the kernel. Note that the .cia_setkey() call might happen +before or after any of these schematics happen, but must not happen +during any of these are in-flight. + +:: + + KEY ---. PLAINTEXT ---. + v v + .cia_setkey() -> .cia_encrypt() + | + '-----> CIPHERTEXT + + +Please note that a pattern where .cia_setkey() is called multiple times +is also valid: + +:: + + + KEY1 --. PLAINTEXT1 --. KEY2 --. PLAINTEXT2 --. + v v v v + .cia_setkey() -> .cia_encrypt() -> .cia_setkey() -> .cia_encrypt() + | | + '---> CIPHERTEXT1 '---> CIPHERTEXT2 + + +Multi-Block Ciphers +------------------- + +Example of transformations: cbc(aes), ecb(arc4), ... + +This section describes the multi-block cipher transformation +implementations. The multi-block ciphers are used for transformations +which operate on scatterlists of data supplied to the transformation +functions. They output the result into a scatterlist of data as well. + +Registration Specifics +~~~~~~~~~~~~~~~~~~~~~~ + +The registration of multi-block cipher algorithms is one of the most +standard procedures throughout the crypto API. + +Note, if a cipher implementation requires a proper alignment of data, +the caller should use the functions of crypto_skcipher_alignmask() to +identify a memory alignment mask. The kernel crypto API is able to +process requests that are unaligned. This implies, however, additional +overhead as the kernel crypto API needs to perform the realignment of +the data which may imply moving of data. + +Cipher Definition With struct blkcipher_alg and ablkcipher_alg +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Struct blkcipher_alg defines a synchronous block cipher whereas struct +ablkcipher_alg defines an asynchronous block cipher. + +Please refer to the single block cipher description for schematics of +the block cipher usage. + +Specifics Of Asynchronous Multi-Block Cipher +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are a couple of specifics to the asynchronous interface. + +First of all, some of the drivers will want to use the Generic +ScatterWalk in case the hardware needs to be fed separate chunks of the +scatterlist which contains the plaintext and will contain the +ciphertext. Please refer to the ScatterWalk interface offered by the +Linux kernel scatter / gather list implementation. + +Hashing [HASH] +-------------- + +Example of transformations: crc32, md5, sha1, sha256,... + +Registering And Unregistering The Transformation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are multiple ways to register a HASH transformation, depending on +whether the transformation is synchronous [SHASH] or asynchronous +[AHASH] and the amount of HASH transformations we are registering. You +can find the prototypes defined in include/crypto/internal/hash.h: + +:: + + int crypto_register_ahash(struct ahash_alg *alg); + + int crypto_register_shash(struct shash_alg *alg); + int crypto_register_shashes(struct shash_alg *algs, int count); + + +The respective counterparts for unregistering the HASH transformation +are as follows: + +:: + + int crypto_unregister_ahash(struct ahash_alg *alg); + + int crypto_unregister_shash(struct shash_alg *alg); + int crypto_unregister_shashes(struct shash_alg *algs, int count); + + +Cipher Definition With struct shash_alg and ahash_alg +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Here are schematics of how these functions are called when operated from +other part of the kernel. Note that the .setkey() call might happen +before or after any of these schematics happen, but must not happen +during any of these are in-flight. Please note that calling .init() +followed immediately by .finish() is also a perfectly valid +transformation. + +:: + + I) DATA -----------. + v + .init() -> .update() -> .final() ! .update() might not be called + ^ | | at all in this scenario. + '----' '---> HASH + + II) DATA -----------.-----------. + v v + .init() -> .update() -> .finup() ! .update() may not be called + ^ | | at all in this scenario. + '----' '---> HASH + + III) DATA -----------. + v + .digest() ! The entire process is handled + | by the .digest() call. + '---------------> HASH + + +Here is a schematic of how the .export()/.import() functions are called +when used from another part of the kernel. + +:: + + KEY--. DATA--. + v v ! .update() may not be called + .setkey() -> .init() -> .update() -> .export() at all in this scenario. + ^ | | + '-----' '--> PARTIAL_HASH + + ----------- other transformations happen here ----------- + + PARTIAL_HASH--. DATA1--. + v v + .import -> .update() -> .final() ! .update() may not be called + ^ | | at all in this scenario. + '----' '--> HASH1 + + PARTIAL_HASH--. DATA2-. + v v + .import -> .finup() + | + '---------------> HASH2 + + +Specifics Of Asynchronous HASH Transformation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Some of the drivers will want to use the Generic ScatterWalk in case the +implementation needs to be fed separate chunks of the scatterlist which +contains the input data. The buffer containing the resulting hash will +always be properly aligned to .cra_alignmask so there is no need to +worry about this. diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst new file mode 100644 index 000000000000..94c4786f2573 --- /dev/null +++ b/Documentation/crypto/index.rst @@ -0,0 +1,24 @@ +======================= +Linux Kernel Crypto API +======================= + +:Author: Stephan Mueller +:Author: Marek Vasut + +This documentation outlines the Linux kernel crypto API with its +concepts, details about developing cipher implementations, employment of the API +for cryptographic use cases, as well as programming examples. + +.. class:: toc-title + + Table of contents + +.. toctree:: + :maxdepth: 2 + + intro + architecture + devel-algos + userspace-if + api + api-samples diff --git a/Documentation/crypto/intro.rst b/Documentation/crypto/intro.rst new file mode 100644 index 000000000000..9aa89ebbfba9 --- /dev/null +++ b/Documentation/crypto/intro.rst @@ -0,0 +1,74 @@ +Kernel Crypto API Interface Specification +========================================= + +Introduction +------------ + +The kernel crypto API offers a rich set of cryptographic ciphers as well +as other data transformation mechanisms and methods to invoke these. +This document contains a description of the API and provides example +code. + +To understand and properly use the kernel crypto API a brief explanation +of its structure is given. Based on the architecture, the API can be +separated into different components. Following the architecture +specification, hints to developers of ciphers are provided. Pointers to +the API function call documentation are given at the end. + +The kernel crypto API refers to all algorithms as "transformations". +Therefore, a cipher handle variable usually has the name "tfm". Besides +cryptographic operations, the kernel crypto API also knows compression +transformations and handles them the same way as ciphers. + +The kernel crypto API serves the following entity types: + +- consumers requesting cryptographic services + +- data transformation implementations (typically ciphers) that can be + called by consumers using the kernel crypto API + +This specification is intended for consumers of the kernel crypto API as +well as for developers implementing ciphers. This API specification, +however, does not discuss all API calls available to data transformation +implementations (i.e. implementations of ciphers and other +transformations (such as CRC or even compression algorithms) that can +register with the kernel crypto API). + +Note: The terms "transformation" and cipher algorithm are used +interchangeably. + +Terminology +----------- + +The transformation implementation is an actual code or interface to +hardware which implements a certain transformation with precisely +defined behavior. + +The transformation object (TFM) is an instance of a transformation +implementation. There can be multiple transformation objects associated +with a single transformation implementation. Each of those +transformation objects is held by a crypto API consumer or another +transformation. Transformation object is allocated when a crypto API +consumer requests a transformation implementation. The consumer is then +provided with a structure, which contains a transformation object (TFM). + +The structure that contains transformation objects may also be referred +to as a "cipher handle". Such a cipher handle is always subject to the +following phases that are reflected in the API calls applicable to such +a cipher handle: + +1. Initialization of a cipher handle. + +2. Execution of all intended cipher operations applicable for the handle + where the cipher handle must be furnished to every API call. + +3. Destruction of a cipher handle. + +When using the initialization API calls, a cipher handle is created and +returned to the consumer. Therefore, please refer to all initialization +API calls that refer to the data structure type a consumer is expected +to receive and subsequently to use. The initialization API calls have +all the same naming conventions of crypto_alloc\*. + +The transformation context is private data associated with the +transformation object. diff --git a/Documentation/crypto/userspace-if.rst b/Documentation/crypto/userspace-if.rst new file mode 100644 index 000000000000..de5a72e32bc9 --- /dev/null +++ b/Documentation/crypto/userspace-if.rst @@ -0,0 +1,387 @@ +User Space Interface +==================== + +Introduction +------------ + +The concepts of the kernel crypto API visible to kernel space is fully +applicable to the user space interface as well. Therefore, the kernel +crypto API high level discussion for the in-kernel use cases applies +here as well. + +The major difference, however, is that user space can only act as a +consumer and never as a provider of a transformation or cipher +algorithm. + +The following covers the user space interface exported by the kernel +crypto API. A working example of this description is libkcapi that can +be obtained from [1]. That library can be used by user space +applications that require cryptographic services from the kernel. + +Some details of the in-kernel kernel crypto API aspects do not apply to +user space, however. This includes the difference between synchronous +and asynchronous invocations. The user space API call is fully +synchronous. + +[1] http://www.chronox.de/libkcapi.html + +User Space API General Remarks +------------------------------ + +The kernel crypto API is accessible from user space. Currently, the +following ciphers are accessible: + +- Message digest including keyed message digest (HMAC, CMAC) + +- Symmetric ciphers + +- AEAD ciphers + +- Random Number Generators + +The interface is provided via socket type using the type AF_ALG. In +addition, the setsockopt option type is SOL_ALG. In case the user space +header files do not export these flags yet, use the following macros: + +:: + + #ifndef AF_ALG + #define AF_ALG 38 + #endif + #ifndef SOL_ALG + #define SOL_ALG 279 + #endif + + +A cipher is accessed with the same name as done for the in-kernel API +calls. This includes the generic vs. unique naming schema for ciphers as +well as the enforcement of priorities for generic names. + +To interact with the kernel crypto API, a socket must be created by the +user space application. User space invokes the cipher operation with the +send()/write() system call family. The result of the cipher operation is +obtained with the read()/recv() system call family. + +The following API calls assume that the socket descriptor is already +opened by the user space application and discusses only the kernel +crypto API specific invocations. + +To initialize the socket interface, the following sequence has to be +performed by the consumer: + +1. Create a socket of type AF_ALG with the struct sockaddr_alg + parameter specified below for the different cipher types. + +2. Invoke bind with the socket descriptor + +3. Invoke accept with the socket descriptor. The accept system call + returns a new file descriptor that is to be used to interact with the + particular cipher instance. When invoking send/write or recv/read + system calls to send data to the kernel or obtain data from the + kernel, the file descriptor returned by accept must be used. + +In-place Cipher operation +------------------------- + +Just like the in-kernel operation of the kernel crypto API, the user +space interface allows the cipher operation in-place. That means that +the input buffer used for the send/write system call and the output +buffer used by the read/recv system call may be one and the same. This +is of particular interest for symmetric cipher operations where a +copying of the output data to its final destination can be avoided. + +If a consumer on the other hand wants to maintain the plaintext and the +ciphertext in different memory locations, all a consumer needs to do is +to provide different memory pointers for the encryption and decryption +operation. + +Message Digest API +------------------ + +The message digest type to be used for the cipher operation is selected +when invoking the bind syscall. bind requires the caller to provide a +filled struct sockaddr data structure. This data structure must be +filled as follows: + +:: + + struct sockaddr_alg sa = { + .salg_family = AF_ALG, + .salg_type = "hash", /* this selects the hash logic in the kernel */ + .salg_name = "sha1" /* this is the cipher name */ + }; + + +The salg_type value "hash" applies to message digests and keyed message +digests. Though, a keyed message digest is referenced by the appropriate +salg_name. Please see below for the setsockopt interface that explains +how the key can be set for a keyed message digest. + +Using the send() system call, the application provides the data that +should be processed with the message digest. The send system call allows +the following flags to be specified: + +- MSG_MORE: If this flag is set, the send system call acts like a + message digest update function where the final hash is not yet + calculated. If the flag is not set, the send system call calculates + the final message digest immediately. + +With the recv() system call, the application can read the message digest +from the kernel crypto API. If the buffer is too small for the message +digest, the flag MSG_TRUNC is set by the kernel. + +In order to set a message digest key, the calling application must use +the setsockopt() option of ALG_SET_KEY. If the key is not set the HMAC +operation is performed without the initial HMAC state change caused by +the key. + +Symmetric Cipher API +-------------------- + +The operation is very similar to the message digest discussion. During +initialization, the struct sockaddr data structure must be filled as +follows: + +:: + + struct sockaddr_alg sa = { + .salg_family = AF_ALG, + .salg_type = "skcipher", /* this selects the symmetric cipher */ + .salg_name = "cbc(aes)" /* this is the cipher name */ + }; + + +Before data can be sent to the kernel using the write/send system call +family, the consumer must set the key. The key setting is described with +the setsockopt invocation below. + +Using the sendmsg() system call, the application provides the data that +should be processed for encryption or decryption. In addition, the IV is +specified with the data structure provided by the sendmsg() system call. + +The sendmsg system call parameter of struct msghdr is embedded into the +struct cmsghdr data structure. See recv(2) and cmsg(3) for more +information on how the cmsghdr data structure is used together with the +send/recv system call family. That cmsghdr data structure holds the +following information specified with a separate header instances: + +- specification of the cipher operation type with one of these flags: + + - ALG_OP_ENCRYPT - encryption of data + + - ALG_OP_DECRYPT - decryption of data + +- specification of the IV information marked with the flag ALG_SET_IV + +The send system call family allows the following flag to be specified: + +- MSG_MORE: If this flag is set, the send system call acts like a + cipher update function where more input data is expected with a + subsequent invocation of the send system call. + +Note: The kernel reports -EINVAL for any unexpected data. The caller +must make sure that all data matches the constraints given in +/proc/crypto for the selected cipher. + +With the recv() system call, the application can read the result of the +cipher operation from the kernel crypto API. The output buffer must be +at least as large as to hold all blocks of the encrypted or decrypted +data. If the output data size is smaller, only as many blocks are +returned that fit into that output buffer size. + +AEAD Cipher API +--------------- + +The operation is very similar to the symmetric cipher discussion. During +initialization, the struct sockaddr data structure must be filled as +follows: + +:: + + struct sockaddr_alg sa = { + .salg_family = AF_ALG, + .salg_type = "aead", /* this selects the symmetric cipher */ + .salg_name = "gcm(aes)" /* this is the cipher name */ + }; + + +Before data can be sent to the kernel using the write/send system call +family, the consumer must set the key. The key setting is described with +the setsockopt invocation below. + +In addition, before data can be sent to the kernel using the write/send +system call family, the consumer must set the authentication tag size. +To set the authentication tag size, the caller must use the setsockopt +invocation described below. + +Using the sendmsg() system call, the application provides the data that +should be processed for encryption or decryption. In addition, the IV is +specified with the data structure provided by the sendmsg() system call. + +The sendmsg system call parameter of struct msghdr is embedded into the +struct cmsghdr data structure. See recv(2) and cmsg(3) for more +information on how the cmsghdr data structure is used together with the +send/recv system call family. That cmsghdr data structure holds the +following information specified with a separate header instances: + +- specification of the cipher operation type with one of these flags: + + - ALG_OP_ENCRYPT - encryption of data + + - ALG_OP_DECRYPT - decryption of data + +- specification of the IV information marked with the flag ALG_SET_IV + +- specification of the associated authentication data (AAD) with the + flag ALG_SET_AEAD_ASSOCLEN. The AAD is sent to the kernel together + with the plaintext / ciphertext. See below for the memory structure. + +The send system call family allows the following flag to be specified: + +- MSG_MORE: If this flag is set, the send system call acts like a + cipher update function where more input data is expected with a + subsequent invocation of the send system call. + +Note: The kernel reports -EINVAL for any unexpected data. The caller +must make sure that all data matches the constraints given in +/proc/crypto for the selected cipher. + +With the recv() system call, the application can read the result of the +cipher operation from the kernel crypto API. The output buffer must be +at least as large as defined with the memory structure below. If the +output data size is smaller, the cipher operation is not performed. + +The authenticated decryption operation may indicate an integrity error. +Such breach in integrity is marked with the -EBADMSG error code. + +AEAD Memory Structure +~~~~~~~~~~~~~~~~~~~~~ + +The AEAD cipher operates with the following information that is +communicated between user and kernel space as one data stream: + +- plaintext or ciphertext + +- associated authentication data (AAD) + +- authentication tag + +The sizes of the AAD and the authentication tag are provided with the +sendmsg and setsockopt calls (see there). As the kernel knows the size +of the entire data stream, the kernel is now able to calculate the right +offsets of the data components in the data stream. + +The user space caller must arrange the aforementioned information in the +following order: + +- AEAD encryption input: AAD \|\| plaintext + +- AEAD decryption input: AAD \|\| ciphertext \|\| authentication tag + +The output buffer the user space caller provides must be at least as +large to hold the following data: + +- AEAD encryption output: ciphertext \|\| authentication tag + +- AEAD decryption output: plaintext + +Random Number Generator API +--------------------------- + +Again, the operation is very similar to the other APIs. During +initialization, the struct sockaddr data structure must be filled as +follows: + +:: + + struct sockaddr_alg sa = { + .salg_family = AF_ALG, + .salg_type = "rng", /* this selects the symmetric cipher */ + .salg_name = "drbg_nopr_sha256" /* this is the cipher name */ + }; + + +Depending on the RNG type, the RNG must be seeded. The seed is provided +using the setsockopt interface to set the key. For example, the +ansi_cprng requires a seed. The DRBGs do not require a seed, but may be +seeded. + +Using the read()/recvmsg() system calls, random numbers can be obtained. +The kernel generates at most 128 bytes in one call. If user space +requires more data, multiple calls to read()/recvmsg() must be made. + +WARNING: The user space caller may invoke the initially mentioned accept +system call multiple times. In this case, the returned file descriptors +have the same state. + +Zero-Copy Interface +------------------- + +In addition to the send/write/read/recv system call family, the AF_ALG +interface can be accessed with the zero-copy interface of +splice/vmsplice. As the name indicates, the kernel tries to avoid a copy +operation into kernel space. + +The zero-copy operation requires data to be aligned at the page +boundary. Non-aligned data can be used as well, but may require more +operations of the kernel which would defeat the speed gains obtained +from the zero-copy interface. + +The system-interent limit for the size of one zero-copy operation is 16 +pages. If more data is to be sent to AF_ALG, user space must slice the +input into segments with a maximum size of 16 pages. + +Zero-copy can be used with the following code example (a complete +working example is provided with libkcapi): + +:: + + int pipes[2]; + + pipe(pipes); + /* input data in iov */ + vmsplice(pipes[1], iov, iovlen, SPLICE_F_GIFT); + /* opfd is the file descriptor returned from accept() system call */ + splice(pipes[0], NULL, opfd, NULL, ret, 0); + read(opfd, out, outlen); + + +Setsockopt Interface +-------------------- + +In addition to the read/recv and send/write system call handling to send +and retrieve data subject to the cipher operation, a consumer also needs +to set the additional information for the cipher operation. This +additional information is set using the setsockopt system call that must +be invoked with the file descriptor of the open cipher (i.e. the file +descriptor returned by the accept system call). + +Each setsockopt invocation must use the level SOL_ALG. + +The setsockopt interface allows setting the following data using the +mentioned optname: + +- ALG_SET_KEY -- Setting the key. Key setting is applicable to: + + - the skcipher cipher type (symmetric ciphers) + + - the hash cipher type (keyed message digests) + + - the AEAD cipher type + + - the RNG cipher type to provide the seed + +- ALG_SET_AEAD_AUTHSIZE -- Setting the authentication tag size for + AEAD ciphers. For a encryption operation, the authentication tag of + the given size will be generated. For a decryption operation, the + provided ciphertext is assumed to contain an authentication tag of + the given size (see section about AEAD memory layout below). + +User space API example +---------------------- + +Please see [1] for libkcapi which provides an easy-to-use wrapper around +the aforementioned Netlink kernel interface. [1] also contains a test +application that invokes all libkcapi API calls. + +[1] http://www.chronox.de/libkcapi.html diff --git a/Documentation/dev-tools/sparse.rst b/Documentation/dev-tools/sparse.rst index 8c250e8a2105..78aa00a604a0 100644 --- a/Documentation/dev-tools/sparse.rst +++ b/Documentation/dev-tools/sparse.rst @@ -51,13 +51,6 @@ sure that bitwise types don't get mixed up (little-endian vs big-endian vs cpu-endian vs whatever), and there the constant "0" really _is_ special. -__bitwise__ - to be used for relatively compact stuff (gfp_t, etc.) that -is mostly warning-free and is supposed to stay that way. Warnings will -be generated without __CHECK_ENDIAN__. - -__bitwise - noisy stuff; in particular, __le*/__be* are that. We really -don't want to drown in noise unless we'd explicitly asked for it. - Using sparse for lock checking ------------------------------ @@ -109,9 +102,4 @@ be recompiled or not. The latter is a fast way to check the whole tree if you have already built it. The optional make variable CF can be used to pass arguments to sparse. The -build system passes -Wbitwise to sparse automatically. To perform endianness -checks, you may define __CHECK_ENDIAN__:: - - make C=2 CF="-D__CHECK_ENDIAN__" - -These checks are disabled by default as they generate a host of warnings. +build system passes -Wbitwise to sparse automatically. diff --git a/Documentation/device-mapper/delay.txt b/Documentation/device-mapper/delay.txt index a07b5927f4a8..4b1d22a44ce4 100644 --- a/Documentation/device-mapper/delay.txt +++ b/Documentation/device-mapper/delay.txt @@ -16,12 +16,12 @@ Example scripts [[ #!/bin/sh # Create device delaying rw operation for 500ms -echo "0 `blockdev --getsize $1` delay $1 0 500" | dmsetup create delayed +echo "0 `blockdev --getsz $1` delay $1 0 500" | dmsetup create delayed ]] [[ #!/bin/sh # Create device delaying only write operation for 500ms and # splitting reads and writes to different devices $1 $2 -echo "0 `blockdev --getsize $1` delay $1 0 0 $2 0 500" | dmsetup create delayed +echo "0 `blockdev --getsz $1` delay $1 0 0 $2 0 500" | dmsetup create delayed ]] diff --git a/Documentation/device-mapper/dm-crypt.txt b/Documentation/device-mapper/dm-crypt.txt index 6f15fcea9566..ff1f87bf26e8 100644 --- a/Documentation/device-mapper/dm-crypt.txt +++ b/Documentation/device-mapper/dm-crypt.txt @@ -102,7 +102,7 @@ https://gitlab.com/cryptsetup/cryptsetup [[ #!/bin/sh # Create a crypt device using dmsetup -dmsetup create crypt1 --table "0 `blockdev --getsize $1` crypt aes-cbc-essiv:sha256 babebabebabebabebabebabebabebabe 0 $1 0" +dmsetup create crypt1 --table "0 `blockdev --getsz $1` crypt aes-cbc-essiv:sha256 babebabebabebabebabebabebabebabe 0 $1 0" ]] [[ diff --git a/Documentation/device-mapper/linear.txt b/Documentation/device-mapper/linear.txt index d5307d380a45..7cb98d89d3f8 100644 --- a/Documentation/device-mapper/linear.txt +++ b/Documentation/device-mapper/linear.txt @@ -16,15 +16,15 @@ Example scripts [[ #!/bin/sh # Create an identity mapping for a device -echo "0 `blockdev --getsize $1` linear $1 0" | dmsetup create identity +echo "0 `blockdev --getsz $1` linear $1 0" | dmsetup create identity ]] [[ #!/bin/sh # Join 2 devices together -size1=`blockdev --getsize $1` -size2=`blockdev --getsize $2` +size1=`blockdev --getsz $1` +size2=`blockdev --getsz $2` echo "0 $size1 linear $1 0 $size1 $size2 linear $2 0" | dmsetup create joined ]] @@ -44,7 +44,7 @@ if (!defined($dev)) { die("Please specify a device.\n"); } -my $dev_size = `blockdev --getsize $dev`; +my $dev_size = `blockdev --getsz $dev`; my $extents = int($dev_size / $extent_size) - (($dev_size % $extent_size) ? 1 : 0); diff --git a/Documentation/device-mapper/striped.txt b/Documentation/device-mapper/striped.txt index 45f3b91ea4c3..07ec492cceee 100644 --- a/Documentation/device-mapper/striped.txt +++ b/Documentation/device-mapper/striped.txt @@ -37,9 +37,9 @@ if (!$num_devs) { die("Specify at least one device\n"); } -$min_dev_size = `blockdev --getsize $devs[0]`; +$min_dev_size = `blockdev --getsz $devs[0]`; for ($i = 1; $i < $num_devs; $i++) { - my $this_size = `blockdev --getsize $devs[$i]`; + my $this_size = `blockdev --getsz $devs[$i]`; $min_dev_size = ($min_dev_size < $this_size) ? $min_dev_size : $this_size; } diff --git a/Documentation/device-mapper/switch.txt b/Documentation/device-mapper/switch.txt index 424835e57f27..5bd4831db4a8 100644 --- a/Documentation/device-mapper/switch.txt +++ b/Documentation/device-mapper/switch.txt @@ -123,7 +123,7 @@ Assume that you have volumes vg1/switch0 vg1/switch1 vg1/switch2 with the same size. Create a switch device with 64kB region size: - dmsetup create switch --table "0 `blockdev --getsize /dev/vg1/switch0` + dmsetup create switch --table "0 `blockdev --getsz /dev/vg1/switch0` switch 3 128 0 /dev/vg1/switch0 0 /dev/vg1/switch1 0 /dev/vg1/switch2 0" Set mappings for the first 7 entries to point to devices switch0, switch1, diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt new file mode 100644 index 000000000000..7b9a861e9306 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -0,0 +1,20 @@ +System Control and Power Interface (SCPI) Message Protocol +(in addition to the standard binding in [0]) +---------------------------------------------------------- +Required properties + +- compatible : should be "amlogic,meson-gxbb-scpi" + +AMLOGIC SRAM and Shared Memory for SCPI +------------------------------------ + +Required properties: +- compatible : should be "amlogic,meson-gxbb-sram" + +Each sub-node represents the reserved area for SCPI. + +Required sub-node properties: +- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared + memory on Amlogic GXBB SoC. + +[0] Documentation/devicetree/bindings/arm/arm,scpi.txt diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index fcc6f6c10803..9b2b41ab6817 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -17,6 +17,18 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties: Required root node property: compatible: "amlogic,meson-gxbb"; +Boards with the Amlogic Meson GXL S905X SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905x", "amlogic,meson-gxl"; + +Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905d", "amlogic,meson-gxl"; + +Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s912", "amlogic,meson-gxm"; + Board compatible values: - "geniatech,atv1200" (Meson6) - "minix,neo-x8" (Meson8) @@ -28,3 +40,10 @@ Board compatible values: - "hardkernel,odroid-c2" (Meson gxbb) - "amlogic,p200" (Meson gxbb) - "amlogic,p201" (Meson gxbb) + - "amlogic,p212" (Meson gxl s905x) + - "amlogic,p230" (Meson gxl s905d) + - "amlogic,p231" (Meson gxl s905d) + - "amlogic,q200" (Meson gxm s912) + - "amlogic,q201" (Meson gxm s912) + - "nexbox,a95x" (Meson gxbb or Meson gxl s905x) + - "nexbox,a1" (Meson gxm s912) diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index faa4b44572e3..401831973638 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -7,7 +7,10 @@ by Linux to initiate various system control and power operations. Required properties: -- compatible : should be "arm,scpi" +- compatible : should be + * "arm,scpi" : For implementations complying to SCPI v1.0 or above + * "arm,scpi-pre-1.0" : For implementations complying to all + unversioned releases prior to SCPI v1.0 - mboxes: List of phandle and mailbox channel specifiers All the channels reserved by remote SCP firmware for use by SCPI message protocol should be specified in any order @@ -59,18 +62,14 @@ SRAM and Shared Memory for SCPI A small area of SRAM is reserved for SCPI communication between application processors and SCP. -Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno - -The rest of the properties should follow the generic mmio-sram description -found in ../../sram/sram.txt +The properties should follow the generic mmio-sram description found in [3] Each sub-node represents the reserved area for SCPI. Required sub-node properties: - reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms +- compatible : should be "arm,scp-shmem" for Non-secure SRAM based + shared memory Sensor bindings for the sensors based on SCPI Message Protocol -------------------------------------------------------------- @@ -81,11 +80,9 @@ Required properties: - #thermal-sensor-cells: should be set to 1. This property follows the thermal device tree bindings[2]. - Valid cell values are raw identifiers (Sensor - ID) as used by the firmware. Refer to - platform documentation for your - implementation for the IDs to use. For Juno - R0 and Juno R1 refer to [3]. + Valid cell values are raw identifiers (Sensor ID) + as used by the firmware. Refer to platform details + for your implementation for the IDs to use. Power domain bindings for the power domains based on SCPI Message Protocol ------------------------------------------------------------ @@ -112,7 +109,7 @@ Required properties: [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/thermal/thermal.txt -[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html +[3] Documentation/devicetree/bindings/sram/sram.txt [4] Documentation/devicetree/bindings/power/power_domain.txt Example: diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index ab318a56fca2..b6e810c2781a 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -148,11 +148,12 @@ Example: /dts-v1/; #include -#include "skeleton.dtsi" / { model = "ARM RealView PB1176 with device tree"; compatible = "arm,realview-pb1176"; + #address-cells = <1>; + #size-cells = <1>; soc { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index e1f5ad855f14..29737b9b616e 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -225,3 +225,19 @@ required properties: compatible = "atmel,sama5d3-sfr", "syscon"; reg = <0xf0038000 0x60>; }; + +Security Module (SECUMOD) + +The Security Module macrocell provides all necessary secure functions to avoid +voltage, temperature, frequency and mechanical attacks on the chip. It also +embeds secure memories that can be scrambled + +required properties: +- compatible: Should be "atmel,-secumod", "syscon". + can be "sama5d2". +- reg: Should contain registers location and length + + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/ns2.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index c1dcf4cade2e..a1bcfeed5f24 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -178,6 +178,7 @@ nodes to be present and contain the properties described below. "marvell,pj4b" "marvell,sheeva-v5" "nvidia,tegra132-denver" + "nvidia,tegra186-denver" "qcom,krait" "qcom,kryo" "qcom,scorpion" diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index dbbc0952021c..d6ee9c6e1dbb 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings Required root node compatible properties: - compatible = "fsl,ls1021a"; -Freescale LS1021A SoC-specific Device Tree Bindings +Freescale SoC-specific Device Tree Bindings ------------------------------------------- Freescale SCFG @@ -105,7 +105,11 @@ Freescale SCFG configuration and status registers for the chip. Such as getting PEX port status. Required properties: - - compatible: should be "fsl,ls1021a-scfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-scfg", + The following s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg: should contain base address and length of SCFG memory-mapped registers Example: @@ -119,7 +123,11 @@ Freescale DCFG configuration and status for the device. Such as setting the secondary core start address and release the secondary core from holdoff and startup. Required properties: - - compatible: should be "fsl,ls1021a-dcfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-dcfg", + The following s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg : should contain base address and length of DCFG memory-mapped registers Example: @@ -131,6 +139,10 @@ Example: Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ---------------------------------------------------------------- +LS1043A SoC +Required root node properties: + - compatible = "fsl,ls1043a"; + LS1043A ARMv8 based RDB Board Required root node properties: - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; @@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board Required root node properties: - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; +LS1046A SoC +Required root node properties: + - compatible = "fsl,ls1046a"; + +LS1046A ARMv8 based QDS Board +Required root node properties: + - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; + +LS1046A ARMv8 based RDB Board +Required root node properties: + - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; + +LS2080A SoC +Required root node properties: + - compatible = "fsl,ls2080a"; + LS2080A ARMv8 based Simulator model Required root node properties: - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 3f81575aa6be..7df79a715611 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -28,6 +28,10 @@ HiP06 D03 Board Required root node properties: - compatible = "hisilicon,hip06-d03"; +HiP07 D05 Board +Required root node properties: + - compatible = "hisilicon,hip07-d05"; + Hisilicon system controller Required properties: diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt new file mode 100644 index 000000000000..2ace8696bbee --- /dev/null +++ b/Documentation/devicetree/bindings/arm/juno,scpi.txt @@ -0,0 +1,26 @@ +System Control and Power Interface (SCPI) Message Protocol +(in addition to the standard binding in [0]) + +Juno SRAM and Shared Memory for SCPI +------------------------------------ + +Required properties: +- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM + +Each sub-node represents the reserved area for SCPI. + +Required sub-node properties: +- reg : The base offset and size of the reserved area with the SRAM +- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based + shared memory on Juno platforms + +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +Required properties: +- compatible : should be "arm,scpi-sensors". +- #thermal-sensor-cells: should be set to 1. + For Juno R0 and Juno R1 refer to [1] for the + sensor identifiers + +[0] Documentation/devicetree/bindings/arm/arm,scpi.txt +[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt new file mode 100644 index 000000000000..31f5f9a104cc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt @@ -0,0 +1,81 @@ +Texas Instruments System Control Interface (TI-SCI) Message Protocol +-------------------------------------------------------------------- + +Texas Instrument's processors including those belonging to Keystone generation +of processors have separate hardware entity which is now responsible for the +management of the System on Chip (SoC) system. These include various system +level functions as well. + +An example of such an SoC is K2G, which contains the system control hardware +block called Power Management Micro Controller (PMMC). This hardware block is +initialized early into boot process and provides services to Operating Systems +on multiple processors including ones running Linux. + +See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. + +TI-SCI controller Device Node: +============================= + +The TI-SCI node describes the Texas Instrument's System Controller entity node. +This parent node may optionally have additional children nodes which describe +specific functionality such as clocks, power domain, reset or additional +functionality as may be required for the SoC. This hierarchy also describes the +relationship between the TI-SCI parent node to the child node. + +Required properties: +------------------- +- compatible: should be "ti,k2g-sci" +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details +about the generic mailbox controller and client driver bindings. Also see +Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical +controller that is used to communicate with this System controllers. + +Optional Properties: +------------------- +- reg-names: + debug_messages - Map the Debug message region +- reg: register space corresponding to the debug_messages +- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot + +Example (K2G): +------------- + pmmc: pmmc { + compatible = "ti,k2g-sci"; + mbox-names = "rx", "tx"; + mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>, + <&msgmgr &msgmgr_proxy_pmmc_tx>; + reg-names = "debug_messages"; + reg = <0x02921800 0x800>; + }; + + +TI-SCI Client Device Node: +========================= + +Client nodes are maintained as children of the relevant TI-SCI device node. + +Example (K2G): +------------- + pmmc: pmmc { + compatible = "ti,k2g-sci"; + ... + + my_clk_node: clk_node { + ... + ... + }; + + my_pd_node: pd_node { + ... + ... + }; + }; diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index f53e2ee65e35..05f95c3ed7d4 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -86,6 +86,9 @@ SoCs: - DRA722 compatible = "ti,dra722", "ti,dra72", "ti,dra7" +- DRA718 + compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" + - AM5728 compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" @@ -175,12 +178,18 @@ Boards: - AM5728 IDK compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" +- AM5718 IDK + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7" + - DRA742 EVM: Software Development Board for DRA742 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" - DRA722 EVM: Software Development Board for DRA722 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" +- DRA718 EVM: Software Development Board for DRA718 + compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" + - DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt index b9e49711ba05..ac64e60f99f1 100644 --- a/Documentation/devicetree/bindings/arm/oxnas.txt +++ b/Documentation/devicetree/bindings/arm/oxnas.txt @@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties: Required root node property: compatible: "oxsemi,ox810se" +Boards with the OX820 SoC shall have the following properties: + Required root node property: + compatible: "oxsemi,ox820" + Board compatible values: - "wd,mbwe" (OX810SE) + - "cloudengines,pogoplugv3" (OX820) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 3e24518c6678..028d16e72186 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -21,7 +21,10 @@ The 'SoC' element must be one of the following strings: apq8096 msm8916 msm8974 + msm8992 + msm8994 msm8996 + mdm9615 The 'board' element must be one of the following strings: diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 55f388f954de..cc4ace6397ab 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -25,6 +25,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "radxa,rock2-square", "rockchip,rk3288"; +- Rikomagic MK808 v1 board: + Required root node properties: + - compatible = "rikomagic,mk808", "rockchip,rk3066a"; + - Firefly Firefly-RK3288 board: Required root node properties: - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; @@ -99,6 +103,18 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mqmaker,miqi", "rockchip,rk3288"; +- Rockchip PX3 Evaluation board: + Required root node properties: + - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + +- Rockchip PX5 Evaluation board: + Required root node properties: + - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + +- Rockchip RK1108 Evaluation board + Required root node properties: + - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + - Rockchip RK3368 evb: Required root node properties: - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 0ea7f14ef294..3c551894f621 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -15,6 +15,8 @@ Required root node properties: - "samsung,xyref5260" - for Exynos5260-based Samsung board. - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. + - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. + - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - "samsung,sd5v1" - for Exynos5440-based Samsung board. - "samsung,ssdk5440" - for Exynos5440-based Samsung board. @@ -22,6 +24,9 @@ Required root node properties: * FriendlyARM - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM TINY4412 board. + * TOPEET + - "topeet,itop4412-elite" - for Exynos4412-based TOPEET + Elite base board. * Google - "google,pi" - for Exynos5800-based Google Peach Pi diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 2f0b7169f132..253bf9b86690 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -13,6 +13,10 @@ SoCs: compatible = "renesas,r8a73a4" - R-Mobile A1 (R8A77400) compatible = "renesas,r8a7740" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" + - RZ/G1E (R8A77450) + compatible = "renesas,r8a7745" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790) @@ -35,7 +39,7 @@ SoCs: Boards: - - Alt + - Alt (RTP0RC7794SEB00010S) compatible = "renesas,alt", "renesas,r8a7794" - APE6-EVM compatible = "renesas,ape6evm", "renesas,r8a73a4" @@ -47,9 +51,9 @@ Boards: compatible = "renesas,bockw", "renesas,r8a7778" - Genmai (RTK772100BC00000BR) compatible = "renesas,genmai", "renesas,r7s72100" - - Gose + - Gose (RTP0RC7793SEB00010S) compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (RTP0RC7795SKB00010S) + - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S) compatible = "renesas,h3ulcb", "renesas,r8a7795"; - Henninger compatible = "renesas,henninger", "renesas,r8a7791" @@ -61,7 +65,9 @@ Boards: compatible = "renesas,kzm9g", "renesas,sh73a0" - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" - - Marzen + - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S) + compatible = "renesas,m3ulcb", "renesas,r8a7796"; + - Marzen (R0P7779A00010S) compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) compatible = "renesas,porter", "renesas,r8a7791" @@ -73,5 +79,27 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" + - SK-RZG1E (YR8A77450S000BE) + compatible = "renesas,sk-rzg1e", "renesas,r8a7745" + - SK-RZG1M (YR8A77430S000BE) + compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Wheat compatible = "renesas,wheat", "renesas,r8a7792" + + +Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC +product and revision information. If present, a device node for this register +should be added. + +Required properties: + - compatible: Must be "renesas,prr". + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 3975d0a0e4c2..4d6467cc2aa2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,4 +14,5 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h3 allwinner,sun9i-a80 + allwinner,sun50i-a64 nextthing,gr8 diff --git a/Documentation/devicetree/bindings/arm/swir.txt b/Documentation/devicetree/bindings/arm/swir.txt new file mode 100644 index 000000000000..042be73a95d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/swir.txt @@ -0,0 +1,12 @@ +Sierra Wireless Modules device tree bindings +-------------------------------------------- + +Supported Modules : + - WP8548 : Includes MDM9615 and PM8018 in a module + +Sierra Wireless modules shall have the following properties : + Required root node property + - compatible: "swir,wp8548" for the WP8548 CF3 Module + +Board compatible values: + - "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 032a7606b862..fc33ca01e9ba 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where - chip could be ls1021a, ls2080a, ls1043a etc. + chip could be ls1021a, ls1043a, ls1046a, ls2080a etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt index e1d01df8e3c1..909c9935360d 100644 --- a/Documentation/devicetree/bindings/ata/ahci-st.txt +++ b/Documentation/devicetree/bindings/ata/ahci-st.txt @@ -18,21 +18,6 @@ Optional properties: Example: - /* Example for stih416 */ - sata0: sata@fe380000 { - compatible = "st,ahci"; - reg = <0xfe380000 0x1000>; - interrupts = ; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ahci_clk"; - }; - /* Example for stih407 family silicon */ sata0: sata@9b20000 { compatible = "st,ahci"; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt new file mode 100644 index 000000000000..83b0e54f727c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt @@ -0,0 +1,132 @@ +Device tree bindings for NVIDIA Tegra Generic Memory Interface bus + +The Generic Memory Interface bus enables memory transfers between internal and +external memory. Can be used to attach various high speed devices such as +synchronous/asynchronous NOR, FPGA, UARTS and more. + +The actual devices are instantiated from the child nodes of a GMI node. + +Required properties: + - compatible : Should contain one of the following: + For Tegra20 must contain "nvidia,tegra20-gmi". + For Tegra30 must contain "nvidia,tegra30-gmi". + - reg: Should contain GMI controller registers location and length. + - clocks: Must contain an entry for each entry in clock-names. + - clock-names: Must include the following entries: "gmi" + - resets : Must contain an entry for each entry in reset-names. + - reset-names : Must include the following entries: "gmi" + - #address-cells: The number of cells used to represent physical base + addresses in the GMI address space. Should be 2. + - #size-cells: The number of cells used to represent the size of an address + range in the GMI address space. Should be 1. + - ranges: Must be set up to reflect the memory layout with three integer values + for each chip-select line in use (only one entry is supported, see below + comments): + + +Note that the GMI controller does not have any internal chip-select address +decoding, because of that chip-selects either need to be managed via software +or by employing external chip-select decoding logic. + +If external chip-select logic is used to support multiple devices it is assumed +that the devices use the same timing and so are probably the same type. It also +assumes that they can fit in the 256MB address range. In this case only one +child device is supported which represents the active chip-select line, see +examples for more insight. + +The chip-select number is decoded from the child nodes second address cell of +'ranges' property, if 'ranges' property is not present or empty chip-select will +then be decoded from the first cell of the 'reg' property. + +Optional child cs node properties: + + - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit. + - nvidia,snor-mux-mode: Enable address/data MUX mode. + - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data. + If omitted it will be asserted with data. + - nvidia,snor-rdy-active-high: RDY signal is active high + - nvidia,snor-adv-active-high: ADV signal is active high + - nvidia,snor-oe-active-high: WE/OE signal is active high + - nvidia,snor-cs-active-high: CS signal is active high + + Note that there is some special handling for the timing values. + From Tegra TRM: + Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1 + + - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the + bus. Valid values are 0-15, default is 1 + - nvidia,snor-hold-width: Number of cycles CE stays asserted after the + de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N + (in case of MASTER Request). Valid values are 0-15, default is 1 + - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted. + Valid values are 0-15, default is 1. + - nvidia,snor-ce-width: Number of cycles before CE is asserted. + Valid values are 0-15, default is 4 + - nvidia,snor-we-width: Number of cycles during which WE stays asserted. + Valid values are 0-15, default is 1 + - nvidia,snor-oe-width: Number of cycles during which OE stays asserted. + Valid values are 0-255, default is 1 + - nvidia,snor-wait-width: Number of cycles before READY is asserted. + Valid values are 0-255, default is 3 + +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the +controllers with a simple-bus node since they are all connected to the same +chip-select (CS4), in this example external address decoding is provided: + +gmi@70090000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + ranges = <4 0 0xd0000000 0xfffffff>; + + status = "okay"; + + bus@4,0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 4 0 0x40100>; + + nvidia,snor-mux-mode; + nvidia,snor-adv-active-high; + + can@0 { + reg = <0 0x100>; + ... + }; + + can@40000 { + reg = <0x40000 0x100>; + ... + }; + }; +}; + +Example with one SJA1000 CAN controller connected to the GMI bus +on CS4: + +gmi@70090000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + ranges = <4 0 0xd0000000 0xfffffff>; + + status = "okay"; + + can@4,0 { + reg = <4 0 0x100>; + nvidia,snor-mux-mode; + nvidia,snor-adv-active-high; + ... + }; +}; diff --git a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt new file mode 100644 index 000000000000..72daefc6b4a1 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt @@ -0,0 +1,20 @@ +* Device tree bindings for Texas Instruments da8xx master peripheral + priority driver + +DA8XX SoCs feature a set of registers allowing to change the priority of all +peripherals classified as masters. + +Documentation: +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf + +Required properties: + +- compatible: "ti,da850-mstpri" - for da850 based boards +- reg: offset and length of the mstpri registers + +Example for da850-lcdk is shown below. + +mstpri { + compatible = "ti,da850-mstpri"; + reg = <0x14110 0x0c>; +}; diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.txt b/Documentation/devicetree/bindings/clock/imx31-clock.txt index 19df842c694f..8163d565f697 100644 --- a/Documentation/devicetree/bindings/clock/imx31-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx31-clock.txt @@ -77,7 +77,7 @@ Examples: clks: ccm@53f80000{ compatible = "fsl,imx31-ccm"; reg = <0x53f80000 0x4000>; - interrupts = <0 31 0x04 0 53 0x04>; + interrupts = <31>, <53>; #clock-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 16a3ec433119..df9cb5ac5f72 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -32,6 +32,9 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" + * "fsl,ls1043a-clockgen" + * "fsl,ls1046a-clockgen" + * "fsl,ls2080a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index adeca34c5a33..10a425f451fc 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -123,6 +123,9 @@ PROPERTIES EXAMPLE + +iMX6QDL/SX requires four clocks + crypto@300000 { compatible = "fsl,sec-v4.0"; fsl,sec-era = <2>; @@ -139,6 +142,23 @@ EXAMPLE clock-names = "mem", "aclk", "ipg", "emi_slow"; }; + +iMX6UL does only require three clocks + + crypto: caam@2140000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + + clocks = <&clks IMX6UL_CLK_CAAM_MEM>, + <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_IPG>; + clock-names = "mem", "aclk", "ipg"; + }; + ===================================================================== Job Ring (JR) Node diff --git a/Documentation/devicetree/bindings/dma/nbpfaxi.txt b/Documentation/devicetree/bindings/dma/nbpfaxi.txt index d5e2522b9ec1..d2e1e62e346a 100644 --- a/Documentation/devicetree/bindings/dma/nbpfaxi.txt +++ b/Documentation/devicetree/bindings/dma/nbpfaxi.txt @@ -23,6 +23,14 @@ Required properties #define NBPF_SLAVE_RQ_LEVEL 4 Optional properties: +- max-burst-mem-read: limit burst size for memory reads + (DMA_MEM_TO_MEM/DMA_MEM_TO_DEV) to this value, specified in bytes, rather + than using the maximum burst size allowed by the hardware's buffer size. +- max-burst-mem-write: limit burst size for memory writes + (DMA_DEV_TO_MEM/DMA_MEM_TO_MEM) to this value, specified in bytes, rather + than using the maximum burst size allowed by the hardware's buffer size. + If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM + will use the lower value. You can use dma-channels and dma-requests as described in dma.txt, although they won't be used, this information is derived from the compatibility string. diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt index fd5618bd8fbc..55492c264d17 100644 --- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt @@ -5,13 +5,13 @@ memcpy and memset capabilities. It has been designed for virtualized environments. Each HIDMA HW instance consists of multiple DMA channels. These channels -share the same bandwidth. The bandwidth utilization can be parititioned +share the same bandwidth. The bandwidth utilization can be partitioned among channels based on the priority and weight assignments. There are only two priority levels and 15 weigh assignments possible. Other parameters here determine how much of the system bus this HIDMA -instance can use like maximum read/write request and and number of bytes to +instance can use like maximum read/write request and number of bytes to read/write in a single burst. Main node required properties: @@ -47,12 +47,18 @@ When the OS is not in control of the management interface (i.e. it's a guest), the channel nodes appear on their own, not under a management node. Required properties: -- compatible: must contain "qcom,hidma-1.0" +- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1" +for MSI capable HW. - reg: Addresses for the transfer and event channel - interrupts: Should contain the event interrupt - desc-count: Number of asynchronous requests this channel can handle - iommus: required a iommu node +Optional properties for MSI: +- msi-parent : See the generic MSI binding described in + devicetree/bindings/interrupt-controller/msi.txt for a description of the + msi-parent property. + Example: Hypervisor OS configuration: diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 5f2ce669789a..3316a9c2e638 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -24,6 +24,7 @@ Required Properties: - "renesas,dmac-r8a7793" (R-Car M2-N) - "renesas,dmac-r8a7794" (R-Car E2) - "renesas,dmac-r8a7795" (R-Car H3) + - "renesas,dmac-r8a7796" (R-Car M3-W) - reg: base address and length of the registers block for the DMAC diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index 0f5583293c9c..4775c66f4508 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -27,6 +27,8 @@ Optional properties: that services interrupts for this device - is_private: The device channels should be marked as private and not for by the general purpose DMA channel allocator. False if not passed. +- multi-block: Multi block transfers supported by hardware. Array property with + one cell per channel. 0: not supported, 1 (default): supported. Example: diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt new file mode 100644 index 000000000000..e821e16ad65b --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -0,0 +1,108 @@ +NVIDIA Tegra Boot and Power Management Processor (BPMP) + +The BPMP is a specific processor in Tegra chip, which is designed for +booting process handling and offloading the power management, clock +management, and reset control tasks from the CPU. The binding document +defines the resources that would be used by the BPMP firmware driver, +which can create the interprocessor communication (IPC) between the CPU +and BPMP. + +Required properties: +- name : Should be bpmp +- compatible + Array of strings + One of: + - "nvidia,tegra186-bpmp" +- mboxes : The phandle of mailbox controller and the mailbox specifier. +- shmem : List of the phandle of the TX and RX shared memory area that + the IPC between CPU and BPMP is based on. +- #clock-cells : Should be 1. +- #power-domain-cells : Should be 1. +- #reset-cells : Should be 1. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +This node is a clock, power domain, and reset provider. See the following +files for general documentation of those features, and the specifiers +implemented by this node: + +- .../clock/clock-bindings.txt +- +- ../power/power_domain.txt +- +- .../reset/reset.txt +- + +The BPMP implements some services which must be represented by separate nodes. +For example, it can provide access to certain I2C controllers, and the I2C +bindings represent each I2C controller as a device tree node. Such nodes should +be nested directly inside the main BPMP node. + +Software can determine whether a child node of the BPMP node represents a device +by checking for a compatible property. Any node with a compatible property +represents a device that can be instantiated. Nodes without a compatible +property may be used to provide configuration information regarding the BPMP +itself, although no such configuration nodes are currently defined by this +binding. + +The BPMP firmware defines no single global name-/numbering-space for such +services. Put another way, the numbering scheme for I2C buses is distinct from +the numbering scheme for any other service the BPMP may provide (e.g. a future +hypothetical SPI bus service). As such, child device nodes will have no reg +property, and the BPMP node will have no #address-cells or #size-cells property. + +The shared memory bindings for BPMP +----------------------------------- + +The shared memory area for the IPC TX and RX between CPU and BPMP are +predefined and work on top of sysram, which is an SRAM inside the chip. + +See ".../sram/sram.txt" for the bindings. + +Example: + +hsp_top0: hsp@03c00000 { + ... + #mbox-cells = <2>; +}; + +sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; +}; + +bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "..."; + ... + }; +}; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 3b4436e56865..20f26fbce875 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -10,8 +10,10 @@ Required properties: * "qcom,scm-apq8064" for APQ8064 platforms * "qcom,scm-msm8660" for MSM8660 platforms * "qcom,scm-msm8690" for MSM8690 platforms + * "qcom,scm-msm8996" for MSM8996 platforms * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) - clocks: One to three clocks may be required based on compatible. + * No clock required for "qcom,scm-msm8996" * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" * Core, iface, and bus clocks required for "qcom,scm" - clock-names: Must contain "core" for the core clock, "iface" for the interface diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt new file mode 100644 index 000000000000..817a8d4bf903 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt @@ -0,0 +1,16 @@ +Altera FPGA To SDRAM Bridge Driver + +Required properties: +- compatible : Should contain "altr,socfpga-fpga2sdram-bridge" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + bridge-enable = <0>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt new file mode 100644 index 000000000000..f8e288c71b2d --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt @@ -0,0 +1,23 @@ +Altera Freeze Bridge Controller Driver + +The Altera Freeze Bridge Controller manages one or more freeze bridges. +The controller can freeze/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +unfreeze/enable the bridges which allows traffic to pass through the +bridge normally. + +Required properties: +- compatible : Should contain "altr,freeze-bridge-controller" +- regs : base address and size for freeze bridge module + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + freeze-controller@100000450 { + compatible = "altr,freeze-bridge-controller"; + regs = <0x1000 0x10>; + bridge-enable = <0>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt new file mode 100644 index 000000000000..6406f9337eeb --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt @@ -0,0 +1,39 @@ +Altera FPGA/HPS Bridge Driver + +Required properties: +- regs : base address and size for AXI bridge module +- compatible : Should contain one of: + "altr,socfpga-lwhps2fpga-bridge", + "altr,socfpga-hps2fpga-bridge", or + "altr,socfpga-fpga2hps-bridge" +- resets : Phandle and reset specifier for this bridge's reset +- clocks : Clocks used by this module. + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup. + 1 if driver should enable bridge at startup. + Default is to leave bridge in its current state. + +Example: + fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <0>; + }; + + fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <1>; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt new file mode 100644 index 000000000000..2fd8e7a84734 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -0,0 +1,19 @@ +Altera SOCFPGA Arria10 FPGA Manager + +Required properties: +- compatible : should contain "altr,socfpga-a10-fpga-mgr" +- reg : base address and size for memory mapped io. + - The first index is for FPGA manager register access. + - The second index is for writing FPGA configuration data. +- resets : Phandle and reset specifier for the device's reset. +- clocks : Clocks used by the device. + +Example: + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + }; diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index c3d016532d8e..30fd2201b3d4 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -17,7 +17,9 @@ Required properties: - #interrupt-cells: Specifies the number of cells needed to encode an interrupt source. - gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be one. It is the pin number. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. See gpio.txt for possible + values. Example for a MMP platform: @@ -27,7 +29,7 @@ Example for a MMP platform: interrupts = <49>; interrupt-names = "gpio_mux"; gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt new file mode 100644 index 000000000000..70c054a9a997 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt @@ -0,0 +1,20 @@ +* Freescale Low Power Inter IC (LPI2C) for i.MX + +Required properties: +- compatible : + - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc + - "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc +- reg : address and length of the lpi2c master registers +- interrupt-parent : core interrupt controller +- interrupts : lpi2c interrupt +- clocks : lpi2c clock specifier + +Examples: + +lpi2c7: lpi2c7@40A50000 { + compatible = "fsl,imx8dv-lpi2c"; + reg = <0x40A50000 0x10000>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_LPI2C7>; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt index 12b78ac507e9..d30f0b11d853 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt @@ -7,6 +7,7 @@ Required properties : compatible processor, e.g. pxa168, pxa910, mmp2, mmp3. For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required as shown in the example below. + For the Armada 3700, the compatible should be "marvell,armada-3700-i2c". Recommended properties : diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index 239632a0d709..2b8bd33dbf8d 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -1,17 +1,25 @@ I2C for R-Car platforms Required properties: -- compatible: Must be one of - "renesas,i2c-rcar" - "renesas,i2c-r8a7778" - "renesas,i2c-r8a7779" - "renesas,i2c-r8a7790" - "renesas,i2c-r8a7791" - "renesas,i2c-r8a7792" - "renesas,i2c-r8a7793" - "renesas,i2c-r8a7794" - "renesas,i2c-r8a7795" - "renesas,i2c-r8a7796" +- compatible: + "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. + "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. + "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. + "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC. + "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC. + "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC. + "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. + "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. + "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. + "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. + "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device. + "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device. + "renesas,i2c-rcar" (deprecated) + + When compatible with the generic version, nodes must list the + SoC-specific version corresponding to the platform first followed + by the generic version. + - reg: physical base address of the controller and length of memory mapped region. - interrupts: interrupt specifier. @@ -33,7 +41,7 @@ Examples : i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; + compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_I2C0>; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index 214f94c25d37..7716acc55dec 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt @@ -1,8 +1,7 @@ Device tree configuration for Renesas IIC (sh_mobile) driver Required properties: -- compatible : "renesas,iic-". "renesas,rmobile-iic" as fallback - Examples with soctypes are: +- compatible : - "renesas,iic-r8a73a4" (R-Mobile APE6) - "renesas,iic-r8a7740" (R-Mobile A1) - "renesas,iic-r8a7790" (R-Car H2) @@ -12,6 +11,17 @@ Required properties: - "renesas,iic-r8a7794" (R-Car E2) - "renesas,iic-r8a7795" (R-Car H3) - "renesas,iic-sh73a0" (SH-Mobile AG5) + - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device) + - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device) + - "renesas,rmobile-iic" (generic device) + + When compatible with a generic R-Car version, nodes + must list the SoC-specific version corresponding to + the platform first followed by the generic R-Car + version. + + renesas,rmobile-iic must always follow. + - reg : address start and address range size of device - interrupts : interrupt of device - clocks : clock for device @@ -31,7 +41,8 @@ Pinctrl properties might be needed, too. See there. Example: iic0: i2c@e6500000 { - compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC0>; diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index 5fa691e6f638..cee9d5055fa2 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -62,6 +62,9 @@ wants to support one of the below features, it should adapt the bindings below. "irq" and "wakeup" names are recognized by I2C core, other names are left to individual drivers. +- host-notify + device uses SMBus host notify protocol instead of interrupt line. + - multi-master states that there is another master active on this bus. The OS can use this information to adapt power management to keep the arbitration awake @@ -81,6 +84,11 @@ Binding may contain optional "interrupts" property, describing interrupts used by the device. I2C core will assign "irq" interrupt (or the very first interrupt if not using interrupt names) as primary interrupt for the slave. +Alternatively, devices supporting SMbus Host Notify, and connected to +adapters that support this feature, may use "host-notify" property. I2C +core will create a virtual interrupt for Host Notify and assign it as +primary interrupt for the slave. + Also, if device is marked as a wakeup source, I2C core will set up "wakeup" interrupt for the device. If "wakeup" interrupt name is not present in the binding, then primary interrupt will be used as wakeup interrupt. diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index df720ca00fcf..cdd7b48826c3 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -138,6 +138,8 @@ nuvoton,npct501 i2c trusted platform module (TPM) nuvoton,npct601 i2c trusted platform module (TPM2) nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset +nxp,pcf2127 Real-time clock +nxp,pcf2129 Real-time clock nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock oki,ml86v7667 OKI ML86V7667 video decoder @@ -167,4 +169,5 @@ ti,tsc2003 I2C Touch-Screen Controller ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface ti,tmp275 Digital Temperature Sensor +winbond,w83793 Winbond/Nuvoton H/W Monitor winbond,wpct301 i2c trusted platform module (TPM) diff --git a/Documentation/devicetree/bindings/input/da9062-onkey.txt b/Documentation/devicetree/bindings/input/da9062-onkey.txt index ab0e0488fe92..5f9fbc68e58a 100644 --- a/Documentation/devicetree/bindings/input/da9062-onkey.txt +++ b/Documentation/devicetree/bindings/input/da9062-onkey.txt @@ -1,32 +1,47 @@ -* Dialog DA9062/63 OnKey Module +* Dialog DA9061/62/63 OnKey Module -This module is part of the DA9062/DA9063. For more details about entire -chips see Documentation/devicetree/bindings/mfd/da9062.txt and -Documentation/devicetree/bindings/mfd/da9063.txt +This module is part of the DA9061/DA9062/DA9063. For more details about entire +DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt +For DA9063 see Documentation/devicetree/bindings/mfd/da9063.txt -This module provides KEY_POWER, KEY_SLEEP and events. +This module provides the KEY_POWER event. Required properties: -- compatible: should be one of: - dlg,da9062-onkey - dlg,da9063-onkey +- compatible: should be one of the following valid compatible string lines: + "dlg,da9061-onkey", "dlg,da9062-onkey" + "dlg,da9062-onkey" + "dlg,da9063-onkey" Optional properties: - - dlg,disable-key-power : Disable power-down using a long key-press. If this +- dlg,disable-key-power : Disable power-down using a long key-press. If this entry exists the OnKey driver will remove support for the KEY_POWER key - press. If this entry does not exist then by default the key-press - triggered power down is enabled and the OnKey will support both KEY_POWER - and KEY_SLEEP. + press when triggered using a long press of the OnKey. -Example: - - pmic0: da9062@58 { +Example: DA9063 + pmic0: da9063@58 { onkey { compatible = "dlg,da9063-onkey"; dlg,disable-key-power; }; - + }; + +Example: DA9062 + + pmic0: da9062@58 { + onkey { + compatible = "dlg,da9062-onkey"; + dlg,disable-key-power; + }; + }; + +Example: DA9061 using a fall-back compatible for the DA9062 onkey driver + + pmic0: da9061@58 { + onkey { + compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; + dlg,disable-key-power; + }; }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt index 853dff96dd9f..d4927c202aef 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt @@ -17,6 +17,8 @@ Optional properties: This value depends on the touch screen. - pre-charge-time: the touch screen need some time to precharge. This value depends on the touch screen. +- touchscreen-average-samples: Number of data samples which are averaged for + each read. Valid values are 1, 4, 8, 16 and 32. Example: tsc: tsc@02040000 { @@ -32,5 +34,6 @@ Example: xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xfff>; pre-charge-time = <0xffff>; + touchscreen-average-samples = <32>; status = "okay"; }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt index 820fee4b77b6..ce85ee508238 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt @@ -18,6 +18,8 @@ Optional properties: - touchscreen-inverted-y : See touchscreen.txt - touchscreen-swapped-x-y : See touchscreen.txt - silead,max-fingers : maximum number of fingers the touchscreen can detect +- vddio-supply : regulator phandle for controller VDDIO +- avdd-supply : regulator phandle for controller AVDD Example: diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt index bccaa4e73045..537643e86f61 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt @@ -14,6 +14,9 @@ Optional properties for Touchscreens: - touchscreen-fuzz-pressure : pressure noise value of the absolute input device (arbitrary range dependent on the controller) + - touchscreen-average-samples : Number of data samples which are averaged + for each read (valid values dependent on the + controller) - touchscreen-inverted-x : X axis is inverted (boolean) - touchscreen-inverted-y : Y axis is inverted (boolean) - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) diff --git a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt b/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt index 3e5b9793341f..8682ab6d4a50 100644 --- a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt +++ b/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt @@ -8,8 +8,9 @@ This driver provides a simple power button event via an Interrupt. Required properties: - compatible: should be "ti,tps65217-pwrbutton" or "ti,tps65218-pwrbutton" -Required properties for TPS65218: +Required properties: - interrupts: should be one of the following + - <2>: For controllers compatible with tps65217 - <3 IRQ_TYPE_EDGE_BOTH>: For controllers compatible with tps65218 Examples: @@ -17,6 +18,7 @@ Examples: &tps { tps65217-pwrbutton { compatible = "ti,tps65217-pwrbutton"; + interrupts = <2>; }; }; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt index e893615ef635..b48d7d30012c 100644 --- a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt +++ b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt @@ -12,7 +12,7 @@ Required properties: Example: -mailbox: mailbox@7e00b800 { +mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; interrupts = <0 1>; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt new file mode 100644 index 000000000000..b99d25fc2f26 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -0,0 +1,52 @@ +NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +The HSP modules are used for the processors to share resources and communicate +together. It provides a set of hardware synchronization primitives for +interprocessor communication. So the interprocessor communication (IPC) +protocols can use hardware synchronization primitives, when operating between +two processors not in an SMP relationship. + +The features that HSP supported are shared mailboxes, shared semaphores, +arbitrated semaphores and doorbells. + +Required properties: +- name : Should be hsp +- compatible + Array of strings. + one of: + - "nvidia,tegra186-hsp" +- reg : Offset and length of the register set for the device. +- interrupt-names + Array of strings. + Contains a list of names for the interrupts described by the interrupt + property. May contain the following entries, in any order: + - "doorbell" + Users of this binding MUST look up entries in the interrupt property + by name, using this interrupt-names property to do so. +- interrupts + Array of interrupt specifiers. + Must contain one entry per entry in the interrupt-names property, + in a matching order. +- #mbox-cells : Should be 2. + +The mbox specifier of the "mboxes" property in the client node should +contain two data. The first one should be the HSP type and the second +one should be the ID that the client is going to use. Those information +can be found in the following file. + +- . + +Example: + +hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; +}; + +client { + ... + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; +}; diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt index 5fe9372abb37..26ca25b6d264 100644 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt @@ -3,7 +3,8 @@ G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs. Required properties: -- compatible: should be "samsung,exynos5-gsc" +- compatible: should be "samsung,exynos5-gsc" (for Exynos 5250, 5420 and + 5422 SoCs) or "samsung,exynos5433-gsc" (Exynos 5433) - reg: should contain G-Scaler physical address location and length. - interrupts: should contain G-Scaler interrupt number diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt index fb5e7606643a..54e1bede6244 100644 --- a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt +++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt @@ -8,10 +8,11 @@ Required properties: the device. The interrupt specifier format depends on the interrupt controller parent. - clocks: clock phandle and specifier pair. - - hisilicon,power-syscon: phandle of syscon used to control power. Optional properties: - linux,rc-map-name : Remote control map name. + - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files. + Provide correct clocks instead. Example node: @@ -19,7 +20,6 @@ Example node: compatible = "hisilicon,hix5hd2-ir"; reg = <0xf8001000 0x1000>; interrupts = <0 47 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - hisilicon,power-syscon = <&sysctrl>; + clocks = <&clock HIX5HD2_IR_CLOCK>; linux,rc-map-name = "rc-tivo"; }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.txt b/Documentation/devicetree/bindings/media/i2c/adv7604.txt index 8337f75c75da..9cbd92eb5d05 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.txt +++ b/Documentation/devicetree/bindings/media/i2c/adv7604.txt @@ -34,6 +34,7 @@ The digital output port node must contain at least one endpoint. Optional Properties: - reset-gpios: Reference to the GPIO connected to the device's reset pin. + - default-input: Select which input is selected after reset. Optional Endpoint Properties: @@ -47,8 +48,6 @@ Optional Endpoint Properties: If none of hsync-active, vsync-active and pclk-sample is specified the endpoint will use embedded BT.656 synchronization. - - default-input: Select which input is selected after reset. - Example: hdmi_receiver@4c { diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt new file mode 100644 index 000000000000..4182063a54db --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-mdp.txt @@ -0,0 +1,109 @@ +* Mediatek Media Data Path + +Media Data Path is used for scaling and color space conversion. + +Required properties (controller (parent) node): +- compatible: "mediatek,mt8173-mdp" +- mediatek,vpu: the node of video processor unit, see + Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. + +Required properties (all function blocks, child node): +- compatible: Should be one of + "mediatek,mt8173-mdp-rdma" - read DMA + "mediatek,mt8173-mdp-rsz" - resizer + "mediatek,mt8173-mdp-wdma" - write DMA + "mediatek,mt8173-mdp-wrot" - write DMA with rotation +- reg: Physical base address and length of the function block register space +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- power-domains: a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. + +Required properties (DMA function blocks, child node): +- compatible: Should be one of + "mediatek,mt8173-mdp-rdma" + "mediatek,mt8173-mdp-wdma" + "mediatek,mt8173-mdp-wrot" +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,larb: must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. + +Example: +mdp { + compatible = "mediatek,mt8173-mdp"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + mediatek,vpu = <&vpu>; + + mdp_rdma0: rdma@14001000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,larb = <&larb0>; + }; + + mdp_rdma1: rdma@14002000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA1>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA1>; + mediatek,larb = <&larb4>; + }; + + mdp_rsz0: rsz@14003000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz1: rsz@14004000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz2: rsz@14005000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ2>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + }; + + mdp_wdma0: wdma@14006000 { + compatible = "mediatek,mt8173-mdp-wdma"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WDMA>; + mediatek,larb = <&larb0>; + }; + + mdp_wrot0: wrot@14007000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + mediatek,larb = <&larb0>; + }; + + mdp_wrot1: wrot@14008000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14008000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT1>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT1>; + mediatek,larb = <&larb4>; + }; +}; diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt index 59a47a5b924b..46c15c54175d 100644 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -1,25 +1,74 @@ Mediatek Video Codec Mediatek Video Codec is the video codec hw present in Mediatek SoCs which -supports high resolution encoding functionalities. +supports high resolution encoding and decoding functionalities. Required properties: - compatible : "mediatek,mt8173-vcodec-enc" for encoder + "mediatek,mt8173-vcodec-dec" for decoder. - reg : Physical base address of the video codec registers and length of memory mapped region. - interrupts : interrupt number to the cpu. - mediatek,larb : must contain the local arbiters in the current Socs. - clocks : list of clock specifiers, corresponding to entries in the clock-names property. -- clock-names: encoder must contain "venc_sel_src", "venc_sel", -- "venc_lt_sel_src", "venc_lt_sel". +- clock-names: encoder must contain "venc_sel_src", "venc_sel",, + "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", + "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", + "venc_lt_sel", "vdec_bus_clk_src". - iommus : should point to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. - mediatek,vpu : the node of video processor unit + Example: -vcodec_enc: vcodec@0x18002000 { + +vcodec_dec: vcodec@16000000 { + compatible = "mediatek,mt8173-vcodec-dec"; + reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/ + <0 0x16020000 0 0x1000>, /*VDEC_MISC*/ + <0 0x16021000 0 0x800>, /*VDEC_LD*/ + <0 0x16021800 0 0x800>, /*VDEC_TOP*/ + <0 0x16022000 0 0x1000>, /*VDEC_CM*/ + <0 0x16023000 0 0x1000>, /*VDEC_AD*/ + <0 0x16024000 0 0x1000>, /*VDEC_AV*/ + <0 0x16025000 0 0x1000>, /*VDEC_PP*/ + <0 0x16026800 0 0x800>, /*VP8_VD*/ + <0 0x16027000 0 0x800>, /*VP6_VD*/ + <0 0x16027800 0 0x800>, /*VP8_VL*/ + <0 0x16028400 0 0x400>; /*VP9_VD*/ + interrupts = ; + mediatek,larb = <&larb1>; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; + mediatek,vpu = <&vpu>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vcodecpll", + "univpll_d2", + "clk_cci400_sel", + "vdec_sel", + "vdecpll", + "vencpll", + "venc_lt_sel", + "vdec_bus_clk_src"; + }; + + vcodec_enc: vcodec@0x18002000 { compatible = "mediatek,mt8173-vcodec-enc"; reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.txt b/Documentation/devicetree/bindings/media/renesas,fcp.txt index 27f9b8e459ac..3ec91803ba58 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.txt +++ b/Documentation/devicetree/bindings/media/renesas,fcp.txt @@ -11,15 +11,9 @@ are paired with. These DT bindings currently support the FCPV and FCPF. - compatible: Must be one or more of the following - - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP' - - "renesas,r8a7795-fcpf" for R8A7795 (R-Car H3) compatible 'FCP for FDP' - "renesas,fcpv" for generic compatible 'FCP for VSP' - "renesas,fcpf" for generic compatible 'FCP for FDP' - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - - reg: the register base and size for the device registers - clocks: Reference to the functional clock @@ -32,7 +26,7 @@ Device node example ------------------- fcpvd1: fcp@fea2f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A7795_PD_A3VP>; diff --git a/Documentation/devicetree/bindings/media/renesas,fdp1.txt b/Documentation/devicetree/bindings/media/renesas,fdp1.txt new file mode 100644 index 000000000000..8dd1007bb573 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,fdp1.txt @@ -0,0 +1,37 @@ +Renesas R-Car Fine Display Processor (FDP1) +------------------------------------------- + +The FDP1 is a de-interlacing module which converts interlaced video to +progressive video. It is capable of performing pixel format conversion between +YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as +an input to the module. + +Required properties: + + - compatible: must be "renesas,fdp1" + - reg: the register base and size for the device registers + - interrupts : interrupt specifier for the FDP1 instance + - clocks: reference to the functional clock + +Optional properties: + + - power-domains: reference to the power domain that the FDP1 belongs to, if + any. + - renesas,fcp: a phandle referencing the FCP that handles memory accesses + for the FDP1. Not needed on Gen2, mandatory on Gen3. + +Please refer to the binding documentation for the clock and/or power domain +providers for more details. + + +Device node example +------------------- + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf0>; + }; diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index 92c94f5ecbf1..2c901286d818 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -12,6 +12,7 @@ Required properties: (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC + (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - reg : Physical base address of the IP registers and length of memory mapped region. diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt new file mode 100644 index 000000000000..ec1dd408d573 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt @@ -0,0 +1,20 @@ +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller + +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features +a set of registers which allow to tweak the controller's behavior. + +Documentation: +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf + +Required properties: + +- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards +- reg: a tuple containing the base address of the memory + controller and the size of the memory area to map + +Example for da850 shown below. + +ddrctl { + compatible = "ti,da850-ddr-controller"; + reg = <0xb0000000 0xe8>; +}; diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt new file mode 100644 index 000000000000..ea151f295ad7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt @@ -0,0 +1,46 @@ +* Altera Arria10 Development Kit System Resource Chip + +Required parent device properties: +- compatible : "altr,a10sr" +- spi-max-frequency : Maximum SPI frequency. +- reg : The SPI Chip Select address for the Arria10 + System Resource chip +- interrupt-parent : The parent interrupt controller. +- interrupts : The interrupt line the device is connected to. +- interrupt-controller : Marks the device node as an interrupt controller. +- #interrupt-cells : The number of cells to describe an IRQ, should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as trigger + masks from ../interrupt-controller/interrupts.txt. + +The A10SR consists of these sub-devices: + +Device Description +------ ---------- +a10sr_gpio GPIO Controller + +Arria10 GPIO +Required Properties: +- compatible : Should be "altr,a10sr-gpio" +- gpio-controller : Marks the device node as a GPIO Controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + +Example: + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt index 37a088f9a648..9e5eba4a4f0d 100644 --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt @@ -10,6 +10,7 @@ voltages and other various functionality to Qualcomm SoCs. Value type: Definition: must be one of: "qcom,pm8058" + "qcom,pm8821" "qcom,pm8921" - #address-cells: diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt index 9e6770b105c9..65c23263cc54 100644 --- a/Documentation/devicetree/bindings/mfd/rn5t618.txt +++ b/Documentation/devicetree/bindings/mfd/rn5t618.txt @@ -1,21 +1,25 @@ * Ricoh RN5T567/RN5T618 PMIC -Ricoh RN5T567/RN5T618 is a power management IC family which integrates -3 to 4 step-down DCDC converters, 7 low-dropout regulators, GPIOs and -a watchdog timer. The RN5T618 provides additionally a Li-ion battery -charger, fuel gauge and an ADC. It can be controlled through an I2C -interface. +Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which +integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators, +GPIOs, and a watchdog timer. It can be controlled through an I2C interface. +The RN5T618/RC5T619 provides additionally a Li-ion battery charger, +fuel gauge, and an ADC. +The RC5T619 additionnally includes USB charger detection and an RTC. Required properties: - compatible: must be one of "ricoh,rn5t567" "ricoh,rn5t618" + "ricoh,rc5t619" - reg: the I2C slave address of the device Sub-nodes: - regulators: the node is required if the regulator functionality is needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4 - (RN5T567), LDO1, LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2. + (RN5T567/RC5T619), LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, + LDO9, LDO10, LDORTC1 and LDORTC2. + LDO7-10 are specific to RC5T619. The common bindings for each individual regulator can be found in: Documentation/devicetree/bindings/regulator/regulator.txt diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index 07184e8f894e..ea9c1c9607f6 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -13,6 +13,7 @@ Required Properties: - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, before RK3288 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 + - "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt index 750374fc9d94..c0f37cb41a9b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt @@ -1,7 +1,9 @@ * Cadence SD/SDIO/eMMC Host Controller Required properties: -- compatible: should be "cdns,sd4hc". +- compatible: should be one of the following: + "cdns,sd4hc" - default of the IP + "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs - reg: offset and length of the register set for the device. - interrupts: a single interrupt specifier. - clocks: phandle to the input clock. @@ -19,7 +21,7 @@ if supported. See mmc.txt for details. Example: emmc: sdhci@5a000000 { - compatible = "cdns,sd4hc"; + compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; reg = <0x5a000000 0x400>; interrupts = <0 78 4>; clocks = <&clk 4>; diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt new file mode 100644 index 000000000000..56d5c19da41d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt @@ -0,0 +1,41 @@ +* Oxford Semiconductor OXNAS NAND Controller + +Please refer to nand.txt for generic information regarding MTD NAND bindings. + +Required properties: + - compatible: "oxsemi,ox820-nand" + - reg: Base address and length for NAND mapped memory. + +Optional Properties: + - clocks: phandle to the NAND gate clock if needed. + - resets: phandle to the NAND reset control if needed. + +Example: + +nandc: nand-controller@41000000 { + compatible = "oxsemi,ox820-nand"; + reg = <0x41000000 0x100000>; + clocks = <&stdclk CLK_820_NAND>; + resets = <&reset RESET_NAND>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "hamming"; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00e00000>; + read-only; + }; + + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt new file mode 100644 index 000000000000..0040eb8895e0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt @@ -0,0 +1,56 @@ +* Samsung S3C2410 and compatible NAND flash controller + +Required properties: +- compatible : The possible values are: + "samsung,s3c2410-nand" + "samsung,s3c2412-nand" + "samsung,s3c2440-nand" +- reg : register's location and length. +- #address-cells, #size-cells : see nand.txt +- clocks : phandle to the nand controller clock +- clock-names : must contain "nand" + +Optional child nodes: +Child nodes representing the available nand chips. + +Optional child properties: +- nand-ecc-mode : see nand.txt +- nand-on-flash-bbt : see nand.txt + +Each child device node may optionally contain a 'partitions' sub-node, +which further contains sub-nodes describing the flash partition mapping. +See partition.txt for more detail. + +Example: + +nand-controller@4e000000 { + compatible = "samsung,s3c2440-nand"; + reg = <0x4e000000 0x40>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clocks HCLK_NAND>; + clock-names = "nand"; + + nand { + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x040000>; + }; + + partition@40000 { + label = "kernel"; + reg = <0x040000 0x500000>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt new file mode 100644 index 000000000000..cd1bf2ac9055 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/tango-nand.txt @@ -0,0 +1,38 @@ +Sigma Designs Tango4 NAND Flash Controller (NFC) + +Required properties: + +- compatible: "sigma,smp8758-nand" +- reg: address/size of nfc_reg, nfc_mem, and pbus_reg +- dmas: reference to the DMA channel used by the controller +- dma-names: "rxtx" +- clocks: reference to the system clock +- #address-cells: <1> +- #size-cells: <0> + +Children nodes represent the available NAND chips. +See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. + +Example: + + nandc: nand-controller@2c000 { + compatible = "sigma,smp8758-nand"; + reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>; + dmas = <&dma0 3>; + dma-names = "rxtx"; + clocks = <&clkgen SYS_CLK>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; /* CS0 */ + nand-ecc-strength = <14>; + nand-ecc-step-size = <1024>; + }; + + nand@1 { + reg = <1>; /* CS1 */ + nand-ecc-strength = <14>; + nand-ecc-step-size = <1024>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt index 063c02da018a..eea73adc678f 100644 --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt @@ -2,11 +2,14 @@ Hisilicon hix5hd2 gmac controller Required properties: - compatible: should contain one of the following SoC strings: - * "hisilicon,hix5hd2-gemac" - * "hisilicon,hi3798cv200-gemac" + * "hisilicon,hix5hd2-gmac" + * "hisilicon,hi3798cv200-gmac" + * "hisilicon,hi3516a-gmac" and one of the following version string: - * "hisilicon,hisi-gemac-v1" - * "hisilicon,hisi-gemac-v2" + * "hisilicon,hisi-gmac-v1" + * "hisilicon,hisi-gmac-v2" + The version v1 includes SoCs hix5hd2. + The version v2 includes SoCs hi3798cv200, hi3516a. - reg: specifies base physical address(s) and size of the device registers. The first region is the MAC register base and size. The second region is external interface control register. @@ -35,7 +38,7 @@ Required properties: Example: gmac0: ethernet@f9840000 { - compatible = "hisilicon,hi3798cv200-gemac", "hisilicon,hisi-gemac-v2"; + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; reg = <0xf9840000 0x1000>,<0xf984300c 0x4>; interrupts = <0 71 4>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 54749b60a466..ff1bc4b1bb3b 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt @@ -38,8 +38,14 @@ Optional Properties: - enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to compensate for the board being designed with the lanes swapped. -- eee-broken-modes: Bits to clear in the MDIO_AN_EEE_ADV register to - disable EEE broken modes. +- eee-broken-100tx: +- eee-broken-1000t: +- eee-broken-10gt: +- eee-broken-1000kx: +- eee-broken-10gkx4: +- eee-broken-10gkr: + Mark the corresponding energy efficient ethernet mode as broken and + request the ethernet to stop advertising it. Example: diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 85bf945b898f..afe9630a5e7d 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -3,9 +3,11 @@ Required properties: - reg - The ID number for the phy, usually a small integer - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index 01b88f4e0d5b..b8e48b4762b2 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -1,10 +1,17 @@ * Broadcom iProc PCIe controller with the platform bus interface Required properties: -- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc" - for PAXC. PAXB-based root complex is used for external endpoint devices. - PAXC-based root complex is connected to emulated endpoint devices - internal to the ASIC +- compatible: + "brcm,iproc-pcie" for the first generation of PAXB based controller, +used in SoCs including NSP, Cygnus, NS2, and Pegasus + "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based +controllers, used in Stingray + "brcm,iproc-pcie-paxc" for the first generation of PAXC based +controller, used in NS2 + "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based +controller, used in Stingray + PAXB-based root complex is used for external endpoint devices. PAXC-based +root complex is connected to emulated endpoint devices internal to the ASIC - reg: base address and length of the PCIe controller I/O register space - #interrupt-cells: set to <1> - interrupt-map-mask and interrupt-map, standard PCI properties to define the @@ -19,6 +26,10 @@ Required properties: Optional properties: - phys: phandle of the PCIe PHY device - phy-names: must be "pcie-phy" +- dma-coherent: present if DMA operations are coherent +- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done + by the ASIC after power on reset. In this case, SW is required to configure +the mapping, based on inbound memory regions specified by this property. - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done by the ASIC after power on reset. In this case, SW needs to configure it @@ -29,11 +40,6 @@ effective: Required: - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal address used by the iProc PCIe core (not the PCIe address) -- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB) - -Optional: -- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to -increase the outbound window size MSI support (optional): @@ -41,10 +47,19 @@ For older platforms without MSI integrated in the GIC, iProc PCIe core provides an event queue based MSI support. The iProc MSI uses host memories to store MSI posted writes in the event queues -- msi-parent: Link to the device node of the MSI controller. On newer iProc -platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc -platforms without MSI support in its interrupt controller, one may use the -event queue based MSI support integrated within the iProc PCIe core. +On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used + +- msi-map: Maps a Requester ID to an MSI controller and associated MSI +sideband data + +- msi-parent: Link to the device node of the MSI controller, used when no MSI +sideband data is passed between the iProc PCIe controller and the MSI +controller + +Refer to the following binding documents for more detailed description on +the use of 'msi-map' and 'msi-parent': + Documentation/devicetree/bindings/pci/pci-msi.txt + Documentation/devicetree/bindings/interrupt-controller/msi.txt When the iProc event queue based MSI is used, one needs to define the following properties in the MSI device node: @@ -80,9 +95,7 @@ Example: phy-names = "pcie-phy"; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x00000000>; - brcm,pcie-ob-window-size = <256>; msi-parent = <&msi0>; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 41e9f55a1467..ee1c72d5162e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -15,6 +15,7 @@ Required properties: - compatible: should contain the platform identifier such as: "fsl,ls1021a-pcie", "snps,dw-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls1046a-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index b8cc395fffea..982a74ea6df9 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -110,6 +110,20 @@ Power supplies for Tegra124: - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must supply 1.05 V. +Power supplies for Tegra210: +- Required: + - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must + supply 1.05 V. + - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output + clocks. Must supply 1.8 V. + - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. + - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). + Must supply 3.3 V. + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must + supply 1.8 V. + Root ports are defined as subnodes of the PCIe controller node. Required properties: @@ -436,3 +450,99 @@ Board DTS: status = "okay"; }; }; + +Tegra210: +--------- + +SoC DTSI: + + pcie-controller@01003000 { + compatible = "nvidia,tegra210-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA210_CLK_PCIE>, + <&tegra_car TEGRA210_CLK_AFI>, + <&tegra_car TEGRA210_CLK_PLL_E>, + <&tegra_car TEGRA210_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + +Board DTS: + + pcie-controller@01003000 { + status = "okay"; + + avdd-pll-uerefe-supply = <&avdd_1v05_pll>; + hvddio-pex-supply = <&vdd_1v8>; + dvddio-pex-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + vddio-pex-ctl-supply = <&vdd_1v8>; + + pci@1,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; + status = "okay"; + }; + + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; + phy-names = "pcie-0"; + status = "okay"; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 08dcfad09f8d..50f9e2ca5b13 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -18,3 +18,9 @@ driver implementation may support the following properties: host bridges in the system, otherwise potentially conflicting domain numbers may be assigned to root buses behind different host bridges. The domain number for each host bridge in the system must be unique. +- max-link-speed: + If present this property specifies PCI gen for link capability. Host + drivers could add this as a strategy to avoid unnecessary operation for + unsupported link speed, for instance, trying to do training for + unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' + for gen2, and '1' for gen1. Any other values are invalid. diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 4059a6f89bc1..e15f9b19901f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -7,6 +7,7 @@ - "qcom,pcie-ipq8064" for ipq8064 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 + - "qcom,pcie-msm8996" for msm8996 or apq8096 - reg: Usage: required @@ -92,6 +93,17 @@ - "aux" Auxiliary (AUX) clock - "bus_master" Master AXI clock - "bus_slave" Slave AXI clock + +- clock-names: + Usage: required for msm8996/apq8096 + Value type: + Definition: Should contain the following entries + - "pipe" Pipe Clock driving internal logic + - "aux" Auxiliary (AUX) clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - resets: Usage: required Value type: @@ -115,7 +127,7 @@ - "core" Core reset - power-domains: - Usage: required for apq8084 + Usage: required for apq8084 and msm8996/apq8096 Value type: Definition: A phandle and power domain specifier pair to the power domain which is responsible for collapsing diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 6cf99690eef9..eee518db90b9 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -7,6 +7,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 66dcaa9efd74..e705acd3612c 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -7,6 +7,9 @@ Required properties: - reg : offset and length of the register set for the mux registers +- #pinctrl-cells : number of cells in addition to the index, set to 1 + for pinctrl-single,pins and 2 for pinctrl-single,bits + - pinctrl-single,register-width : pinmux register access width in bits - pinctrl-single,function-mask : mask of allowed pinmux function bits diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 0725fb37a973..d91715bc8d52 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -1,12 +1,14 @@ -DT bindings for the Renesas R-Car System Controller +DT bindings for the Renesas R-Car (RZ/G) System Controller == System Controller Node == -The R-Car System Controller provides power management for the CPU cores and -various coprocessors. +The R-Car (RZ/G) System Controller provides power management for the CPU cores +and various coprocessors. Required properties: - compatible: Must contain exactly one of the following: + - "renesas,r8a7743-sysc" (RZ/G1M) + - "renesas,r8a7745-sysc" (RZ/G1E) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W) diff --git a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt b/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt index 98d131acee95..a11072c5a866 100644 --- a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt +++ b/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt @@ -2,11 +2,16 @@ TPS65217 Charger Required Properties: -compatible: "ti,tps65217-charger" +-interrupts: TPS65217 interrupt numbers for the AC and USB charger input change. + Should be <0> for the USB charger and <1> for the AC adapter. +-interrupt-names: Should be "USB" and "AC" This node is a subnode of the tps65217 PMIC. Example: tps65217-charger { - compatible = "ti,tps65090-charger"; + compatible = "ti,tps65217-charger"; + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt index fb6fb31bc4c4..cf573e85b11d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt @@ -3,7 +3,7 @@ BCM2835 PWM controller (Raspberry Pi controller) Required properties: - compatible: should be "brcm,bcm2835-pwm" - reg: physical base address and length of the controller's registers -- clock: This clock defines the base clock frequency of the PWM hardware +- clocks: This clock defines the base clock frequency of the PWM hardware system, the period and the duty_cycle of the PWM signal is a multiple of the base period. - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of diff --git a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt new file mode 100644 index 000000000000..fa7849d67836 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt @@ -0,0 +1,21 @@ +Hisilicon PWM controller + +Required properties: +-compatible: should contain one SoC specific compatible string + The SoC specific strings supported including: + "hisilicon,hi3516cv300-pwm" + "hisilicon,hi3519v100-pwm" +- reg: physical base address and length of the controller's registers. +- clocks: phandle and clock specifier of the PWM reference clock. +- resets: phandle and reset specifier for the PWM controller reset. +- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + pwm: pwm@12130000 { + compatible = "hisilicon,hi3516cv300-pwm"; + reg = <0x12130000 0x10000>; + clocks = <&crg_ctrl HI3516CV300_PWM_CLK>; + resets = <&crg_ctrl 0x38 0>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt index fccc1d24af58..02f0e9bbfbf8 100644 --- a/Documentation/devicetree/bindings/regulator/tps65218.txt +++ b/Documentation/devicetree/bindings/regulator/tps65218.txt @@ -1,23 +1,78 @@ TPS65218 family of regulators Required properties: -For tps65218 regulators/LDOs -- compatible: - - "ti,tps65218-dcdc1" for DCDC1 - - "ti,tps65218-dcdc2" for DCDC2 - - "ti,tps65218-dcdc3" for DCDC3 - - "ti,tps65218-dcdc4" for DCDC4 - - "ti,tps65218-dcdc5" for DCDC5 - - "ti,tps65218-dcdc6" for DCDC6 - - "ti,tps65218-ldo1" for LDO1 +- compatible: "ti,tps65218" +- reg: I2C slave address -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt +- List of regulators provided by this controller, must be named + after their hardware counterparts: dcdc[1-6] and ldo1 +- This is the list of child nodes that specify the regulator + initialization data for defined regulators. Not all regulators for the given + device need to be present. The definition for each of these nodes is defined + using the standard binding for regulators found at ./regulator.txt. + + The valid names for regulators are: + tps65217: regulator-dcdc1, regulator-dcdc2, regulator-dcdc3, regulator-dcdc4, + regulator-dcdc5, regulator-dcdc6, regulator-ldo1, regulator-ls3. + Each regulator is defined using the standard binding for regulators. Example: +tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; - xyz: regulator@0 { - compatible = "ti,tps65218-dcdc1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; + dcdc1: regulator-dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; }; + + dcdc2: regulator-dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc6: regulator-dcdc6 { + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ls3: regulator-ls3 { + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <1000000>; + }; +}; diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt index 6f06db930030..d27ccb5d04fc 100644 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ b/Documentation/devicetree/bindings/reset/oxnas,reset.txt @@ -5,45 +5,19 @@ Please also refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "oxsemi,ox810se-reset" +- compatible: For OX810SE, should be "oxsemi,ox810se-reset" + For OX820, should be "oxsemi,ox820-reset" - #reset-cells: 1, see below Parent node should have the following properties : -- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" +- compatible: For OX810SE, should be : + "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" + For OX820, should be : + "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" -For OX810SE, the indices are : - - 0 : ARM - - 1 : COPRO - - 2 : Reserved - - 3 : Reserved - - 4 : USBHS - - 5 : USBHSPHY - - 6 : MAC - - 7 : PCI - - 8 : DMA - - 9 : DPE - - 10 : DDR - - 11 : SATA - - 12 : SATA_LINK - - 13 : SATA_PHY - - 14 : Reserved - - 15 : NAND - - 16 : GPIO - - 17 : UART1 - - 18 : UART2 - - 19 : MISC - - 20 : I2S - - 21 : AHB_MON - - 22 : UART3 - - 23 : UART4 - - 24 : SGDMA - - 25 : Reserved - - 26 : Reserved - - 27 : Reserved - - 28 : Reserved - - 29 : Reserved - - 30 : Reserved - - 31 : BUS +Reset indices are in dt-bindings include files : +- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h +- For OX820: include/dt-bindings/reset/oxsemi,ox820.h example: diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt index 1cfd21d1dfa1..92527138bc93 100644 --- a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt +++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt @@ -16,15 +16,14 @@ Please refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "st,-powerdown" - ex: "st,stih415-powerdown", "st,stih416-powerdown" +- compatible: Should be "st,stih407-powerdown" - #reset-cells: 1, see below example: powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; #reset-cells = <1>; - compatible = "st,stih415-powerdown"; }; @@ -37,11 +36,10 @@ index specifying which channel to use, as described in reset.txt example: - usb1: usb@fe200000 { - resets = <&powerdown STIH41X_USB1_POWERDOWN>; + st_dwc3: dwc3@8f94000 { + resets = <&powerdown STIH407_USB3_POWERDOWN>, }; Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h +include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt index 891a2fd85ed6..a21658f18fe6 100644 --- a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt +++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt @@ -15,15 +15,14 @@ Please refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "st,-softreset" example: - "st,stih415-softreset" or "st,stih416-softreset"; +- compatible: Should be st,stih407-softreset"; - #reset-cells: 1, see below example: softreset: softreset-controller { #reset-cells = <1>; - compatible = "st,stih415-softreset"; + compatible = "st,stih407-softreset"; }; @@ -42,5 +41,4 @@ example: Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h +include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt index 6a62acd86953..471477299ece 100644 --- a/Documentation/devicetree/bindings/rng/omap_rng.txt +++ b/Documentation/devicetree/bindings/rng/omap_rng.txt @@ -1,4 +1,4 @@ -OMAP SoC HWRNG Module +OMAP SoC and Inside-Secure HWRNG Module Required properties: @@ -6,11 +6,13 @@ Required properties: RNG versions: - "ti,omap2-rng" for OMAP2. - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX. + - "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block Note that these two versions are incompatible. - ti,hwmods: Name of the hwmod associated with the RNG module - reg : Offset and length of the register set for the module - interrupts : the interrupt number for the RNG module. - Only used for "ti,omap4-rng". + Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76" +- clocks: the trng clock source Example: /* AM335x */ @@ -20,3 +22,11 @@ rng: rng@48310000 { reg = <0x48310000 0x2000>; interrupts = <111>; }; + +/* SafeXcel IP-76 */ +trng: rng@f2760000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0xf2760000 0x7d>; + interrupts = ; + clocks = <&cpm_syscon0 1 25>; +}; diff --git a/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt b/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt new file mode 100644 index 000000000000..5f9df3f1467c --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt @@ -0,0 +1,16 @@ +EPSON TOYOCOM RTC-7301SF/DG + +Required properties: + +- compatible: Should be "epson,rtc7301sf" or "epson,rtc7301dg" +- reg: Specifies base physical address and size of the registers. +- interrupts: A single interrupt specifier. + +Example: + +rtc: rtc@44a00000 { + compatible = "epson,rtc7301dg"; + reg = <0x44a00000 0x10000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; +}; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt new file mode 100644 index 000000000000..41c7ae18fd7b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt @@ -0,0 +1,37 @@ +JZ4740 and similar SoCs real-time clock driver + +Required properties: + +- compatible: One of: + - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC + - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC +- reg: Address range of rtc register set +- interrupts: IRQ number for the alarm interrupt +- clocks: phandle to the "rtc" clock +- clock-names: must be "rtc" + +Optional properties: +- system-power-controller: To use this component as the + system power controller +- reset-pin-assert-time-ms: Reset pin low-level assertion + time after wakeup (default 60ms; range 0-125ms if RTC clock + at 32 kHz) +- min-wakeup-pin-assert-time-ms: Minimum wakeup pin assertion + time (default 100ms; range 0-2s if RTC clock at 32 kHz) + +Example: + +rtc@10003000 { + compatible = "ingenic,jz4740-rtc"; + reg = <0x10003000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <32>; + + clocks = <&rtc_clock>; + clock-names = "rtc"; + + system-power-controller; + reset-pin-assert-time-ms = <60>; + min-wakeup-pin-assert-time-ms = <100>; +}; diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt index 596e0c97be7a..8f9a94f2f896 100644 --- a/Documentation/devicetree/bindings/rtc/twl-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/twl-rtc.txt @@ -1,12 +1,11 @@ -* TI twl RTC - -The TWL family (twl4030/6030) contains a RTC. +* Texas Instruments TWL4030/6030 RTC Required properties: -- compatible : Should be twl4030-rtc +- compatible : Should be "ti,twl4030-rtc" +- interrupts : Should be the interrupt number. -Examples: - -rtc@0 { - compatible = "ti,twl4030-rtc"; -}; +Example: + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; diff --git a/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt b/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt new file mode 100644 index 000000000000..d89f99971368 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt @@ -0,0 +1,41 @@ +* Device Tree Bindings for IBM Virtual Trusted Platform Module(vtpm) + +Required properties: + +- compatible : property name that conveys the platform architecture + identifiers, as 'IBM,vtpm' +- device_type : specifies type of virtual device +- interrupts : property specifying the interrupt source number and + sense code associated with this virtual I/O Adapters +- ibm,my-drc-index : integer index for the connector between the device + and its parent - present only if Dynamic + Reconfiguration(DR) Connector is enabled +- ibm,#dma-address-cells: specifies the number of cells that are used to + encode the physical address field of dma-window + properties +- ibm,#dma-size-cells : specifies the number of cells that are used to + encode the size field of dma-window properties +- ibm,my-dma-window : specifies DMA window associated with this virtual + IOA +- ibm,loc-code : specifies the unique and persistent location code + associated with this virtual I/O Adapters +- linux,sml-base : 64-bit base address of the reserved memory allocated + for the firmware event log +- linux,sml-size : size of the memory allocated for the firmware event log + +Example (IBM Virtual Trusted Platform Module) +--------------------------------------------- + + vtpm@30000003 { + ibm,#dma-size-cells = <0x2>; + compatible = "IBM,vtpm"; + device_type = "IBM,vtpm"; + ibm,my-drc-index = <0x30000003>; + ibm,#dma-address-cells = <0x2>; + linux,sml-base = <0xc60e 0x0>; + interrupts = <0xa0003 0x0>; + ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>; + ibm,loc-code = "U8286.41A.10082DV-V3-C3"; + reg = <0x30000003>; + linux,sml-size = <0xbce10200>; + }; diff --git a/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt b/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt new file mode 100644 index 000000000000..8cb638b7e89c --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt @@ -0,0 +1,21 @@ +* Device Tree Bindings for I2C based Trusted Platform Module(TPM) + +Required properties: + +- compatible : 'manufacturer,model', eg. nuvoton,npct650 +- label : human readable string describing the device, eg. "tpm" +- linux,sml-base : 64-bit base address of the reserved memory allocated for + the firmware event log +- linux,sml-size : size of the memory allocated for the firmware event log + +Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C) +---------------------------------------------------------- + +tpm@57 { + reg = <0x57>; + label = "tpm"; + compatible = "nuvoton,npct650", "nuvoton,npct601"; + linux,sml-base = <0x7f 0xfd450000>; + linux,sml-size = <0x10000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt new file mode 100644 index 000000000000..41d740545189 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt @@ -0,0 +1,25 @@ +Trusted Computing Group MMIO Trusted Platform Module + +The TCG defines multi vendor standard for accessing a TPM chip, this +is the standard protocol defined to access the TPM via MMIO. Typically +this interface will be implemented over Intel's LPC bus. + +Refer to the 'TCG PC Client Specific TPM Interface Specification (TIS)' TCG +publication for the specification. + +Required properties: + +- compatible: should contain a string below for the chip, followed by + "tcg,tpm-tis-mmio". Valid chip strings are: + * "atmel,at97sc3204" +- reg: The location of the MMIO registers, should be at least 0x5000 bytes +- interrupt-parent/interrupts: An optional interrupt indicating command completion. + +Example: + + tpm_tis@90000 { + compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio"; + reg = <0x90000 0x5000>; + interrupt-parent = <&EIC0>; + interrupts = <1 2>; + }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index 845850caf088..c93a2d1c1a65 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt @@ -10,7 +10,7 @@ Required properties: See ../reset/reset.txt for details. - reset-names : Must include the following entries: - serial -- dmas : Must contain an entry for each entry in clock-names. +- dmas : Must contain an entry for each entry in dma-names. See ../dma/dma.txt for details. - dma-names : Must include the following entries: - rx diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index e8f15e34027f..16fe94d7783c 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -9,17 +9,20 @@ domain control. The driver implements the Generic PM domain bindings described in power/power_domain.txt. It provides the power domains defined in -include/dt-bindings/power/mt8173-power.h. +include/dt-bindings/power/mt8173-power.h and mt2701-power.h. Required properties: -- compatible: Must be "mediatek,mt8173-scpsys" +- compatible: Should be one of: + - "mediatek,mt2701-scpsys" + - "mediatek,mt8173-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit - infracfg: must contain a phandle to the infracfg controller - clock, clock-names: clocks according to the common clock binding. - The clocks needed "mm", "mfg", "venc" and "venc_lt". - These are the clocks which hardware needs to be enabled - before enabling certain power domains. + These are clocks which hardware needs to be + enabled before enabling certain power domains. + Required clocks for MT2701: "mm", "mfg", "ethif" + Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" Optional properties: - vdec-supply: Power supply for the vdec power domain diff --git a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt new file mode 100644 index 000000000000..5b9b38f578bb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt @@ -0,0 +1,88 @@ +Devicetree bindings for the Axentia TSE-850 audio complex + +Required properties: + - compatible: "axentia,tse850-pcm5142" + - axentia,ssc-controller: The phandle of the atmel SSC controller used as + cpu dai. + - axentia,audio-codec: The phandle of the PCM5142 codec. + - axentia,add-gpios: gpio specifier that controls the mixer. + - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1. + - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2. + - axentia,ana-supply: Regulator that supplies the output amplifier. Must + support voltages in the 2V - 20V range, in 1V steps. + +The schematics explaining the gpios are as follows: + + loop1 relays + IN1 +---o +------------+ o---+ OUT1 + \ / + + + + | / | + +--o +--. | + | add | | + | V | + | .---. | + DAC +----------->|Sum|---+ + | '---' | + | | + + + + + IN2 +---o--+------------+--o---+ OUT2 + loop2 relays + +The 'loop1' gpio pin controlls two relays, which are either in loop position, +meaning that input and output are directly connected, or they are in mixer +position, meaning that the signal is passed through the 'Sum' mixer. Similarly +for 'loop2'. + +In the above, the 'loop1' relays are inactive, thus feeding IN1 to the mixer +(if 'add' is active) and feeding the mixer output to OUT1. The 'loop2' relays +are active, short-cutting the TSE-850 from channel 2. IN1, IN2, OUT1 and OUT2 +are TSE-850 connectors and DAC is the PCB name of the (filtered) output from +the PCM5142 codec. + +Example: + + &i2c { + codec: pcm5142@4c { + compatible = "ti,pcm5142"; + + reg = <0x4c>; + + AVDD-supply = <®_3v3>; + DVDD-supply = <®_3v3>; + CPVDD-supply = <®_3v3>; + + clocks = <&sck>; + + pll-in = <3>; + pll-out = <6>; + }; + }; + + ana: ana-reg { + compatible = "pwm-regulator"; + + regulator-name = "ANA"; + + pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; + pwm-dutycycle-unit = <1000>; + pwm-dutycycle-range = <100 1000>; + + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <20000000>; + regulator-ramp-delay = <1000>; + }; + + sound { + compatible = "axentia,tse850-pcm5142"; + + axentia,ssc-controller = <&ssc0>; + axentia,audio-codec = <&codec>; + + axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; + axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; + + axentia,ana-supply = <&ana>; + }; diff --git a/Documentation/devicetree/bindings/sound/cs35l34.txt b/Documentation/devicetree/bindings/sound/cs35l34.txt new file mode 100644 index 000000000000..b218ead2e68e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l34.txt @@ -0,0 +1,64 @@ +CS35L34 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l34" + + - reg : the I2C address of the device for I2C. + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + + - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost + converter's output voltage in mV. The range is from VP to 8V with + increments of 100mV. + + - cirrus,boost-nanohenry: Inductor value for boost converter. The value is + in nH and they can be values of 1000nH, 1100nH, 1200nH, 1500nH, and 2200nH. + +Optional properties: + + - reset-gpios: GPIO used to reset the amplifier. + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L34 are delivered to. + - interrupts : IRQ line info CS35L34. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The + range starts at 1200mA and goes to a maximum of 3840mA with increments of + 80mA. The default value is 2480mA. + + - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the + received mono data is in the left or right portion of the I2S frame + according to the AD0 pin or directly via this configuration. + 0x0 (Default) = Selected by AD0 input (if AD0 = LOW, use left channel), + 0x2 = Left, + 0x1 = Selected by the inversion of the AD0 input (if AD0 = LOW, use right + channel), + 0x3 = Right. + + - cirrus,gain-zc-disable: Boolean property. If set, the gain change will take + effect without waiting for a zero cross. + + - cirrus,tdm-rising-edge: Boolean property. If set, data is on the rising edge of + SCLK. Otherwise, data is on the falling edge of SCLK. + + +Example: + +cs35l34: cs35l34@40 { + compatible = "cirrus,cs35l34"; + reg = <0x40>; + + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio 10 0>; + + cirrus,boost-vtge-milltvolt = <8000>; /* 8V */ + cirrus,boost-ind-nanohenry = <1000>; /* 1uH */ + cirrus,boost-peak-milliamp = <3000>; /* 3A */ +}; diff --git a/Documentation/devicetree/bindings/sound/cs42l42.txt b/Documentation/devicetree/bindings/sound/cs42l42.txt new file mode 100644 index 000000000000..9a2c5e2423d5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs42l42.txt @@ -0,0 +1,110 @@ +CS42L42 audio CODEC + +Required properties: + + - compatible : "cirrus,cs42l42" + + - reg : the I2C address of the device for I2C. + + - VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply : + power supplies for the device, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. If specified, it will be + deasserted before communication to the codec starts. + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS42L42 are delivered to. + + - interrupts : IRQ line info CS42L42. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense + polarity. Normal jacks will short tip sense pin to HS1 when headphones are + plugged in and leave tip sense floating when not plugged in. Inverting jacks + short tip sense when unplugged and float when plugged in. + + 0 = (Default) Non-inverted + 1 = Inverted + + - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no + debounce, the tip sense pin might be noisy on a plug event. + + 0 - 0ms, + 1 - 125ms, + 2 - 250ms, + 3 - 500ms, + 4 - 750ms, + 5 - (Default) 1s, + 6 - 1.25s, + 7 - 1.5s, + + - cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG. + With no debounce, the tip sense pin might be noisy on an unplug event. + + 0 - 0ms, + 1 - 125ms, + 2 - 250ms, + 3 - 500ms, + 4 - 750ms, + 5 - (Default) 1s, + 6 - 1.25s, + 7 - 1.5s, + + - cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after + enabling button detection interrupts. After auto-detection and before + servicing button interrupts, the HS bias needs time to settle. If you + don't wait, there is possibility for erroneous button interrupt. + + 0ms - 200ms, + Default = 100ms + + - cirrus,btn-det-event-dbnce : This sets how long the driver delays after + receiving a button press interrupt. With level detect interrupts, you want + to wait a small amount of time to make sure the button press is making a + clean connection with the bias resistors. + + 0ms - 20ms, + Default = 10ms + + - cirrus,bias-lvls : For a level-detect headset button scheme, each button + will bias the mic pin to a certain voltage. To determine which button was + pressed, the driver will compare this biased voltage to sequential, + decreasing voltages and will stop when a comparator is tripped, + indicating a comparator voltage < bias voltage. This value represents a + percentage of the internally generated HS bias voltage. For different + hardware setups, a designer might want to tweak this. This is an array of + descending values for the comparator voltage. + + Array of 4 values + Each 0-63 + < x1 x2 x3 x4 > + Default = < 15 8 4 1> + + +Example: + +cs42l42: cs42l42@48 { + compatible = "cirrus,cs42l42"; + reg = <0x48>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + VCP-supply = <&dummy_vreg>; + VD_FILT-supply = <&dummy_vreg>; + VL-supply = <&dummy_vreg>; + + reset-gpios = <&axi_gpio_0 1 0>; + interrupt-parent = <&gpio0>; + interrupts = <55 8> + + cirrus,ts-inv = <0x00>; + cirrus,ts-dbnc-rise = <0x05>; + cirrus,ts-dbnc-fall = <0x00>; + cirrus,btn-det-init-dbnce = <100>; + cirrus,btn-det-event-dbnce = <10>; + cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>; + cirrus,hs-bias-ramp-rate = <0x02>; +}; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt index 55b53e1fd72c..e0b6165c9cfc 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt @@ -43,7 +43,7 @@ mcbsp0: mcbsp@1d10000 { <0x00310000 0x1000>; reg-names = "mpu", "dat"; interrupts = <97 98>; - interrupts-names = "rx", "tx"; + interrupt-names = "rx", "tx"; dmas = <&edma0 3 1 &edma0 2 1>; dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt index d9d8635ff94c..6a4aadc4ce06 100644 --- a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt +++ b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt @@ -44,8 +44,7 @@ Required dai-link subnodes: Required CPU/CODEC subnodes properties: -link-name : Name of the dai link. --sound-dai : phandle and port of CPU/CODEC --capture-dai : phandle and port of CPU/CODEC +-sound-dai : phandle/s and port of CPU/CODEC Example: @@ -73,7 +72,7 @@ sound: sound { sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt new file mode 100644 index 000000000000..ccb401cfef9d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt @@ -0,0 +1,85 @@ +msm8916 analog audio CODEC + +Bindings for codec Analog IP which is integrated in pmic pm8916, + +## Bindings for codec core on pmic: + +Required properties + - compatible = "qcom,pm8916-wcd-analog-codec"; + - reg: represents the slave base address provided to the peripheral. + - interrupt-parent : The parent interrupt controller. + - interrupts: List of interrupts in given SPMI peripheral. + - interrupt-names: Names specified to above list of interrupts in same + order. List of supported interrupt names are: + "cdc_spk_cnp_int" - Speaker click and pop interrupt. + "cdc_spk_clip_int" - Speaker clip interrupt. + "cdc_spk_ocp_int" - Speaker over current protect interrupt. + "mbhc_ins_rem_det1" - jack insert removal detect interrupt 1. + "mbhc_but_rel_det" - button release interrupt. + "mbhc_but_press_det" - button press event + "mbhc_ins_rem_det" - jack insert removal detect interrupt. + "mbhc_switch_int" - multi button headset interrupt. + "cdc_ear_ocp_int" - Earphone over current protect interrupt. + "cdc_hphr_ocp_int" - Headphone R over current protect interrupt. + "cdc_hphl_ocp_det" - Headphone L over current protect interrupt. + "cdc_ear_cnp_int" - earphone cnp interrupt. + "cdc_hphr_cnp_int" - hphr click and pop interrupt. + "cdc_hphl_cnp_int" - hphl click and pop interrupt. + + - clocks: Handle to mclk. + - clock-names: should be "mclk" + - vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node. + - vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node. + - vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node. + +Optional Properties: +- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor + connected. +- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor + connected. + +Example: + +spmi_bus { + ... + audio-codec@f000{ + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000 0x200>; + reg-names = "pmic-codec-core"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + VDD-CDC-IO-supply = <&pm8916_l5>; + VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>; + VDD-MICBIAS-supply = <&pm8916_l13>; + #sound-dai-cells = <1>; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt new file mode 100644 index 000000000000..1c8e4cb25176 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt @@ -0,0 +1,20 @@ +msm8916 digital audio CODEC + +## Bindings for codec core in lpass: + +Required properties + - compatible = "qcom,msm8916-wcd-digital-codec"; + - reg: address space for lpass codec. + - clocks: Handle to mclk and ahbclk + - clock-names: should be "mclk", "ahbix-clk". + +Example: + +audio-codec@771c000{ + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt index 9cabfc18cb57..929ca6756b02 100644 --- a/Documentation/devicetree/bindings/sound/rt5514.txt +++ b/Documentation/devicetree/bindings/sound/rt5514.txt @@ -13,6 +13,9 @@ Optional properties: - clocks: The phandle of the master clock to the CODEC - clock-names: Should be "mclk" +- realtek,dmic-init-delay-ms + Set the DMIC initial delay (ms) to wait it ready. + Pins on the device (for linking into audio routes) for RT5514: * DMIC1L diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt index 7d3c974c6e2e..70eaeaed2b18 100644 --- a/Documentation/devicetree/bindings/sound/rt5663.txt +++ b/Documentation/devicetree/bindings/sound/rt5663.txt @@ -1,10 +1,10 @@ -RT5663/RT5668 audio CODEC +RT5663 audio CODEC This device supports I2C only. Required properties: -- compatible : One of "realtek,rt5663" or "realtek,rt5668". +- compatible : "realtek,rt5663". - reg : The I2C address of the device. @@ -12,7 +12,7 @@ Required properties: Optional properties: -Pins on the device (for linking into audio routes) for RT5663/RT5668: +Pins on the device (for linking into audio routes) for RT5663: * IN1P * IN1N diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt new file mode 100755 index 000000000000..419c89219681 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt5665.txt @@ -0,0 +1,68 @@ +RT5665/RT5666/RT5668 audio CODEC + +This device supports I2C only. + +Required properties: + +- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668". + +- reg : The I2C address of the device. + +- interrupts : The CODEC's interrupt output. + +Optional properties: + +- realtek,in1-differential +- realtek,in2-differential +- realtek,in3-differential +- realtek,in4-differential + Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended. + +- realtek,dmic1-data-pin + 0: dmic1 is not used + 1: using GPIO4 pin as dmic1 data pin + 2: using IN2N pin as dmic2 data pin + +- realtek,dmic2-data-pin + 0: dmic2 is not used + 1: using GPIO5 pin as dmic2 data pin + 2: using IN2P pin as dmic2 data pin + +- realtek,jd-src + 0: No JD is used + 1: using JD1 as JD source + +- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. + +Pins on the device (for linking into audio routes) for RT5659/RT5658: + + * DMIC L1 + * DMIC R1 + * DMIC L2 + * DMIC R2 + * IN1P + * IN1N + * IN2P + * IN2N + * IN3P + * IN3N + * IN4P + * IN4N + * HPOL + * HPOR + * LOUTL + * LOUTR + * MONOOUT + * PDML + * PDMR + +Example: + +rt5659 { + compatible = "realtek,rt5665"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; +}; diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt new file mode 100644 index 000000000000..94442e5673b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt @@ -0,0 +1,38 @@ +Samsung Exynos5433 TM2(E) audio complex with WM5110 codec + +Required properties: + + - compatible : "samsung,tm2-audio" + - model : the user-visible name of this sound complex + - audio-codec : the phandle of the wm5110 audio codec node, + as described in ../mfd/arizona.txt + - i2s-controller : the phandle of the I2S controller + - audio-amplifier : the phandle of the MAX98504 amplifier + - samsung,audio-routing : a list of the connections between audio components; + each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source; valid names for sources and sinks are the + WM5110's and MAX98504's pins and the jacks on the + board: HP, SPK, Main Mic, Sub Mic, Third Mic, + Headset Mic + - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator + + +Example: + +sound { + compatible = "samsung,tm2-audio"; + audio-codec = <&wm5110>; + i2s-controller = <&i2s0>; + audio-amplifier = <&max98504>; + mic-bias-gpios = <&gpr3 2 0>; + model = "wm5110"; + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + "SPK", "SPKOUT", + "SPKOUT", "HPOUT2L", + "SPKOUT", "HPOUT2R", + "Main Mic", "MICBIAS2", + "IN1R", "Main Mic"; +}; diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt index 0dce690f78f5..3033bd8aab0f 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt @@ -1,8 +1,12 @@ * Allwinner A10 Codec Required properties: -- compatible: must be either "allwinner,sun4i-a10-codec" or - "allwinner,sun7i-a20-codec" +- compatible: must be one of the following compatibles: + - "allwinner,sun4i-a10-codec" + - "allwinner,sun6i-a31-codec" + - "allwinner,sun7i-a20-codec" + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" - reg: must contain the registers location and length - interrupts: must contain the codec interrupt - dmas: DMA channels for tx and rx dma. See the DMA client binding, @@ -17,6 +21,43 @@ Required properties: Optional properties: - allwinner,pa-gpios: gpio to enable external amplifier +Required properties for the following compatibles: + - "allwinner,sun6i-a31-codec" + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" +- resets: phandle to the reset control for this device +- allwinner,audio-routing: A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names include: + + Audio pins on the SoC: + "HP" + "HPCOM" + "LINEIN" + "LINEOUT" (not on sun8i-a23) + "MIC1" + "MIC2" + "MIC3" (sun6i-a31 only) + + Microphone biases from the SoC: + "HBIAS" + "MBIAS" + + Board connectors: + "Headphone" + "Headset Mic" + "Line In" + "Line Out" + "Mic" + "Speaker" + +Required properties for the following compatibles: + - "allwinner,sun8i-a23-codec" + - "allwinner,sun8i-h3-codec" +- allwinner,codec-analog-controls: A phandle to the codec analog controls + block in the PRCM. + Example: codec: codec@01c22c00 { #sound-dai-cells = <0>; @@ -28,3 +69,23 @@ codec: codec@01c22c00 { dmas = <&dma 0 19>, <&dma 0 19>; dma-names = "rx", "tx"; }; + +codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x98>; + interrupts = ; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "MBIAS", + "MIC1", "Mic", + "MIC2", "HBIAS", + "MIC2", "Headset Mic"; +}; diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt new file mode 100644 index 000000000000..779b735781ba --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt @@ -0,0 +1,16 @@ +* Allwinner Codec Analog Controls + +Required properties: +- compatible: must be one of the following compatibles: + - "allwinner,sun8i-a23-codec-analog" + - "allwinner,sun8i-h3-codec-analog" + +Required properties if not a sub-node of the PRCM node: +- reg: must contain the registers location and length + +Example: +prcm: prcm@01f01400 { + codec_analog: codec-analog { + compatible = "allwinner,sun8i-a23-codec-analog"; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt index 9340d2ddcc54..6fbba562eaa7 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt @@ -12,6 +12,7 @@ Required properties: "ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP) "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP) "ti,tlv320dac3100" - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP) + "ti,tlv320dac3101" - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP) - reg - - I2C slave address - HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply, diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt index 7d9821f348da..78fce9b14954 100644 --- a/Documentation/devicetree/bindings/sound/wm8580.txt +++ b/Documentation/devicetree/bindings/sound/wm8580.txt @@ -1,10 +1,10 @@ -WM8580 audio CODEC +WM8580 and WM8581 audio CODEC This device supports I2C only. Required properties: - - compatible : "wlf,wm8580" + - compatible : "wlf,wm8580", "wlf,wm8581" - reg : the I2C address of the device. diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt index add48f09015e..068c2c03c38f 100644 --- a/Documentation/devicetree/bindings/sram/sram.txt +++ b/Documentation/devicetree/bindings/sram/sram.txt @@ -4,7 +4,7 @@ Simple IO memory regions to be managed by the genalloc API. Required properties: -- compatible : mmio-sram +- compatible : mmio-sram or atmel,sama5d2-securam - reg : SRAM iomem address range diff --git a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt new file mode 100644 index 000000000000..474531d2b2c5 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt @@ -0,0 +1,17 @@ +Binding for Thermal Sensor driver for BCM2835 SoCs. + +Required parameters: +------------------- + +compatible: should be one of: "brcm,bcm2835-thermal", + "brcm,bcm2836-thermal" or "brcm,bcm2837-thermal" +reg: Address range of the thermal registers. +clocks: Phandle of the clock used by the thermal sensor. + +Example: + +thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; +}; diff --git a/Documentation/devicetree/bindings/thermal/st-thermal.txt b/Documentation/devicetree/bindings/thermal/st-thermal.txt index 3b9251b4a145..a2f939137e35 100644 --- a/Documentation/devicetree/bindings/thermal/st-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/st-thermal.txt @@ -3,17 +3,8 @@ Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs. Required parameters: ------------------- -compatible : st,--thermal; should be one of: - "st,stih415-sas-thermal", - "st,stih415-mpe-thermal", - "st,stih416-sas-thermal" - "st,stih416-mpe-thermal" - "st,stid127-thermal" or - "st,stih407-thermal" - according to the SoC type (stih415, stih416, stid127, stih407) - and module type (sas or mpe). On stid127 & stih407 there is only - one die/module, so there is no module type in the compatible - string. +compatible : Should be "st,stih407-thermal" + clock-names : Should be "thermal". See: Documentation/devicetree/bindings/resource-names.txt clocks : Phandle of the clock used by the thermal sensor. @@ -25,18 +16,17 @@ Optional parameters: reg : For non-sysconf based sensors, this should be the physical base address and length of the sensor's registers. interrupts : Standard way to define interrupt number. - Interrupt is mandatory to be defined when compatible is - "stih416-mpe-thermal". NB: For thermal sensor's for which no interrupt has been defined, a polling delay of 1000ms will be used to read the temperature from device. Example: - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clock-names = "thermal"; - clocks = <&clk_m_mpethsens>; - interrupts = ; + temp0@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&CLK_SYSIN>; + interrupts = ; + st,passive_cooling_temp = <110>; }; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt new file mode 100644 index 000000000000..e3cfce8fecc5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt @@ -0,0 +1,17 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer0" + +Clocks required for compatible = "ezchip,nps400-timer0": +- interrupts : The interrupt of the first timer +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; +}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt similarity index 52% rename from Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt rename to Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt index c8c03d700382..c0ab4190b8fb 100644 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt @@ -2,14 +2,14 @@ NPS Network Processor Required properties: -- compatible : should be "ezchip,nps400-timer" +- compatible : should be "ezchip,nps400-timer1" -Clocks required for compatible = "ezchip,nps400-timer": +Clocks required for compatible = "ezchip,nps400-timer1": - clocks : Must contain a single entry describing the clock input Example: timer { - compatible = "ezchip,nps400-timer"; + compatible = "ezchip,nps400-timer1"; clocks = <&sysclk>; }; diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index f4262ed60582..ad8ea56a9ed3 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -6,9 +6,9 @@ Required properties: - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers used in host mode. - reg: Address and length of the register set for the device - - interrupts: Should contain ehci interrupt + - interrupts: Should contain ohci interrupt - clocks: Should reference the peripheral, host and system clocks - - clock-names: Should contains two strings + - clock-names: Should contain three strings "ohci_clk" for the peripheral clock "hclk" for the host clock "uhpck" for the system clock @@ -35,7 +35,7 @@ Required properties: - reg: Address and length of the register set for the device - interrupts: Should contain ehci interrupt - clocks: Should reference the peripheral and the UTMI clocks - - clock-names: Should contains two strings + - clock-names: Should contain two strings "ehci_clk" for the peripheral clock "usb_clk" for the UTMI clock @@ -58,7 +58,7 @@ Required properties: - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - clocks: Should reference the peripheral and the AHB clocks - - clock-names: Should contains two strings + - clock-names: Should contain two strings "pclk" for the peripheral clock "hclk" for the AHB clock @@ -85,7 +85,7 @@ Required properties: - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt - clocks: Should reference the peripheral and host clocks - - clock-names: Should contains two strings + - clock-names: Should contain two strings "pclk" for the peripheral clock "hclk" for the host clock - ep childnode: To specify the number of endpoints and their properties. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 98371753a08f..16d3b5e7f5d1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -24,9 +24,11 @@ ampire Ampire Co., Ltd. ams AMS AG amstaos AMS-Taos Inc. analogix Analogix Semiconductor, Inc. +andestech Andes Technology Corporation apm Applied Micro Circuits Corporation (APM) aptina Aptina Imaging arasan Arasan Chip Systems +aries Aries Embedded GmbH arm ARM Ltd. armadeus ARMadeus Systems SARL arrow Arrow Electronics @@ -68,6 +70,7 @@ creative Creative Technology Ltd crystalfontz Crystalfontz America, Inc. cubietech Cubietech, Ltd. cypress Cypress Semiconductor Corporation +cznic CZ.NIC, z.s.p.o. dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. delta Delta Electronics, Inc. @@ -137,6 +140,7 @@ infineon Infineon Technologies inforce Inforce Computing ingenic Ingenic Semiconductor innolux Innolux Corporation +inside-secure INSIDE Secure intel Intel Corporation intercontrol Inter Control Group invensense InvenSense Inc. @@ -160,6 +164,7 @@ lg LG Corporation linux Linux-specific binding lltc Linear Technology Corporation lsi LSI Corp. (LSI Logic) +macnica Macnica Americas marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products mcube mCube @@ -185,20 +190,24 @@ mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) mundoreader Mundo Reader S.L. murata Murata Manufacturing Co., Ltd. mxicy Macronix International Co., Ltd. +myir MYIR Tech Limited national National Semiconductor nec NEC LCD Technologies, Ltd. neonode Neonode Inc. netgear NETGEAR netlogic Broadcom Corporation (formerly NetLogic Microsystems) netxeon Shenzhen Netxeon Technology CO., LTD +nexbox Nexbox newhaven Newhaven Display International -nvd New Vision Display +ni National Instruments nintendo Nintendo nokia Nokia nuvoton Nuvoton Technology Corporation +nvd New Vision Display nvidia NVIDIA nxp NXP Semiconductors okaya Okaya Electric America, Inc. +oki Oki Electric Industry Co., Ltd. olimex OLIMEX Ltd. onion Onion Corporation onnn ON Semiconductor Corp. @@ -214,6 +223,7 @@ parade Parade Technologies Inc. pericom Pericom Technology Inc. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd +pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA @@ -235,8 +245,10 @@ realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. +rikomagic Rikomagic Tech Corp. Ltd rockchip Fuzhou Rockchip Electronics Co., Ltd samsung Samsung Semiconductor +samtec Samtec/Softing company sandisk Sandisk Corporation sbs Smart Battery System schindler Schindler @@ -281,6 +293,7 @@ tcg Trusted Computing Group tcl Toby Churchill Ltd. technexion TechNexion technologic Technologic Systems +terasic Terasic Inc. thine THine Electronics, Inc. ti Texas Instruments tlm Trusted Logic Mobility @@ -295,6 +308,7 @@ tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited tyan Tyan Computer Corporation +udoo Udoo uniwest United Western Technologies Corp (UniWest) upisemi uPI Semiconductor Corp. urt United Radiant Technology Corporation diff --git a/Documentation/dmaengine/client.txt b/Documentation/dmaengine/client.txt index 9e33189745f0..c72b4563de10 100644 --- a/Documentation/dmaengine/client.txt +++ b/Documentation/dmaengine/client.txt @@ -37,8 +37,8 @@ The slave DMA usage consists of following steps: 2. Set slave and controller specific parameters Next step is always to pass some specific information to the DMA - driver. Most of the generic information which a slave DMA can use - is in struct dma_slave_config. This allows the clients to specify + driver. Most of the generic information which a slave DMA can use + is in struct dma_slave_config. This allows the clients to specify DMA direction, DMA addresses, bus widths, DMA burst lengths etc for the peripheral. @@ -52,7 +52,7 @@ The slave DMA usage consists of following steps: struct dma_slave_config *config) Please see the dma_slave_config structure definition in dmaengine.h - for a detailed explanation of the struct members. Please note + for a detailed explanation of the struct members. Please note that the 'direction' member will be going away as it duplicates the direction given in the prepare call. @@ -101,7 +101,7 @@ The slave DMA usage consists of following steps: desc = dmaengine_prep_slave_sg(chan, sgl, nr_sg, direction, flags); Once a descriptor has been obtained, the callback information can be - added and the descriptor must then be submitted. Some DMA engine + added and the descriptor must then be submitted. Some DMA engine drivers may hold a spinlock between a successful preparation and submission so it is important that these two operations are closely paired. @@ -138,7 +138,7 @@ The slave DMA usage consists of following steps: activity via other DMA engine calls not covered in this document. dmaengine_submit() will not start the DMA operation, it merely adds - it to the pending queue. For this, see step 5, dma_async_issue_pending. + it to the pending queue. For this, see step 5, dma_async_issue_pending. 5. Issue pending DMA requests and wait for callback notification @@ -184,13 +184,13 @@ Further APIs: 3. int dmaengine_resume(struct dma_chan *chan) - Resume a previously paused DMA channel. It is invalid to resume a + Resume a previously paused DMA channel. It is invalid to resume a channel which is not currently paused. 4. enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) - This can be used to check the status of the channel. Please see + This can be used to check the status of the channel. Please see the documentation in include/linux/dmaengine.h for a more complete description of this API. @@ -200,7 +200,7 @@ Further APIs: Note: Not all DMA engine drivers can return reliable information for - a running DMA channel. It is recommended that DMA engine users + a running DMA channel. It is recommended that DMA engine users pause or stop (via dmaengine_terminate_all()) the channel before using this API. diff --git a/Documentation/dmaengine/dmatest.txt b/Documentation/dmaengine/dmatest.txt index dd77a81bdb80..fb683c72dea8 100644 --- a/Documentation/dmaengine/dmatest.txt +++ b/Documentation/dmaengine/dmatest.txt @@ -34,7 +34,7 @@ command: % ls -1 /sys/class/dma/ Once started a message like "dmatest: Started 1 threads using dma0chan0" is -emitted. After that only test failure messages are reported until the test +emitted. After that only test failure messages are reported until the test stops. Note that running a new test will not stop any in progress test. @@ -43,11 +43,11 @@ The following command returns the state of the test. % cat /sys/module/dmatest/parameters/run To wait for test completion userpace can poll 'run' until it is false, or use -the wait parameter. Specifying 'wait=1' when loading the module causes module +the wait parameter. Specifying 'wait=1' when loading the module causes module initialization to pause until a test run has completed, while reading /sys/module/dmatest/parameters/wait waits for any running test to complete -before returning. For example, the following scripts wait for 42 tests -to complete before exiting. Note that if 'iterations' is set to 'infinite' then +before returning. For example, the following scripts wait for 42 tests +to complete before exiting. Note that if 'iterations' is set to 'infinite' then waiting is disabled. Example: @@ -81,7 +81,7 @@ Example of output: The message format is unified across the different types of errors. A number in the parens represents additional information, e.g. error code, error counter, -or status. A test thread also emits a summary line at completion listing the +or status. A test thread also emits a summary line at completion listing the number of tests executed, number that failed, and a result code. Example: diff --git a/Documentation/dmaengine/provider.txt b/Documentation/dmaengine/provider.txt index c4fd47540b31..e33bc1c8ed2c 100644 --- a/Documentation/dmaengine/provider.txt +++ b/Documentation/dmaengine/provider.txt @@ -384,7 +384,7 @@ where to put them) - The descriptor should be prepared for reuse by invoking dmaengine_desc_set_reuse() which will set DMA_CTRL_REUSE. - dmaengine_desc_set_reuse() will succeed only when channel support - reusable descriptor as exhibited by capablities + reusable descriptor as exhibited by capabilities - As a consequence, if a device driver wants to skip the dma_map_sg() and dma_unmap_sg() in between 2 transfers, because the DMA'd data wasn't used, it can resubmit the transfer right after its completion. diff --git a/Documentation/dmaengine/pxa_dma.txt b/Documentation/dmaengine/pxa_dma.txt index 413ef9cfaa4d..0736d44b5438 100644 --- a/Documentation/dmaengine/pxa_dma.txt +++ b/Documentation/dmaengine/pxa_dma.txt @@ -29,7 +29,7 @@ Constraints d) Bandwidth guarantee The PXA architecture has 4 levels of DMAs priorities : high, normal, low. - The high prorities get twice as much bandwidth as the normal, which get twice + The high priorities get twice as much bandwidth as the normal, which get twice as much as the low priorities. A driver should be able to request a priority, especially the real-time ones such as pxa_camera with (big) throughputs. diff --git a/Documentation/dontdiff b/Documentation/dontdiff index 5385cba941d2..a23edccd2059 100644 --- a/Documentation/dontdiff +++ b/Documentation/dontdiff @@ -139,7 +139,6 @@ hpet_example hugepage-mmap hugepage-shm ihex2fw -ikconfig.h* inat-tables.c initramfs_list int16.c diff --git a/Documentation/driver-api/edac.rst b/Documentation/driver-api/edac.rst new file mode 100644 index 000000000000..b8c742aa0a71 --- /dev/null +++ b/Documentation/driver-api/edac.rst @@ -0,0 +1,178 @@ +Error Detection And Correction (EDAC) Devices +============================================= + +Main Concepts used at the EDAC subsystem +---------------------------------------- + +There are several things to be aware of that aren't at all obvious, like +*sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*, +etc... + +These are some of the many terms that are thrown about that don't always +mean what people think they mean (Inconceivable!). In the interest of +creating a common ground for discussion, terms and their definitions +will be established. + +* Memory devices + +The individual DRAM chips on a memory stick. These devices commonly +output 4 and 8 bits each (x4, x8). Grouping several of these in parallel +provides the number of bits that the memory controller expects: +typically 72 bits, in order to provide 64 bits + 8 bits of ECC data. + +* Memory Stick + +A printed circuit board that aggregates multiple memory devices in +parallel. In general, this is the Field Replaceable Unit (FRU) which +gets replaced, in the case of excessive errors. Most often it is also +called DIMM (Dual Inline Memory Module). + +* Memory Socket + +A physical connector on the motherboard that accepts a single memory +stick. Also called as "slot" on several datasheets. + +* Channel + +A memory controller channel, responsible to communicate with a group of +DIMMs. Each channel has its own independent control (command) and data +bus, and can be used independently or grouped with other channels. + +* Branch + +It is typically the highest hierarchy on a Fully-Buffered DIMM memory +controller. Typically, it contains two channels. Two channels at the +same branch can be used in single mode or in lockstep mode. When +lockstep is enabled, the cacheline is doubled, but it generally brings +some performance penalty. Also, it is generally not possible to point to +just one memory stick when an error occurs, as the error correction code +is calculated using two DIMMs instead of one. Due to that, it is capable +of correcting more errors than on single mode. + +* Single-channel + +The data accessed by the memory controller is contained into one dimm +only. E. g. if the data is 64 bits-wide, the data flows to the CPU using +one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3 +memories. FB-DIMM and RAMBUS use a different concept for channel, so +this concept doesn't apply there. + +* Double-channel + +The data size accessed by the memory controller is interlaced into two +dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72 +bits with ECC), the data flows to the CPU using a 128 bits parallel +access. + +* Chip-select row + +This is the name of the DRAM signal used to select the DRAM ranks to be +accessed. Common chip-select rows for single channel are 64 bits, for +dual channel 128 bits. It may not be visible by the memory controller, +as some DIMM types have a memory buffer that can hide direct access to +it from the Memory Controller. + +* Single-Ranked stick + +A Single-ranked stick has 1 chip-select row of memory. Motherboards +commonly drive two chip-select pins to a memory stick. A single-ranked +stick, will occupy only one of those rows. The other will be unused. + +.. _doubleranked: + +* Double-Ranked stick + +A double-ranked stick has two chip-select rows which access different +sets of memory devices. The two rows cannot be accessed concurrently. + +* Double-sided stick + +**DEPRECATED TERM**, see :ref:`Double-Ranked stick `. + +A double-sided stick has two chip-select rows which access different sets +of memory devices. The two rows cannot be accessed concurrently. +"Double-sided" is irrespective of the memory devices being mounted on +both sides of the memory stick. + +* Socket set + +All of the memory sticks that are required for a single memory access or +all of the memory sticks spanned by a chip-select row. A single socket +set has two chip-select rows and if double-sided sticks are used these +will occupy those chip-select rows. + +* Bank + +This term is avoided because it is unclear when needing to distinguish +between chip-select rows and socket sets. + + +Memory Controllers +------------------ + +Most of the EDAC core is focused on doing Memory Controller error detection. +The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info`` +to describe the memory controllers, with is an opaque struct for the EDAC +drivers. Only the EDAC core is allowed to touch it. + +.. kernel-doc:: include/linux/edac.h + +.. kernel-doc:: drivers/edac/edac_mc.h + +PCI Controllers +--------------- + +The EDAC subsystem provides a mechanism to handle PCI controllers by calling +the :c:func:`edac_pci_alloc_ctl_info`. It will use the struct +:c:type:`edac_pci_ctl_info` to describe the PCI controllers. + +.. kernel-doc:: drivers/edac/edac_pci.h + +EDAC Blocks +----------- + +The EDAC subsystem also provides a generic mechanism to report errors on +other parts of the hardware via :c:func:`edac_device_alloc_ctl_info` function. + +The structures :c:type:`edac_dev_sysfs_block_attribute`, +:c:type:`edac_device_block`, :c:type:`edac_device_instance` and +:c:type:`edac_device_ctl_info` provide a generic or abstract 'edac_device' +representation at sysfs. + +This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or +PCI, like: + +- CPU caches (L1 and L2) +- DMA engines +- Core CPU switches +- Fabric switch units +- PCIe interface controllers +- other EDAC/ECC type devices that can be monitored for + errors, etc. + +It allows for a 2 level set of hierarchy. + +For example, a cache could be composed of L1, L2 and L3 levels of cache. +Each CPU core would have its own L1 cache, while sharing L2 and maybe L3 +caches. On such case, those can be represented via the following sysfs +nodes:: + + /sys/devices/system/edac/.. + + pci/ + mc/ + cpu/cpu0/.. + /L1-cache/ce_count + /ue_count + /L2-cache/ce_count + /ue_count + cpu/cpu1/.. + /L1-cache/ce_count + /ue_count + /L2-cache/ce_count + /ue_count + ... + + the L1 and L2 directories would be "edac_device_block's" + +.. kernel-doc:: drivers/edac/edac_device.h diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst index a528178a54a5..5475a2807e7a 100644 --- a/Documentation/driver-api/index.rst +++ b/Documentation/driver-api/index.rst @@ -26,6 +26,7 @@ available subsections can be seen below. spi i2c hsi + edac miscellaneous vme 80211/index diff --git a/Documentation/driver-api/infrastructure.rst b/Documentation/driver-api/infrastructure.rst index 0bb0b5fc9512..6d9ff316b608 100644 --- a/Documentation/driver-api/infrastructure.rst +++ b/Documentation/driver-api/infrastructure.rst @@ -55,21 +55,6 @@ Device Drivers DMA Management .. kernel-doc:: drivers/base/dma-mapping.c :export: -Device Drivers Power Management -------------------------------- - -.. kernel-doc:: drivers/base/power/main.c - :export: - -Device Drivers ACPI Support ---------------------------- - -.. kernel-doc:: drivers/acpi/scan.c - :export: - -.. kernel-doc:: drivers/acpi/scan.c - :internal: - Device drivers PnP support -------------------------- diff --git a/Documentation/edac.txt b/Documentation/edac.txt deleted file mode 100644 index f89cfd85ae13..000000000000 --- a/Documentation/edac.txt +++ /dev/null @@ -1,812 +0,0 @@ -EDAC - Error Detection And Correction -===================================== - -"bluesmoke" was the name for this device driver when it -was "out-of-tree" and maintained at sourceforge.net - -bluesmoke.sourceforge.net. That site is mostly archaic now and can be -used only for historical purposes. - -When the subsystem was pushed into 2.6.16 for the first time, it was -renamed to 'EDAC'. - -PURPOSE -------- - -The 'edac' kernel module's goal is to detect and report hardware errors -that occur within the computer system running under linux. - -MEMORY ------- - -Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the -primary errors being harvested. These types of errors are harvested by -the 'edac_mc' device. - -Detecting CE events, then harvesting those events and reporting them, -*can* but must not necessarily be a predictor of future UE events. With -CE events only, the system can and will continue to operate as no data -has been damaged yet. - -However, preventive maintenance and proactive part replacement of memory -DIMMs exhibiting CEs can reduce the likelihood of the dreaded UE events -and system panics. - -OTHER HARDWARE ELEMENTS ------------------------ - -A new feature for EDAC, the edac_device class of device, was added in -the 2.6.23 version of the kernel. - -This new device type allows for non-memory type of ECC hardware detectors -to have their states harvested and presented to userspace via the sysfs -interface. - -Some architectures have ECC detectors for L1, L2 and L3 caches, -along with DMA engines, fabric switches, main data path switches, -interconnections, and various other hardware data paths. If the hardware -reports it, then a edac_device device probably can be constructed to -harvest and present that to userspace. - - -PCI BUS SCANNING ----------------- - -In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors -in order to determine if errors are occurring during data transfers. - -The presence of PCI Parity errors must be examined with a grain of salt. -There are several add-in adapters that do *not* follow the PCI specification -with regards to Parity generation and reporting. The specification says -the vendor should tie the parity status bits to 0 if they do not intend -to generate parity. Some vendors do not do this, and thus the parity bit -can "float" giving false positives. - -There is a PCI device attribute located in sysfs that is checked by -the EDAC PCI scanning code. If that attribute is set, PCI parity/error -scanning is skipped for that device. The attribute is: - - broken_parity_status - -and is located in /sys/devices/pci/0000:XX:YY.Z directories for -PCI devices. - - -VERSIONING ----------- - -EDAC is composed of a "core" module (edac_core.ko) and several Memory -Controller (MC) driver modules. On a given system, the CORE is loaded -and one MC driver will be loaded. Both the CORE and the MC driver (or -edac_device driver) have individual versions that reflect current -release level of their respective modules. - -Thus, to "report" on what version a system is running, one must report -both the CORE's and the MC driver's versions. - - -LOADING -------- - -If 'edac' was statically linked with the kernel then no loading -is necessary. If 'edac' was built as modules then simply modprobe -the 'edac' pieces that you need. You should be able to modprobe -hardware-specific modules and have the dependencies load the necessary -core modules. - -Example: - -$> modprobe amd76x_edac - -loads both the amd76x_edac.ko memory controller module and the edac_mc.ko -core module. - - -SYSFS INTERFACE ---------------- - -EDAC presents a 'sysfs' interface for control and reporting purposes. It -lives in the /sys/devices/system/edac directory. - -Within this directory there currently reside 2 components: - - mc memory controller(s) system - pci PCI control and status system - - - -Memory Controller (mc) Model ----------------------------- - -Each 'mc' device controls a set of DIMM memory modules. These modules -are laid out in a Chip-Select Row (csrowX) and Channel table (chX). -There can be multiple csrows and multiple channels. - -Memory controllers allow for several csrows, with 8 csrows being a -typical value. Yet, the actual number of csrows depends on the layout of -a given motherboard, memory controller and DIMM characteristics. - -Dual channels allows for 128 bit data transfers to/from the CPU from/to -memory. Some newer chipsets allow for more than 2 channels, like Fully -Buffered DIMMs (FB-DIMMs). The following example will assume 2 channels: - - - Channel 0 Channel 1 - =================================== - csrow0 | DIMM_A0 | DIMM_B0 | - csrow1 | DIMM_A0 | DIMM_B0 | - =================================== - - =================================== - csrow2 | DIMM_A1 | DIMM_B1 | - csrow3 | DIMM_A1 | DIMM_B1 | - =================================== - -In the above example table there are 4 physical slots on the motherboard -for memory DIMMs: - - DIMM_A0 - DIMM_B0 - DIMM_A1 - DIMM_B1 - -Labels for these slots are usually silk-screened on the motherboard. -Slots labeled 'A' are channel 0 in this example. Slots labeled 'B' are -channel 1. Notice that there are two csrows possible on a physical DIMM. -These csrows are allocated their csrow assignment based on the slot into -which the memory DIMM is placed. Thus, when 1 DIMM is placed in each -Channel, the csrows cross both DIMMs. - -Memory DIMMs come single or dual "ranked". A rank is a populated csrow. -Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above -will have 1 csrow, csrow0. csrow1 will be empty. On the other hand, -when 2 dual ranked DIMMs are similarly placed, then both csrow0 and -csrow1 will be populated. The pattern repeats itself for csrow2 and -csrow3. - -The representation of the above is reflected in the directory -tree in EDAC's sysfs interface. Starting in directory -/sys/devices/system/edac/mc each memory controller will be represented -by its own 'mcX' directory, where 'X' is the index of the MC. - - - ..../edac/mc/ - | - |->mc0 - |->mc1 - |->mc2 - .... - -Under each 'mcX' directory each 'csrowX' is again represented by a -'csrowX', where 'X' is the csrow index: - - - .../mc/mc0/ - | - |->csrow0 - |->csrow2 - |->csrow3 - .... - -Notice that there is no csrow1, which indicates that csrow0 is composed -of a single ranked DIMMs. This should also apply in both Channels, in -order to have dual-channel mode be operational. Since both csrow2 and -csrow3 are populated, this indicates a dual ranked set of DIMMs for -channels 0 and 1. - - -Within each of the 'mcX' and 'csrowX' directories are several EDAC -control and attribute files. - - -'mcX' directories ------------------ - -In 'mcX' directories are EDAC control and attribute files for -this 'X' instance of the memory controllers. - -For a description of the sysfs API, please see: - Documentation/ABI/testing/sysfs-devices-edac - - - -'csrowX' directories --------------------- - -When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the csrowX -directories. As this API doesn't work properly for Rambus, FB-DIMMs and -modern Intel Memory Controllers, this is being deprecated in favor of -dimmX directories. - -In the 'csrowX' directories are EDAC control and attribute files for -this 'X' instance of csrow: - - -Total Uncorrectable Errors count attribute file: - - 'ue_count' - - This attribute file displays the total count of uncorrectable - errors that have occurred on this csrow. If panic_on_ue is set - this counter will not have a chance to increment, since EDAC - will panic the system. - - -Total Correctable Errors count attribute file: - - 'ce_count' - - This attribute file displays the total count of correctable - errors that have occurred on this csrow. This count is very - important to examine. CEs provide early indications that a - DIMM is beginning to fail. This count field should be - monitored for non-zero values and report such information - to the system administrator. - - -Total memory managed by this csrow attribute file: - - 'size_mb' - - This attribute file displays, in count of megabytes, the memory - that this csrow contains. - - -Memory Type attribute file: - - 'mem_type' - - This attribute file will display what type of memory is currently - on this csrow. Normally, either buffered or unbuffered memory. - Examples: - Registered-DDR - Unbuffered-DDR - - -EDAC Mode of operation attribute file: - - 'edac_mode' - - This attribute file will display what type of Error detection - and correction is being utilized. - - -Device type attribute file: - - 'dev_type' - - This attribute file will display what type of DRAM device is - being utilized on this DIMM. - Examples: - x1 - x2 - x4 - x8 - - -Channel 0 CE Count attribute file: - - 'ch0_ce_count' - - This attribute file will display the count of CEs on this - DIMM located in channel 0. - - -Channel 0 UE Count attribute file: - - 'ch0_ue_count' - - This attribute file will display the count of UEs on this - DIMM located in channel 0. - - -Channel 0 DIMM Label control file: - - 'ch0_dimm_label' - - This control file allows this DIMM to have a label assigned - to it. With this label in the module, when errors occur - the output can provide the DIMM label in the system log. - This becomes vital for panic events to isolate the - cause of the UE event. - - DIMM Labels must be assigned after booting, with information - that correctly identifies the physical slot with its - silk screen label. This information is currently very - motherboard specific and determination of this information - must occur in userland at this time. - - -Channel 1 CE Count attribute file: - - 'ch1_ce_count' - - This attribute file will display the count of CEs on this - DIMM located in channel 1. - - -Channel 1 UE Count attribute file: - - 'ch1_ue_count' - - This attribute file will display the count of UEs on this - DIMM located in channel 0. - - -Channel 1 DIMM Label control file: - - 'ch1_dimm_label' - - This control file allows this DIMM to have a label assigned - to it. With this label in the module, when errors occur - the output can provide the DIMM label in the system log. - This becomes vital for panic events to isolate the - cause of the UE event. - - DIMM Labels must be assigned after booting, with information - that correctly identifies the physical slot with its - silk screen label. This information is currently very - motherboard specific and determination of this information - must occur in userland at this time. - - - -SYSTEM LOGGING --------------- - -If logging for UEs and CEs is enabled, then system logs will contain -information indicating that errors have been detected: - -EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, -channel 1 "DIMM_B1": amd76x_edac - -EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, -channel 1 "DIMM_B1": amd76x_edac - - -The structure of the message is: - the memory controller (MC0) - Error type (CE) - memory page (0x283) - offset in the page (0xce0) - the byte granularity (grain 8) - or resolution of the error - the error syndrome (0xb741) - memory row (row 0) - memory channel (channel 1) - DIMM label, if set prior (DIMM B1 - and then an optional, driver-specific message that may - have additional information. - -Both UEs and CEs with no info will lack all but memory controller, error -type, a notice of "no info" and then an optional, driver-specific error -message. - - -PCI Bus Parity Detection ------------------------- - -On Header Type 00 devices, the primary status is looked at for any -parity error regardless of whether parity is enabled on the device or -not. (The spec indicates parity is generated in some cases). On Header -Type 01 bridges, the secondary status register is also looked at to see -if parity occurred on the bus on the other side of the bridge. - - -SYSFS CONFIGURATION -------------------- - -Under /sys/devices/system/edac/pci are control and attribute files as follows: - - -Enable/Disable PCI Parity checking control file: - - 'check_pci_parity' - - - This control file enables or disables the PCI Bus Parity scanning - operation. Writing a 1 to this file enables the scanning. Writing - a 0 to this file disables the scanning. - - Enable: - echo "1" >/sys/devices/system/edac/pci/check_pci_parity - - Disable: - echo "0" >/sys/devices/system/edac/pci/check_pci_parity - - -Parity Count: - - 'pci_parity_count' - - This attribute file will display the number of parity errors that - have been detected. - - - -MODULE PARAMETERS ------------------ - -Panic on UE control file: - - 'edac_mc_panic_on_ue' - - An uncorrectable error will cause a machine panic. This is usually - desirable. It is a bad idea to continue when an uncorrectable error - occurs - it is indeterminate what was uncorrected and the operating - system context might be so mangled that continuing will lead to further - corruption. If the kernel has MCE configured, then EDAC will never - notice the UE. - - LOAD TIME: module/kernel parameter: edac_mc_panic_on_ue=[0|1] - - RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue - - -Log UE control file: - - 'edac_mc_log_ue' - - Generate kernel messages describing uncorrectable errors. These errors - are reported through the system message log system. UE statistics - will be accumulated even when UE logging is disabled. - - LOAD TIME: module/kernel parameter: edac_mc_log_ue=[0|1] - - RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue - - -Log CE control file: - - 'edac_mc_log_ce' - - Generate kernel messages describing correctable errors. These - errors are reported through the system message log system. - CE statistics will be accumulated even when CE logging is disabled. - - LOAD TIME: module/kernel parameter: edac_mc_log_ce=[0|1] - - RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce - - -Polling period control file: - - 'edac_mc_poll_msec' - - The time period, in milliseconds, for polling for error information. - Too small a value wastes resources. Too large a value might delay - necessary handling of errors and might loose valuable information for - locating the error. 1000 milliseconds (once each second) is the current - default. Systems which require all the bandwidth they can get, may - increase this. - - LOAD TIME: module/kernel parameter: edac_mc_poll_msec=[0|1] - - RUN TIME: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec - - -Panic on PCI PARITY Error: - - 'panic_on_pci_parity' - - - This control file enables or disables panicking when a parity - error has been detected. - - - module/kernel parameter: edac_panic_on_pci_pe=[0|1] - - Enable: - echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe - - Disable: - echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe - - - -EDAC device type ----------------- - -In the header file, edac_core.h, there is a series of edac_device structures -and APIs for the EDAC_DEVICE. - -User space access to an edac_device is through the sysfs interface. - -At the location /sys/devices/system/edac (sysfs) new edac_device devices will -appear. - -There is a three level tree beneath the above 'edac' directory. For example, -the 'test_device_edac' device (found at the bluesmoke.sourceforget.net website) -installs itself as: - - /sys/devices/systm/edac/test-instance - -in this directory are various controls, a symlink and one or more 'instance' -directories. - -The standard default controls are: - - log_ce boolean to log CE events - log_ue boolean to log UE events - panic_on_ue boolean to 'panic' the system if an UE is encountered - (default off, can be set true via startup script) - poll_msec time period between POLL cycles for events - -The test_device_edac device adds at least one of its own custom control: - - test_bits which in the current test driver does nothing but - show how it is installed. A ported driver can - add one or more such controls and/or attributes - for specific uses. - One out-of-tree driver uses controls here to allow - for ERROR INJECTION operations to hardware - injection registers - -The symlink points to the 'struct dev' that is registered for this edac_device. - -INSTANCES ---------- - -One or more instance directories are present. For the 'test_device_edac' case: - - test-instance0 - - -In this directory there are two default counter attributes, which are totals of -counter in deeper subdirectories. - - ce_count total of CE events of subdirectories - ue_count total of UE events of subdirectories - -BLOCKS ------- - -At the lowest directory level is the 'block' directory. There can be 0, 1 -or more blocks specified in each instance. - - test-block0 - - -In this directory the default attributes are: - - ce_count which is counter of CE events for this 'block' - of hardware being monitored - ue_count which is counter of UE events for this 'block' - of hardware being monitored - - -The 'test_device_edac' device adds 4 attributes and 1 control: - - test-block-bits-0 for every POLL cycle this counter - is incremented - test-block-bits-1 every 10 cycles, this counter is bumped once, - and test-block-bits-0 is set to 0 - test-block-bits-2 every 100 cycles, this counter is bumped once, - and test-block-bits-1 is set to 0 - test-block-bits-3 every 1000 cycles, this counter is bumped once, - and test-block-bits-2 is set to 0 - - - reset-counters writing ANY thing to this control will - reset all the above counters. - - -Use of the 'test_device_edac' driver should enable any others to create their own -unique drivers for their hardware systems. - -The 'test_device_edac' sample driver is located at the -bluesmoke.sourceforge.net project site for EDAC. - - -NEHALEM USAGE OF EDAC APIs --------------------------- - -This chapter documents some EXPERIMENTAL mappings for EDAC API to handle -Nehalem EDAC driver. They will likely be changed on future versions -of the driver. - -Due to the way Nehalem exports Memory Controller data, some adjustments -were done at i7core_edac driver. This chapter will cover those differences - -1) On Nehalem, there is one Memory Controller per Quick Patch Interconnect - (QPI). At the driver, the term "socket" means one QPI. This is - associated with a physical CPU socket. - - Each MC have 3 physical read channels, 3 physical write channels and - 3 logic channels. The driver currently sees it as just 3 channels. - Each channel can have up to 3 DIMMs. - - The minimum known unity is DIMMs. There are no information about csrows. - As EDAC API maps the minimum unity is csrows, the driver sequentially - maps channel/dimm into different csrows. - - For example, supposing the following layout: - Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs - dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 - dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400 - Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs - dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 - Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs - dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400 - The driver will map it as: - csrow0: channel 0, dimm0 - csrow1: channel 0, dimm1 - csrow2: channel 1, dimm0 - csrow3: channel 2, dimm0 - -exports one - DIMM per csrow. - - Each QPI is exported as a different memory controller. - -2) Nehalem MC has the ability to generate errors. The driver implements this - functionality via some error injection nodes: - - For injecting a memory error, there are some sysfs nodes, under - /sys/devices/system/edac/mc/mc?/: - - inject_addrmatch/*: - Controls the error injection mask register. It is possible to specify - several characteristics of the address to match an error code: - dimm = the affected dimm. Numbers are relative to a channel; - rank = the memory rank; - channel = the channel that will generate an error; - bank = the affected bank; - page = the page address; - column (or col) = the address column. - each of the above values can be set to "any" to match any valid value. - - At driver init, all values are set to any. - - For example, to generate an error at rank 1 of dimm 2, for any channel, - any bank, any page, any column: - echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm - echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank - - To return to the default behaviour of matching any, you can do: - echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm - echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank - - inject_eccmask: - specifies what bits will have troubles, - - inject_section: - specifies what ECC cache section will get the error: - 3 for both - 2 for the highest - 1 for the lowest - - inject_type: - specifies the type of error, being a combination of the following bits: - bit 0 - repeat - bit 1 - ecc - bit 2 - parity - - inject_enable starts the error generation when something different - than 0 is written. - - All inject vars can be read. root permission is needed for write. - - Datasheet states that the error will only be generated after a write on an - address that matches inject_addrmatch. It seems, however, that reading will - also produce an error. - - For example, the following code will generate an error for any write access - at socket 0, on any DIMM/address on channel 2: - - echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel - echo 2 >/sys/devices/system/edac/mc/mc0/inject_type - echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask - echo 3 >/sys/devices/system/edac/mc/mc0/inject_section - echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable - dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null - - For socket 1, it is needed to replace "mc0" by "mc1" at the above - commands. - - The generated error message will look like: - - EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error)) - -3) Nehalem specific Corrected Error memory counters - - Nehalem have some registers to count memory errors. The driver uses those - registers to report Corrected Errors on devices with Registered Dimms. - - However, those counters don't work with Unregistered Dimms. As the chipset - offers some counters that also work with UDIMMS (but with a worse level of - granularity than the default ones), the driver exposes those registers for - UDIMM memories. - - They can be read by looking at the contents of all_channel_counts/ - - $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done - /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0 - 0 - /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1 - 0 - /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2 - 0 - - What happens here is that errors on different csrows, but at the same - dimm number will increment the same counter. - So, in this memory mapping: - csrow0: channel 0, dimm0 - csrow1: channel 0, dimm1 - csrow2: channel 1, dimm0 - csrow3: channel 2, dimm0 - The hardware will increment udimm0 for an error at the first dimm at either - csrow0, csrow2 or csrow3; - The hardware will increment udimm1 for an error at the second dimm at either - csrow0, csrow2 or csrow3; - The hardware will increment udimm2 for an error at the third dimm at either - csrow0, csrow2 or csrow3; - -4) Standard error counters - - The standard error counters are generated when an mcelog error is received - by the driver. Since, with udimm, this is counted by software, it is - possible that some errors could be lost. With rdimm's, they display the - contents of the registers - -AMD64_EDAC REFERENCE DOCUMENTS USED ------------------------------------ -amd64_edac module is based on the following documents -(available from http://support.amd.com/en-us/search/tech-docs): - -1. Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD - Opteron Processors - AMD publication #: 26094 - Revision: 3.26 - Link: http://support.amd.com/TechDocs/26094.PDF - -2. Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh - Processors - AMD publication #: 32559 - Revision: 3.00 - Issue Date: May 2006 - Link: http://support.amd.com/TechDocs/32559.pdf - -3. Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h - Processors - AMD publication #: 31116 - Revision: 3.00 - Issue Date: September 07, 2007 - Link: http://support.amd.com/TechDocs/31116.pdf - -4. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h - Models 30h-3Fh Processors - AMD publication #: 49125 - Revision: 3.06 - Issue Date: 2/12/2015 (latest release) - Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf - -5. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h - Models 60h-6Fh Processors - AMD publication #: 50742 - Revision: 3.01 - Issue Date: 7/23/2015 (latest release) - Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf - -6. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h - Models 00h-0Fh Processors - AMD publication #: 48751 - Revision: 3.03 - Issue Date: 2/23/2015 (latest release) - Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf - -CREDITS: -======== - -Written by Doug Thompson -7 Dec 2005 -17 Jul 2007 Updated - -(c) Mauro Carvalho Chehab -05 Aug 2009 Nehalem interface - -EDAC authors/maintainers: - - Doug Thompson, Dave Jiang, Dave Peterson et al, - Mauro Carvalho Chehab - Borislav Petkov - original author: Thayne Harbaugh diff --git a/Documentation/features/io/dma-api-debug/arch-support.txt b/Documentation/features/io/dma-api-debug/arch-support.txt index 4f4a3443b114..ffa522a9bdfd 100644 --- a/Documentation/features/io/dma-api-debug/arch-support.txt +++ b/Documentation/features/io/dma-api-debug/arch-support.txt @@ -36,5 +36,5 @@ | um: | TODO | | unicore32: | TODO | | x86: | ok | - | xtensa: | TODO | + | xtensa: | ok | ----------------------- diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt index a97e8e3f4ebb..83d2cf989ea3 100644 --- a/Documentation/features/io/dma-contiguous/arch-support.txt +++ b/Documentation/features/io/dma-contiguous/arch-support.txt @@ -36,5 +36,5 @@ | um: | TODO | | unicore32: | TODO | | x86: | ok | - | xtensa: | TODO | + | xtensa: | ok | ----------------------- diff --git a/Documentation/features/io/sg-chain/arch-support.txt b/Documentation/features/io/sg-chain/arch-support.txt index b9b675539b9d..6ca98f9911bb 100644 --- a/Documentation/features/io/sg-chain/arch-support.txt +++ b/Documentation/features/io/sg-chain/arch-support.txt @@ -7,7 +7,7 @@ | arch |status| ----------------------- | alpha: | TODO | - | arc: | TODO | + | arc: | ok | | arm: | ok | | arm64: | ok | | avr32: | TODO | diff --git a/Documentation/filesystems/00-INDEX b/Documentation/filesystems/00-INDEX index f66e748fc5e4..b7bd6c9009cc 100644 --- a/Documentation/filesystems/00-INDEX +++ b/Documentation/filesystems/00-INDEX @@ -87,8 +87,6 @@ jfs.txt - info and mount options for the JFS filesystem. locks.txt - info on file locking implementations, flock() vs. fcntl(), etc. -logfs.txt - - info on the LogFS flash filesystem. mandatory-locking.txt - info on the Linux implementation of Sys V mandatory file locking. ncpfs.txt diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 1b5f15653b1b..ace63cd7af8c 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -20,7 +20,7 @@ prototypes: void (*d_iput)(struct dentry *, struct inode *); char *(*d_dname)((struct dentry *dentry, char *buffer, int buflen); struct vfsmount *(*d_automount)(struct path *path); - int (*d_manage)(struct dentry *, bool); + int (*d_manage)(const struct path *, bool); struct dentry *(*d_real)(struct dentry *, const struct inode *, unsigned int); @@ -556,7 +556,7 @@ till "end_pgoff". ->map_pages() is called with page table locked and must not block. If it's not possible to reach a page without blocking, filesystem should skip it. Filesystem should use do_set_pte() to setup page table entry. Pointer to entry associated with the page is passed in -"pte" field in fault_env structure. Pointers to entries for other offsets +"pte" field in vm_fault structure. Pointers to entries for other offsets should be calculated relative to "pte". ->page_mkwrite() is called when a previously read-only pte is diff --git a/Documentation/filesystems/logfs.txt b/Documentation/filesystems/logfs.txt deleted file mode 100644 index bca42c22a143..000000000000 --- a/Documentation/filesystems/logfs.txt +++ /dev/null @@ -1,241 +0,0 @@ - -The LogFS Flash Filesystem -========================== - -Specification -============= - -Superblocks ------------ - -Two superblocks exist at the beginning and end of the filesystem. -Each superblock is 256 Bytes large, with another 3840 Bytes reserved -for future purposes, making a total of 4096 Bytes. - -Superblock locations may differ for MTD and block devices. On MTD the -first non-bad block contains a superblock in the first 4096 Bytes and -the last non-bad block contains a superblock in the last 4096 Bytes. -On block devices, the first 4096 Bytes of the device contain the first -superblock and the last aligned 4096 Byte-block contains the second -superblock. - -For the most part, the superblocks can be considered read-only. They -are written only to correct errors detected within the superblocks, -move the journal and change the filesystem parameters through tunefs. -As a result, the superblock does not contain any fields that require -constant updates, like the amount of free space, etc. - -Segments --------- - -The space in the device is split up into equal-sized segments. -Segments are the primary write unit of LogFS. Within each segments, -writes happen from front (low addresses) to back (high addresses. If -only a partial segment has been written, the segment number, the -current position within and optionally a write buffer are stored in -the journal. - -Segments are erased as a whole. Therefore Garbage Collection may be -required to completely free a segment before doing so. - -Journal --------- - -The journal contains all global information about the filesystem that -is subject to frequent change. At mount time, it has to be scanned -for the most recent commit entry, which contains a list of pointers to -all currently valid entries. - -Object Store ------------- - -All space except for the superblocks and journal is part of the object -store. Each segment contains a segment header and a number of -objects, each consisting of the object header and the payload. -Objects are either inodes, directory entries (dentries), file data -blocks or indirect blocks. - -Levels ------- - -Garbage collection (GC) may fail if all data is written -indiscriminately. One requirement of GC is that data is separated -roughly according to the distance between the tree root and the data. -Effectively that means all file data is on level 0, indirect blocks -are on levels 1, 2, 3 4 or 5 for 1x, 2x, 3x, 4x or 5x indirect blocks, -respectively. Inode file data is on level 6 for the inodes and 7-11 -for indirect blocks. - -Each segment contains objects of a single level only. As a result, -each level requires its own separate segment to be open for writing. - -Inode File ----------- - -All inodes are stored in a special file, the inode file. Single -exception is the inode file's inode (master inode) which for obvious -reasons is stored in the journal instead. Instead of data blocks, the -leaf nodes of the inode files are inodes. - -Aliases -------- - -Writes in LogFS are done by means of a wandering tree. A naïve -implementation would require that for each write or a block, all -parent blocks are written as well, since the block pointers have -changed. Such an implementation would not be very efficient. - -In LogFS, the block pointer changes are cached in the journal by means -of alias entries. Each alias consists of its logical address - inode -number, block index, level and child number (index into block) - and -the changed data. Any 8-byte word can be changes in this manner. - -Currently aliases are used for block pointers, file size, file used -bytes and the height of an inodes indirect tree. - -Segment Aliases ---------------- - -Related to regular aliases, these are used to handle bad blocks. -Initially, bad blocks are handled by moving the affected segment -content to a spare segment and noting this move in the journal with a -segment alias, a simple (to, from) tupel. GC will later empty this -segment and the alias can be removed again. This is used on MTD only. - -Vim ---- - -By cleverly predicting the life time of data, it is possible to -separate long-living data from short-living data and thereby reduce -the GC overhead later. Each type of distinc life expectency (vim) can -have a separate segment open for writing. Each (level, vim) tupel can -be open just once. If an open segment with unknown vim is encountered -at mount time, it is closed and ignored henceforth. - -Indirect Tree -------------- - -Inodes in LogFS are similar to FFS-style filesystems with direct and -indirect block pointers. One difference is that LogFS uses a single -indirect pointer that can be either a 1x, 2x, etc. indirect pointer. -A height field in the inode defines the height of the indirect tree -and thereby the indirection of the pointer. - -Another difference is the addressing of indirect blocks. In LogFS, -the first 16 pointers in the first indirect block are left empty, -corresponding to the 16 direct pointers in the inode. In ext2 (maybe -others as well) the first pointer in the first indirect block -corresponds to logical block 12, skipping the 12 direct pointers. -So where ext2 is using arithmetic to better utilize space, LogFS keeps -arithmetic simple and uses compression to save space. - -Compression ------------ - -Both file data and metadata can be compressed. Compression for file -data can be enabled with chattr +c and disabled with chattr -c. Doing -so has no effect on existing data, but new data will be stored -accordingly. New inodes will inherit the compression flag of the -parent directory. - -Metadata is always compressed. However, the space accounting ignores -this and charges for the uncompressed size. Failing to do so could -result in GC failures when, after moving some data, indirect blocks -compress worse than previously. Even on a 100% full medium, GC may -not consume any extra space, so the compression gains are lost space -to the user. - -However, they are not lost space to the filesystem internals. By -cheating the user for those bytes, the filesystem gained some slack -space and GC will run less often and faster. - -Garbage Collection and Wear Leveling ------------------------------------- - -Garbage collection is invoked whenever the number of free segments -falls below a threshold. The best (known) candidate is picked based -on the least amount of valid data contained in the segment. All -remaining valid data is copied elsewhere, thereby invalidating it. - -The GC code also checks for aliases and writes then back if their -number gets too large. - -Wear leveling is done by occasionally picking a suboptimal segment for -garbage collection. If a stale segments erase count is significantly -lower than the active segments' erase counts, it will be picked. Wear -leveling is rate limited, so it will never monopolize the device for -more than one segment worth at a time. - -Values for "occasionally", "significantly lower" are compile time -constants. - -Hashed directories ------------------- - -To satisfy efficient lookup(), directory entries are hashed and -located based on the hash. In order to both support large directories -and not be overly inefficient for small directories, several hash -tables of increasing size are used. For each table, the hash value -modulo the table size gives the table index. - -Tables sizes are chosen to limit the number of indirect blocks with a -fully populated table to 0, 1, 2 or 3 respectively. So the first -table contains 16 entries, the second 512-16, etc. - -The last table is special in several ways. First its size depends on -the effective 32bit limit on telldir/seekdir cookies. Since logfs -uses the upper half of the address space for indirect blocks, the size -is limited to 2^31. Secondly the table contains hash buckets with 16 -entries each. - -Using single-entry buckets would result in birthday "attacks". At -just 2^16 used entries, hash collisions would be likely (P >= 0.5). -My math skills are insufficient to do the combinatorics for the 17x -collisions necessary to overflow a bucket, but testing showed that in -10,000 runs the lowest directory fill before a bucket overflow was -188,057,130 entries with an average of 315,149,915 entries. So for -directory sizes of up to a million, bucket overflows should be -virtually impossible under normal circumstances. - -With carefully chosen filenames, it is obviously possible to cause an -overflow with just 21 entries (4 higher tables + 16 entries + 1). So -there may be a security concern if a malicious user has write access -to a directory. - -Open For Discussion -=================== - -Device Address Space --------------------- - -A device address space is used for caching. Both block devices and -MTD provide functions to either read a single page or write a segment. -Partial segments may be written for data integrity, but where possible -complete segments are written for performance on simple block device -flash media. - -Meta Inodes ------------ - -Inodes are stored in the inode file, which is just a regular file for -most purposes. At umount time, however, the inode file needs to -remain open until all dirty inodes are written. So -generic_shutdown_super() may not close this inode, but shouldn't -complain about remaining inodes due to the inode file either. Same -goes for mapping inode of the device address space. - -Currently logfs uses a hack that essentially copies part of fs/inode.c -code over. A general solution would be preferred. - -Indirect block mapping ----------------------- - -With compression, the block device (or mapping inode) cannot be used -to cache indirect blocks. Some other place is required. Currently -logfs uses the top half of each inode's address space. The low 8TB -(on 32bit) are filled with file data, the high 8TB are used for -indirect blocks. - -One problem is that 16TB files created on 64bit systems actually have -data in the top 8TB. But files >16TB would cause problems anyway, so -only the limit has changed. diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt index bcbf9710e4af..634d03e20c2d 100644 --- a/Documentation/filesystems/overlayfs.txt +++ b/Documentation/filesystems/overlayfs.txt @@ -66,7 +66,7 @@ At mount time, the two directories given as mount options "lowerdir" and "upperdir" are combined into a merged directory: mount -t overlay overlay -olowerdir=/lower,upperdir=/upper,\ -workdir=/work /merged + workdir=/work /merged The "workdir" needs to be an empty directory on the same filesystem as upperdir. @@ -118,6 +118,7 @@ programs. seek offsets are assigned sequentially when the directories are read. Thus if + - read part of a directory - remember an offset, and close the directory - re-open the directory some time later @@ -130,6 +131,23 @@ directory. Readdir on directories that are not merged is simply handled by the underlying directory (upper or lower). +renaming directories +-------------------- + +When renaming a directory that is on the lower layer or merged (i.e. the +directory was not created on the upper layer to start with) overlayfs can +handle it in two different ways: + +1. return EXDEV error: this error is returned by rename(2) when trying to + move a file or directory across filesystem boundaries. Hence + applications are usually prepared to hande this error (mv(1) for example + recursively copies the directory tree). This is the default behavior. + +2. If the "redirect_dir" feature is enabled, then the directory will be + copied up (but not the contents). Then the "trusted.overlay.redirect" + extended attribute is set to the path of the original location from the + root of the overlay. Finally the directory is moved to the new + location. Non-directories --------------- @@ -185,13 +203,13 @@ filesystem, so both st_dev and st_ino of the file may change. Any open files referring to this inode will access the old data. -Any file locks (and leases) obtained before copy_up will not apply -to the copied up file. - If a file with multiple hard links is copied up, then this will "break" the link. Changes will not be propagated to other names referring to the same inode. +Unless "redirect_dir" feature is enabled, rename(2) on a lower or merged +directory will fail with EXDEV. + Changes to underlying filesystems --------------------------------- diff --git a/Documentation/filesystems/porting b/Documentation/filesystems/porting index bdd025ceb763..95280079c0b3 100644 --- a/Documentation/filesystems/porting +++ b/Documentation/filesystems/porting @@ -596,3 +596,7 @@ in your dentry operations instead. [mandatory] ->rename() has an added flags argument. Any flags not handled by the filesystem should result in EINVAL being returned. +-- +[recommended] + ->readlink is optional for symlinks. Don't set, unless filesystem needs + to fake something for readlink(2). diff --git a/Documentation/filesystems/sysfs-pci.txt b/Documentation/filesystems/sysfs-pci.txt index 74eaac26f8b8..6ea1ceda6f52 100644 --- a/Documentation/filesystems/sysfs-pci.txt +++ b/Documentation/filesystems/sysfs-pci.txt @@ -17,6 +17,7 @@ that support it. For example, a given bus might look like this: | |-- resource0 | |-- resource1 | |-- resource2 + | |-- revision | |-- rom | |-- subsystem_device | |-- subsystem_vendor @@ -41,6 +42,7 @@ files, each with their own function. resource PCI resource host addresses (ascii, ro) resource0..N PCI resource N, if present (binary, mmap, rw[1]) resource0_wc..N_wc PCI WC map resource N, if prefetchable (binary, mmap) + revision PCI revision (ascii, ro) rom PCI ROM resource, if present (binary, ro) subsystem_device PCI subsystem device (ascii, ro) subsystem_vendor PCI subsystem vendor (ascii, ro) diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index b5039a00caaf..b968084eeac1 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -451,9 +451,6 @@ otherwise noted. exist; this is checked by the VFS. Unlike plain rename, source and target may be of different type. - readlink: called by the readlink(2) system call. Only required if - you want to support reading symbolic links - get_link: called by the VFS to follow a symbolic link to the inode it points to. Only required if you want to support symbolic links. This method returns the symlink body @@ -468,6 +465,12 @@ otherwise noted. argument. If request can't be handled without leaving RCU mode, have it return ERR_PTR(-ECHILD). + readlink: this is now just an override for use by readlink(2) for the + cases when ->get_link uses nd_jump_link() or object is not in + fact a symlink. Normally filesystems should only implement + ->get_link for symlinks and readlink(2) will automatically use + that. + permission: called by the VFS to check for access rights on a POSIX-like filesystem. @@ -948,7 +951,7 @@ struct dentry_operations { void (*d_iput)(struct dentry *, struct inode *); char *(*d_dname)(struct dentry *, char *, int); struct vfsmount *(*d_automount)(struct path *); - int (*d_manage)(struct dentry *, bool); + int (*d_manage)(const struct path *, bool); struct dentry *(*d_real)(struct dentry *, const struct inode *, unsigned int); }; diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt index c2d44e6e117b..3b9b5c149f32 100644 --- a/Documentation/filesystems/xfs.txt +++ b/Documentation/filesystems/xfs.txt @@ -51,13 +51,6 @@ default behaviour. CRC enabled filesystems always use the attr2 format, and so will reject the noattr2 mount option if it is set. - barrier (*) - nobarrier - Enables/disables the use of block layer write barriers for - writes into the journal and for data integrity operations. - This allows for drive level write caching to be enabled, for - devices that support write barriers. - discard nodiscard (*) Enable/disable the issuing of commands to let the block @@ -228,7 +221,10 @@ default behaviour. Deprecated Mount Options ======================== -None at present. + Name Removal Schedule + ---- ---------------- + barrier no earlier than v4.15 + nobarrier no earlier than v4.15 Removed Mount Options diff --git a/Documentation/i2c/busses/i2c-mlxcpld b/Documentation/i2c/busses/i2c-mlxcpld new file mode 100644 index 000000000000..4e46c440b38d --- /dev/null +++ b/Documentation/i2c/busses/i2c-mlxcpld @@ -0,0 +1,47 @@ +Driver i2c-mlxcpld + +Author: Michael Shych + +This is the Mellanox I2C controller logic, implemented in Lattice CPLD +device. +Device supports: + - Master mode. + - One physical bus. + - Polling mode. + +This controller is equipped within the next Mellanox systems: +"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", +"msn2740", "msn2100". + +The next transaction types are supported: + - Receive Byte/Block. + - Send Byte/Block. + - Read Byte/Block. + - Write Byte/Block. + +Registers: +CTRL 0x1 - control reg. + Resets all the registers. +HALF_CYC 0x4 - cycle reg. + Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK + units). +I2C_HOLD 0x5 - hold reg. + OE (output enable) is delayed by value set to this register + (in LPC_CLK units) +CMD 0x6 - command reg. + Bit 0, 0 = write, 1 = read. + Bits [7:1] - the 7bit Address of the I2C device. + It should be written last as it triggers an I2C transaction. +NUM_DATA 0x7 - data size reg. + Number of data bytes to write in read transaction +NUM_ADDR 0x8 - address reg. + Number of address bytes to write in read transaction. +STATUS 0x9 - status reg. + Bit 0 - transaction is completed. + Bit 4 - ACK/NACK. +DATAx 0xa - 0x54 - 68 bytes data buffer regs. + For write transaction address is specified in four first bytes + (DATA1 - DATA4), data starting from DATA4. + For read transactions address is sent in a separate transaction and + specified in the four first bytes (DATA0 - DATA3). Data is read + starting from DATA0. diff --git a/Documentation/i2c/smbus-protocol b/Documentation/i2c/smbus-protocol index 14d4ec1be245..092d474f5843 100644 --- a/Documentation/i2c/smbus-protocol +++ b/Documentation/i2c/smbus-protocol @@ -200,10 +200,14 @@ alerting device's address. [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P] This is implemented in the following way in the Linux kernel: -* I2C bus drivers which support SMBus Host Notify should call - i2c_setup_smbus_host_notify() to setup SMBus Host Notify support. -* I2C drivers for devices which can trigger SMBus Host Notify should implement - the optional alert() callback. +* I2C bus drivers which support SMBus Host Notify should report + I2C_FUNC_SMBUS_HOST_NOTIFY. +* I2C bus drivers trigger SMBus Host Notify by a call to + i2c_handle_smbus_host_notify(). +* I2C drivers for devices which can trigger SMBus Host Notify will have + client->irq assigned to a Host Notify IRQ if noone else specified an other. + +There is currently no way to retrieve the data parameter from the client. Packet Error Checking (PEC) diff --git a/Documentation/index.rst b/Documentation/index.rst index 2bd8fdc9207c..cb5d77699c60 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -58,6 +58,7 @@ needed). gpu/index security/index sound/index + crypto/index Korean translations ------------------- diff --git a/Documentation/laptops/thinkpad-acpi.txt b/Documentation/laptops/thinkpad-acpi.txt index 72a150d8f3df..ba2e7d254842 100644 --- a/Documentation/laptops/thinkpad-acpi.txt +++ b/Documentation/laptops/thinkpad-acpi.txt @@ -540,6 +540,7 @@ Events that are propagated by the driver to userspace: 0x6022 ALARM: a sensor is extremely hot 0x6030 System thermal table changed 0x6040 Nvidia Optimus/AC adapter related (TO BE VERIFIED) +0x60C0 X1 Yoga 2016, Tablet mode status changed Battery nearly empty alarms are a last resort attempt to get the operating system to hibernate or shutdown cleanly (0x2313), or shutdown diff --git a/Documentation/livepatch/livepatch.txt b/Documentation/livepatch/livepatch.txt index 6c43f6ebee8d..f5967316deb9 100644 --- a/Documentation/livepatch/livepatch.txt +++ b/Documentation/livepatch/livepatch.txt @@ -87,7 +87,7 @@ The theory about how to apply functions a safe way is rather complex. The aim is to define a so-called consistency model. It attempts to define conditions when the new implementation could be used so that the system stays consistent. The theory is not yet finished. See the discussion at -http://thread.gmane.org/gmane.linux.kernel/1823033/focus=1828189 +https://lkml.kernel.org/r/20141107140458.GA21774@suse.cz The current consistency model is very simple. It guarantees that either the old or the new function is called. But various functions get redirected diff --git a/Documentation/media/Makefile b/Documentation/media/Makefile index 4d8e2ff378c4..32663602ff25 100644 --- a/Documentation/media/Makefile +++ b/Documentation/media/Makefile @@ -88,7 +88,7 @@ $(BUILDDIR)/videodev2.h.rst: ${UAPI}/videodev2.h ${PARSER} $(SRC_DIR)/videodev2. $(BUILDDIR)/media.h.rst: ${UAPI}/media.h ${PARSER} $(SRC_DIR)/media.h.rst.exceptions @$($(quiet)gen_rst) -$(BUILDDIR)/cec.h.rst: ${KAPI}/cec.h ${PARSER} $(SRC_DIR)/cec.h.rst.exceptions +$(BUILDDIR)/cec.h.rst: ${UAPI}/cec.h ${PARSER} $(SRC_DIR)/cec.h.rst.exceptions @$($(quiet)gen_rst) $(BUILDDIR)/lirc.h.rst: ${UAPI}/lirc.h ${PARSER} $(SRC_DIR)/lirc.h.rst.exceptions diff --git a/Documentation/media/kapi/cec-core.rst b/Documentation/media/kapi/cec-core.rst index 88c33b53ec13..81c6d8e93774 100644 --- a/Documentation/media/kapi/cec-core.rst +++ b/Documentation/media/kapi/cec-core.rst @@ -37,9 +37,8 @@ The struct cec_adapter represents the CEC adapter hardware. It is created by calling cec_allocate_adapter() and deleted by calling cec_delete_adapter(): .. c:function:: - struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, - void *priv, const char *name, u32 caps, u8 available_las, - struct device *parent); + struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, void *priv, + const char *name, u32 caps, u8 available_las); .. c:function:: void cec_delete_adapter(struct cec_adapter *adap); @@ -66,20 +65,19 @@ available_las: the number of simultaneous logical addresses that this adapter can handle. Must be 1 <= available_las <= CEC_MAX_LOG_ADDRS. -parent: - the parent device. - To register the /dev/cecX device node and the remote control device (if CEC_CAP_RC is set) you call: .. c:function:: - int cec_register_adapter(struct cec_adapter \*adap); + int cec_register_adapter(struct cec_adapter *adap, struct device *parent); + +where parent is the parent device. To unregister the devices call: .. c:function:: - void cec_unregister_adapter(struct cec_adapter \*adap); + void cec_unregister_adapter(struct cec_adapter *adap); Note: if cec_register_adapter() fails, then call cec_delete_adapter() to clean up. But if cec_register_adapter() succeeded, then only call @@ -106,13 +104,13 @@ your driver: int (*adap_log_addr)(struct cec_adapter *adap, u8 logical_addr); int (*adap_transmit)(struct cec_adapter *adap, u8 attempts, u32 signal_free_time, struct cec_msg *msg); - void (\*adap_log_status)(struct cec_adapter *adap); + void (*adap_status)(struct cec_adapter *adap, struct seq_file *file); /* High-level callbacks */ ... }; -The three low-level ops deal with various aspects of controlling the CEC adapter +The five low-level ops deal with various aspects of controlling the CEC adapter hardware: @@ -238,6 +236,18 @@ When a CEC message was received: Speaks for itself. +Implementing the interrupt handler +---------------------------------- + +Typically the CEC hardware provides interrupts that signal when a transmit +finished and whether it was successful or not, and it provides and interrupt +when a CEC message was received. + +The CEC driver should always process the transmit interrupts first before +handling the receive interrupt. The framework expects to see the cec_transmit_done +call before the cec_received_msg call, otherwise it can get confused if the +received message was in reply to the transmitted message. + Implementing the High-Level CEC Adapter --------------------------------------- @@ -247,11 +257,11 @@ CEC protocol driven. The following high-level callbacks are available: .. code-block:: none struct cec_adap_ops { - /\* Low-level callbacks \*/ + /* Low-level callbacks */ ... - /\* High-level CEC message callback \*/ - int (\*received)(struct cec_adapter \*adap, struct cec_msg \*msg); + /* High-level CEC message callback */ + int (*received)(struct cec_adapter *adap, struct cec_msg *msg); }; The received() callback allows the driver to optionally handle a newly @@ -263,7 +273,7 @@ received CEC message If the driver wants to process a CEC message, then it can implement this callback. If it doesn't want to handle this message, then it should return -ENOMSG, otherwise the CEC framework assumes it processed this message and -it will not no anything with it. +it will not do anything with it. CEC framework functions diff --git a/Documentation/media/kapi/csi2.rst b/Documentation/media/kapi/csi2.rst new file mode 100644 index 000000000000..2004db00b12b --- /dev/null +++ b/Documentation/media/kapi/csi2.rst @@ -0,0 +1,61 @@ +MIPI CSI-2 +========== + +CSI-2 is a data bus intended for transferring images from cameras to +the host SoC. It is defined by the `MIPI alliance`_. + +.. _`MIPI alliance`: http://www.mipi.org/ + +Transmitter drivers +------------------- + +CSI-2 transmitter, such as a sensor or a TV tuner, drivers need to +provide the CSI-2 receiver with information on the CSI-2 bus +configuration. These include the V4L2_CID_LINK_FREQ and +V4L2_CID_PIXEL_RATE controls and +(:c:type:`v4l2_subdev_video_ops`->s_stream() callback). These +interface elements must be present on the sub-device represents the +CSI-2 transmitter. + +The V4L2_CID_LINK_FREQ control is used to tell the receiver driver the +frequency (and not the symbol rate) of the link. The +V4L2_CID_PIXEL_RATE is may be used by the receiver to obtain the pixel +rate the transmitter uses. The +:c:type:`v4l2_subdev_video_ops`->s_stream() callback provides an +ability to start and stop the stream. + +The value of the V4L2_CID_PIXEL_RATE is calculated as follows:: + + pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample + +where + +.. list-table:: variables in pixel rate calculation + :header-rows: 1 + + * - variable or constant + - description + * - link_freq + - The value of the V4L2_CID_LINK_FREQ integer64 menu item. + * - nr_of_lanes + - Number of data lanes used on the CSI-2 link. This can + be obtained from the OF endpoint configuration. + * - 2 + - Two bits are transferred per clock cycle per lane. + * - bits_per_sample + - Number of bits per sample. + +The transmitter drivers must configure the CSI-2 transmitter to *LP-11 +mode* whenever the transmitter is powered on but not active. Some +transmitters do this automatically but some have to be explicitly +programmed to do so. + +Receiver drivers +---------------- + +Before the receiver driver may enable the CSI-2 transmitter by using +the :c:type:`v4l2_subdev_video_ops`->s_stream(), it must have powered +the transmitter up by using the +:c:type:`v4l2_subdev_core_ops`->s_power() callback. This may take +place either indirectly by using :c:func:`v4l2_pipeline_pm_use` or +directly. diff --git a/Documentation/media/kapi/dtv-core.rst b/Documentation/media/kapi/dtv-core.rst index a3c4642eabfc..ff86bf0abeae 100644 --- a/Documentation/media/kapi/dtv-core.rst +++ b/Documentation/media/kapi/dtv-core.rst @@ -8,14 +8,6 @@ Digital TV Common functions .. kernel-doc:: drivers/media/dvb-core/dvbdev.h - - -.. kernel-doc:: drivers/media/dvb-core/dvb_math.h - :export: drivers/media/dvb-core/dvb_math.c - -.. kernel-doc:: drivers/media/dvb-core/dvbdev.h - :export: drivers/media/dvb-core/dvbdev.c - Digital TV Ring buffer ---------------------- diff --git a/Documentation/media/media_kapi.rst b/Documentation/media/media_kapi.rst index f282ca270369..bc0638956a43 100644 --- a/Documentation/media/media_kapi.rst +++ b/Documentation/media/media_kapi.rst @@ -33,3 +33,4 @@ For more details see the file COPYING in the source distribution of Linux. kapi/rc-core kapi/mc-core kapi/cec-core + kapi/csi2 diff --git a/Documentation/media/typical_media_device.svg b/Documentation/media/typical_media_device.svg index f0c82f72c4b6..0c8abd69f39a 100644 --- a/Documentation/media/typical_media_device.svg +++ b/Documentation/media/typical_media_device.svg @@ -1,28 +1,2948 @@ -Audio decoder -Video decoder -Audio encoder -Button Key/IR input logic -EEPROM -Sensor -System Bus -Demux -Conditional Access Module -Video encoder -Radio / Analog TV -Digital TV -PS.: picture is not complete: other blocks may be present -Webcam -Processing blocks -Smartcard -TunerFM/TV -Satellite Equipment Control (SEC) -Demod -I2C Bus (control bus) -Digital TV Frontend - -CPU -PCI, USB, SPI, I2C, ... -Bridge - DMA - +image/svg+xmlAudio decoder +Video decoder +Audio encoder +Button Key/IR input logic +EEPROM +Sensor +System Bus +Demux +Conditional Access Module +Video encoder +Radio / Analog TV +Digital TV +PS.: picture is not complete: other blocks may be present +Webcam +Processing blocks +Smartcard +TunerFM/TV +Satellite Equipment Control (SEC) +Demod +I2C Bus (control bus) +Digital TV Frontend + +CPU +PCI, USB, SPI, I2C, ... +Bridge + DMA + \ No newline at end of file diff --git a/Documentation/media/uapi/cec/cec-ioc-adap-g-caps.rst b/Documentation/media/uapi/cec/cec-ioc-adap-g-caps.rst index a35dca281178..2b0ddb14b280 100644 --- a/Documentation/media/uapi/cec/cec-ioc-adap-g-caps.rst +++ b/Documentation/media/uapi/cec/cec-ioc-adap-g-caps.rst @@ -48,41 +48,21 @@ returns the information to the application. The ioctl never fails. :stub-columns: 0 :widths: 1 1 16 - - - .. row 1 - - - char - - - ``driver[32]`` - - - The name of the cec adapter driver. - - - .. row 2 - - - char - - - ``name[32]`` - - - The name of this CEC adapter. The combination ``driver`` and - ``name`` must be unique. - - - .. row 3 - - - __u32 - - - ``capabilities`` - - - The capabilities of the CEC adapter, see - :ref:`cec-capabilities`. - - - .. row 4 - - - __u32 - - - ``version`` - - - CEC Framework API version, formatted with the ``KERNEL_VERSION()`` - macro. + * - char + - ``driver[32]`` + - The name of the cec adapter driver. + * - char + - ``name[32]`` + - The name of this CEC adapter. The combination ``driver`` and + ``name`` must be unique. + * - __u32 + - ``capabilities`` + - The capabilities of the CEC adapter, see + :ref:`cec-capabilities`. + * - __u32 + - ``version`` + - CEC Framework API version, formatted with the ``KERNEL_VERSION()`` + macro. .. tabularcolumns:: |p{4.4cm}|p{2.5cm}|p{10.6cm}| @@ -94,68 +74,50 @@ returns the information to the application. The ioctl never fails. :stub-columns: 0 :widths: 3 1 8 + * .. _`CEC-CAP-PHYS-ADDR`: - - .. _`CEC-CAP-PHYS-ADDR`: + - ``CEC_CAP_PHYS_ADDR`` + - 0x00000001 + - Userspace has to configure the physical address by calling + :ref:`ioctl CEC_ADAP_S_PHYS_ADDR `. If + this capability isn't set, then setting the physical address is + handled by the kernel whenever the EDID is set (for an HDMI + receiver) or read (for an HDMI transmitter). + * .. _`CEC-CAP-LOG-ADDRS`: - - ``CEC_CAP_PHYS_ADDR`` + - ``CEC_CAP_LOG_ADDRS`` + - 0x00000002 + - Userspace has to configure the logical addresses by calling + :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. If + this capability isn't set, then the kernel will have configured + this. + * .. _`CEC-CAP-TRANSMIT`: - - 0x00000001 + - ``CEC_CAP_TRANSMIT`` + - 0x00000004 + - Userspace can transmit CEC messages by calling + :ref:`ioctl CEC_TRANSMIT `. This implies that + userspace can be a follower as well, since being able to transmit + messages is a prerequisite of becoming a follower. If this + capability isn't set, then the kernel will handle all CEC + transmits and process all CEC messages it receives. + * .. _`CEC-CAP-PASSTHROUGH`: - - Userspace has to configure the physical address by calling - :ref:`ioctl CEC_ADAP_S_PHYS_ADDR `. If - this capability isn't set, then setting the physical address is - handled by the kernel whenever the EDID is set (for an HDMI - receiver) or read (for an HDMI transmitter). + - ``CEC_CAP_PASSTHROUGH`` + - 0x00000008 + - Userspace can use the passthrough mode by calling + :ref:`ioctl CEC_S_MODE `. + * .. _`CEC-CAP-RC`: - - .. _`CEC-CAP-LOG-ADDRS`: + - ``CEC_CAP_RC`` + - 0x00000010 + - This adapter supports the remote control protocol. + * .. _`CEC-CAP-MONITOR-ALL`: - - ``CEC_CAP_LOG_ADDRS`` - - - 0x00000002 - - - Userspace has to configure the logical addresses by calling - :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. If - this capability isn't set, then the kernel will have configured - this. - - - .. _`CEC-CAP-TRANSMIT`: - - - ``CEC_CAP_TRANSMIT`` - - - 0x00000004 - - - Userspace can transmit CEC messages by calling - :ref:`ioctl CEC_TRANSMIT `. This implies that - userspace can be a follower as well, since being able to transmit - messages is a prerequisite of becoming a follower. If this - capability isn't set, then the kernel will handle all CEC - transmits and process all CEC messages it receives. - - - .. _`CEC-CAP-PASSTHROUGH`: - - - ``CEC_CAP_PASSTHROUGH`` - - - 0x00000008 - - - Userspace can use the passthrough mode by calling - :ref:`ioctl CEC_S_MODE `. - - - .. _`CEC-CAP-RC`: - - - ``CEC_CAP_RC`` - - - 0x00000010 - - - This adapter supports the remote control protocol. - - - .. _`CEC-CAP-MONITOR-ALL`: - - - ``CEC_CAP_MONITOR_ALL`` - - - 0x00000020 - - - The CEC hardware can monitor all messages, not just directed and - broadcast messages. + - ``CEC_CAP_MONITOR_ALL`` + - 0x00000020 + - The CEC hardware can monitor all messages, not just directed and + broadcast messages. diff --git a/Documentation/media/uapi/cec/cec-ioc-adap-g-log-addrs.rst b/Documentation/media/uapi/cec/cec-ioc-adap-g-log-addrs.rst index 940a16d8d55e..b878637e91b3 100644 --- a/Documentation/media/uapi/cec/cec-ioc-adap-g-log-addrs.rst +++ b/Documentation/media/uapi/cec/cec-ioc-adap-g-log-addrs.rst @@ -77,134 +77,79 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 1 1 16 - - - .. row 1 - - - __u8 - - - ``log_addr[CEC_MAX_LOG_ADDRS]`` - - - The actual logical addresses that were claimed. This is set by the - driver. If no logical address could be claimed, then it is set to - ``CEC_LOG_ADDR_INVALID``. If this adapter is Unregistered, then - ``log_addr[0]`` is set to 0xf and all others to - ``CEC_LOG_ADDR_INVALID``. - - - .. row 2 - - - __u16 - - - ``log_addr_mask`` - - - The bitmask of all logical addresses this adapter has claimed. If - this adapter is Unregistered then ``log_addr_mask`` sets bit 15 - and clears all other bits. If this adapter is not configured at - all, then ``log_addr_mask`` is set to 0. Set by the driver. - - - .. row 3 - - - __u8 - - - ``cec_version`` - - - The CEC version that this adapter shall use. See - :ref:`cec-versions`. Used to implement the - ``CEC_MSG_CEC_VERSION`` and ``CEC_MSG_REPORT_FEATURES`` messages. - Note that :ref:`CEC_OP_CEC_VERSION_1_3A ` is not allowed by the CEC - framework. - - - .. row 4 - - - __u8 - - - ``num_log_addrs`` - - - Number of logical addresses to set up. Must be ≤ - ``available_log_addrs`` as returned by - :ref:`CEC_ADAP_G_CAPS`. All arrays in - this structure are only filled up to index - ``available_log_addrs``-1. The remaining array elements will be - ignored. Note that the CEC 2.0 standard allows for a maximum of 2 - logical addresses, although some hardware has support for more. - ``CEC_MAX_LOG_ADDRS`` is 4. The driver will return the actual - number of logical addresses it could claim, which may be less than - what was requested. If this field is set to 0, then the CEC - adapter shall clear all claimed logical addresses and all other - fields will be ignored. - - - .. row 5 - - - __u32 - - - ``vendor_id`` - - - The vendor ID is a 24-bit number that identifies the specific - vendor or entity. Based on this ID vendor specific commands may be - defined. If you do not want a vendor ID then set it to - ``CEC_VENDOR_ID_NONE``. - - - .. row 6 - - - __u32 - - - ``flags`` - - - Flags. See :ref:`cec-log-addrs-flags` for a list of available flags. - - - .. row 7 - - - char - - - ``osd_name[15]`` - - - The On-Screen Display name as is returned by the - ``CEC_MSG_SET_OSD_NAME`` message. - - - .. row 8 - - - __u8 - - - ``primary_device_type[CEC_MAX_LOG_ADDRS]`` - - - Primary device type for each logical address. See - :ref:`cec-prim-dev-types` for possible types. - - - .. row 9 - - - __u8 - - - ``log_addr_type[CEC_MAX_LOG_ADDRS]`` - - - Logical address types. See :ref:`cec-log-addr-types` for - possible types. The driver will update this with the actual - logical address type that it claimed (e.g. it may have to fallback - to :ref:`CEC_LOG_ADDR_TYPE_UNREGISTERED `). - - - .. row 10 - - - __u8 - - - ``all_device_types[CEC_MAX_LOG_ADDRS]`` - - - CEC 2.0 specific: the bit mask of all device types. See - :ref:`cec-all-dev-types-flags`. It is used in the CEC 2.0 - ``CEC_MSG_REPORT_FEATURES`` message. For CEC 1.4 you can either leave - this field to 0, or fill it in according to the CEC 2.0 guidelines to - give the CEC framework more information about the device type, even - though the framework won't use it directly in the CEC message. - - - .. row 11 - - - __u8 - - - ``features[CEC_MAX_LOG_ADDRS][12]`` - - - Features for each logical address. It is used in the CEC 2.0 - ``CEC_MSG_REPORT_FEATURES`` message. The 12 bytes include both the - RC Profile and the Device Features. For CEC 1.4 you can either leave - this field to all 0, or fill it in according to the CEC 2.0 guidelines to - give the CEC framework more information about the device type, even - though the framework won't use it directly in the CEC message. + * - __u8 + - ``log_addr[CEC_MAX_LOG_ADDRS]`` + - The actual logical addresses that were claimed. This is set by the + driver. If no logical address could be claimed, then it is set to + ``CEC_LOG_ADDR_INVALID``. If this adapter is Unregistered, then + ``log_addr[0]`` is set to 0xf and all others to + ``CEC_LOG_ADDR_INVALID``. + * - __u16 + - ``log_addr_mask`` + - The bitmask of all logical addresses this adapter has claimed. If + this adapter is Unregistered then ``log_addr_mask`` sets bit 15 + and clears all other bits. If this adapter is not configured at + all, then ``log_addr_mask`` is set to 0. Set by the driver. + * - __u8 + - ``cec_version`` + - The CEC version that this adapter shall use. See + :ref:`cec-versions`. Used to implement the + ``CEC_MSG_CEC_VERSION`` and ``CEC_MSG_REPORT_FEATURES`` messages. + Note that :ref:`CEC_OP_CEC_VERSION_1_3A ` is not allowed by the CEC + framework. + * - __u8 + - ``num_log_addrs`` + - Number of logical addresses to set up. Must be ≤ + ``available_log_addrs`` as returned by + :ref:`CEC_ADAP_G_CAPS`. All arrays in + this structure are only filled up to index + ``available_log_addrs``-1. The remaining array elements will be + ignored. Note that the CEC 2.0 standard allows for a maximum of 2 + logical addresses, although some hardware has support for more. + ``CEC_MAX_LOG_ADDRS`` is 4. The driver will return the actual + number of logical addresses it could claim, which may be less than + what was requested. If this field is set to 0, then the CEC + adapter shall clear all claimed logical addresses and all other + fields will be ignored. + * - __u32 + - ``vendor_id`` + - The vendor ID is a 24-bit number that identifies the specific + vendor or entity. Based on this ID vendor specific commands may be + defined. If you do not want a vendor ID then set it to + ``CEC_VENDOR_ID_NONE``. + * - __u32 + - ``flags`` + - Flags. See :ref:`cec-log-addrs-flags` for a list of available flags. + * - char + - ``osd_name[15]`` + - The On-Screen Display name as is returned by the + ``CEC_MSG_SET_OSD_NAME`` message. + * - __u8 + - ``primary_device_type[CEC_MAX_LOG_ADDRS]`` + - Primary device type for each logical address. See + :ref:`cec-prim-dev-types` for possible types. + * - __u8 + - ``log_addr_type[CEC_MAX_LOG_ADDRS]`` + - Logical address types. See :ref:`cec-log-addr-types` for + possible types. The driver will update this with the actual + logical address type that it claimed (e.g. it may have to fallback + to :ref:`CEC_LOG_ADDR_TYPE_UNREGISTERED `). + * - __u8 + - ``all_device_types[CEC_MAX_LOG_ADDRS]`` + - CEC 2.0 specific: the bit mask of all device types. See + :ref:`cec-all-dev-types-flags`. It is used in the CEC 2.0 + ``CEC_MSG_REPORT_FEATURES`` message. For CEC 1.4 you can either leave + this field to 0, or fill it in according to the CEC 2.0 guidelines to + give the CEC framework more information about the device type, even + though the framework won't use it directly in the CEC message. + * - __u8 + - ``features[CEC_MAX_LOG_ADDRS][12]`` + - Features for each logical address. It is used in the CEC 2.0 + ``CEC_MSG_REPORT_FEATURES`` message. The 12 bytes include both the + RC Profile and the Device Features. For CEC 1.4 you can either leave + this field to all 0, or fill it in according to the CEC 2.0 guidelines to + give the CEC framework more information about the device type, even + though the framework won't use it directly in the CEC message. .. _cec-log-addrs-flags: @@ -213,17 +158,33 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 3 1 4 + * .. _`CEC-LOG-ADDRS-FL-ALLOW-UNREG-FALLBACK`: - - .. _`CEC-LOG-ADDRS-FL-ALLOW-UNREG-FALLBACK`: + - ``CEC_LOG_ADDRS_FL_ALLOW_UNREG_FALLBACK`` + - 1 + - By default if no logical address of the requested type can be claimed, then + it will go back to the unconfigured state. If this flag is set, then it will + fallback to the Unregistered logical address. Note that if the Unregistered + logical address was explicitly requested, then this flag has no effect. + * .. _`CEC-LOG-ADDRS-FL-ALLOW-RC-PASSTHRU`: - - ``CEC_LOG_ADDRS_FL_ALLOW_UNREG_FALLBACK`` + - ``CEC_LOG_ADDRS_FL_ALLOW_RC_PASSTHRU`` + - 2 + - By default the ``CEC_MSG_USER_CONTROL_PRESSED`` and ``CEC_MSG_USER_CONTROL_RELEASED`` + messages are only passed on to the follower(s), if any. If this flag is set, + then these messages are also passed on to the remote control input subsystem + and will appear as keystrokes. This features needs to be enabled explicitly. + If CEC is used to enter e.g. passwords, then you may not want to enable this + to avoid trivial snooping of the keystrokes. + * .. _`CEC-LOG-ADDRS-FL-CDC-ONLY`: - - 1 + - `CEC_LOG_ADDRS_FL_CDC_ONLY` + - 4 + - If this flag is set, then the device is CDC-Only. CDC-Only CEC devices + are CEC devices that can only handle CDC messages. + + All other messages are ignored. - - By default if no logical address of the requested type can be claimed, then - it will go back to the unconfigured state. If this flag is set, then it will - fallback to the Unregistered logical address. Note that if the Unregistered - logical address was explicitly requested, then this flag has no effect. .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| @@ -234,30 +195,21 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 3 1 4 + * .. _`CEC-OP-CEC-VERSION-1-3A`: - - .. _`CEC-OP-CEC-VERSION-1-3A`: + - ``CEC_OP_CEC_VERSION_1_3A`` + - 4 + - CEC version according to the HDMI 1.3a standard. + * .. _`CEC-OP-CEC-VERSION-1-4B`: - - ``CEC_OP_CEC_VERSION_1_3A`` + - ``CEC_OP_CEC_VERSION_1_4B`` + - 5 + - CEC version according to the HDMI 1.4b standard. + * .. _`CEC-OP-CEC-VERSION-2-0`: - - 4 - - - CEC version according to the HDMI 1.3a standard. - - - .. _`CEC-OP-CEC-VERSION-1-4B`: - - - ``CEC_OP_CEC_VERSION_1_4B`` - - - 5 - - - CEC version according to the HDMI 1.4b standard. - - - .. _`CEC-OP-CEC-VERSION-2-0`: - - - ``CEC_OP_CEC_VERSION_2_0`` - - - 6 - - - CEC version according to the HDMI 2.0 standard. + - ``CEC_OP_CEC_VERSION_2_0`` + - 6 + - CEC version according to the HDMI 2.0 standard. .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| @@ -269,62 +221,41 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 3 1 4 + * .. _`CEC-OP-PRIM-DEVTYPE-TV`: - - .. _`CEC-OP-PRIM-DEVTYPE-TV`: + - ``CEC_OP_PRIM_DEVTYPE_TV`` + - 0 + - Use for a TV. + * .. _`CEC-OP-PRIM-DEVTYPE-RECORD`: - - ``CEC_OP_PRIM_DEVTYPE_TV`` + - ``CEC_OP_PRIM_DEVTYPE_RECORD`` + - 1 + - Use for a recording device. + * .. _`CEC-OP-PRIM-DEVTYPE-TUNER`: - - 0 + - ``CEC_OP_PRIM_DEVTYPE_TUNER`` + - 3 + - Use for a device with a tuner. + * .. _`CEC-OP-PRIM-DEVTYPE-PLAYBACK`: - - Use for a TV. + - ``CEC_OP_PRIM_DEVTYPE_PLAYBACK`` + - 4 + - Use for a playback device. + * .. _`CEC-OP-PRIM-DEVTYPE-AUDIOSYSTEM`: - - .. _`CEC-OP-PRIM-DEVTYPE-RECORD`: + - ``CEC_OP_PRIM_DEVTYPE_AUDIOSYSTEM`` + - 5 + - Use for an audio system (e.g. an audio/video receiver). + * .. _`CEC-OP-PRIM-DEVTYPE-SWITCH`: - - ``CEC_OP_PRIM_DEVTYPE_RECORD`` + - ``CEC_OP_PRIM_DEVTYPE_SWITCH`` + - 6 + - Use for a CEC switch. + * .. _`CEC-OP-PRIM-DEVTYPE-VIDEOPROC`: - - 1 - - - Use for a recording device. - - - .. _`CEC-OP-PRIM-DEVTYPE-TUNER`: - - - ``CEC_OP_PRIM_DEVTYPE_TUNER`` - - - 3 - - - Use for a device with a tuner. - - - .. _`CEC-OP-PRIM-DEVTYPE-PLAYBACK`: - - - ``CEC_OP_PRIM_DEVTYPE_PLAYBACK`` - - - 4 - - - Use for a playback device. - - - .. _`CEC-OP-PRIM-DEVTYPE-AUDIOSYSTEM`: - - - ``CEC_OP_PRIM_DEVTYPE_AUDIOSYSTEM`` - - - 5 - - - Use for an audio system (e.g. an audio/video receiver). - - - .. _`CEC-OP-PRIM-DEVTYPE-SWITCH`: - - - ``CEC_OP_PRIM_DEVTYPE_SWITCH`` - - - 6 - - - Use for a CEC switch. - - - .. _`CEC-OP-PRIM-DEVTYPE-VIDEOPROC`: - - - ``CEC_OP_PRIM_DEVTYPE_VIDEOPROC`` - - - 7 - - - Use for a video processor device. + - ``CEC_OP_PRIM_DEVTYPE_VIDEOPROC`` + - 7 + - Use for a video processor device. .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| @@ -336,64 +267,43 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-LOG-ADDR-TYPE-TV`: - - .. _`CEC-LOG-ADDR-TYPE-TV`: + - ``CEC_LOG_ADDR_TYPE_TV`` + - 0 + - Use for a TV. + * .. _`CEC-LOG-ADDR-TYPE-RECORD`: - - ``CEC_LOG_ADDR_TYPE_TV`` + - ``CEC_LOG_ADDR_TYPE_RECORD`` + - 1 + - Use for a recording device. + * .. _`CEC-LOG-ADDR-TYPE-TUNER`: - - 0 + - ``CEC_LOG_ADDR_TYPE_TUNER`` + - 2 + - Use for a tuner device. + * .. _`CEC-LOG-ADDR-TYPE-PLAYBACK`: - - Use for a TV. + - ``CEC_LOG_ADDR_TYPE_PLAYBACK`` + - 3 + - Use for a playback device. + * .. _`CEC-LOG-ADDR-TYPE-AUDIOSYSTEM`: - - .. _`CEC-LOG-ADDR-TYPE-RECORD`: + - ``CEC_LOG_ADDR_TYPE_AUDIOSYSTEM`` + - 4 + - Use for an audio system device. + * .. _`CEC-LOG-ADDR-TYPE-SPECIFIC`: - - ``CEC_LOG_ADDR_TYPE_RECORD`` + - ``CEC_LOG_ADDR_TYPE_SPECIFIC`` + - 5 + - Use for a second TV or for a video processor device. + * .. _`CEC-LOG-ADDR-TYPE-UNREGISTERED`: - - 1 - - - Use for a recording device. - - - .. _`CEC-LOG-ADDR-TYPE-TUNER`: - - - ``CEC_LOG_ADDR_TYPE_TUNER`` - - - 2 - - - Use for a tuner device. - - - .. _`CEC-LOG-ADDR-TYPE-PLAYBACK`: - - - ``CEC_LOG_ADDR_TYPE_PLAYBACK`` - - - 3 - - - Use for a playback device. - - - .. _`CEC-LOG-ADDR-TYPE-AUDIOSYSTEM`: - - - ``CEC_LOG_ADDR_TYPE_AUDIOSYSTEM`` - - - 4 - - - Use for an audio system device. - - - .. _`CEC-LOG-ADDR-TYPE-SPECIFIC`: - - - ``CEC_LOG_ADDR_TYPE_SPECIFIC`` - - - 5 - - - Use for a second TV or for a video processor device. - - - .. _`CEC-LOG-ADDR-TYPE-UNREGISTERED`: - - - ``CEC_LOG_ADDR_TYPE_UNREGISTERED`` - - - 6 - - - Use this if you just want to remain unregistered. Used for pure - CEC switches or CDC-only devices (CDC: Capability Discovery and - Control). + - ``CEC_LOG_ADDR_TYPE_UNREGISTERED`` + - 6 + - Use this if you just want to remain unregistered. Used for pure + CEC switches or CDC-only devices (CDC: Capability Discovery and + Control). @@ -406,54 +316,36 @@ logical address types are already defined will return with error ``EBUSY``. :stub-columns: 0 :widths: 3 1 4 + * .. _`CEC-OP-ALL-DEVTYPE-TV`: - - .. _`CEC-OP-ALL-DEVTYPE-TV`: + - ``CEC_OP_ALL_DEVTYPE_TV`` + - 0x80 + - This supports the TV type. + * .. _`CEC-OP-ALL-DEVTYPE-RECORD`: - - ``CEC_OP_ALL_DEVTYPE_TV`` + - ``CEC_OP_ALL_DEVTYPE_RECORD`` + - 0x40 + - This supports the Recording type. + * .. _`CEC-OP-ALL-DEVTYPE-TUNER`: - - 0x80 + - ``CEC_OP_ALL_DEVTYPE_TUNER`` + - 0x20 + - This supports the Tuner type. + * .. _`CEC-OP-ALL-DEVTYPE-PLAYBACK`: - - This supports the TV type. + - ``CEC_OP_ALL_DEVTYPE_PLAYBACK`` + - 0x10 + - This supports the Playback type. + * .. _`CEC-OP-ALL-DEVTYPE-AUDIOSYSTEM`: - - .. _`CEC-OP-ALL-DEVTYPE-RECORD`: + - ``CEC_OP_ALL_DEVTYPE_AUDIOSYSTEM`` + - 0x08 + - This supports the Audio System type. + * .. _`CEC-OP-ALL-DEVTYPE-SWITCH`: - - ``CEC_OP_ALL_DEVTYPE_RECORD`` - - - 0x40 - - - This supports the Recording type. - - - .. _`CEC-OP-ALL-DEVTYPE-TUNER`: - - - ``CEC_OP_ALL_DEVTYPE_TUNER`` - - - 0x20 - - - This supports the Tuner type. - - - .. _`CEC-OP-ALL-DEVTYPE-PLAYBACK`: - - - ``CEC_OP_ALL_DEVTYPE_PLAYBACK`` - - - 0x10 - - - This supports the Playback type. - - - .. _`CEC-OP-ALL-DEVTYPE-AUDIOSYSTEM`: - - - ``CEC_OP_ALL_DEVTYPE_AUDIOSYSTEM`` - - - 0x08 - - - This supports the Audio System type. - - - .. _`CEC-OP-ALL-DEVTYPE-SWITCH`: - - - ``CEC_OP_ALL_DEVTYPE_SWITCH`` - - - 0x04 - - - This supports the CEC Switch or Video Processing type. + - ``CEC_OP_ALL_DEVTYPE_SWITCH`` + - 0x04 + - This supports the CEC Switch or Video Processing type. diff --git a/Documentation/media/uapi/cec/cec-ioc-dqevent.rst b/Documentation/media/uapi/cec/cec-ioc-dqevent.rst index e283588a830b..e256c6605de7 100644 --- a/Documentation/media/uapi/cec/cec-ioc-dqevent.rst +++ b/Documentation/media/uapi/cec/cec-ioc-dqevent.rst @@ -58,26 +58,16 @@ it is guaranteed that the state did change in between the two events. :stub-columns: 0 :widths: 1 1 8 - - - .. row 1 - - - __u16 - - - ``phys_addr`` - - - The current physical address. This is ``CEC_PHYS_ADDR_INVALID`` if no + * - __u16 + - ``phys_addr`` + - The current physical address. This is ``CEC_PHYS_ADDR_INVALID`` if no valid physical address is set. - - - .. row 2 - - - __u16 - - - ``log_addr_mask`` - - - The current set of claimed logical addresses. This is 0 if no logical - addresses are claimed or if ``phys_addr`` is ``CEC_PHYS_ADDR_INVALID``. - If bit 15 is set (``1 << CEC_LOG_ADDR_UNREGISTERED``) then this device - has the unregistered logical address. In that case all other bits are 0. + * - __u16 + - ``log_addr_mask`` + - The current set of claimed logical addresses. This is 0 if no logical + addresses are claimed or if ``phys_addr`` is ``CEC_PHYS_ADDR_INVALID``. + If bit 15 is set (``1 << CEC_LOG_ADDR_UNREGISTERED``) then this device + has the unregistered logical address. In that case all other bits are 0. .. c:type:: cec_event_lost_msgs @@ -89,22 +79,17 @@ it is guaranteed that the state did change in between the two events. :stub-columns: 0 :widths: 1 1 16 - - - .. row 1 - - - __u32 - - - ``lost_msgs`` - - - Set to the number of lost messages since the filehandle was opened - or since the last time this event was dequeued for this - filehandle. The messages lost are the oldest messages. So when a - new message arrives and there is no more room, then the oldest - message is discarded to make room for the new one. The internal - size of the message queue guarantees that all messages received in - the last two seconds will be stored. Since messages should be - replied to within a second according to the CEC specification, - this is more than enough. + * - __u32 + - ``lost_msgs`` + - Set to the number of lost messages since the filehandle was opened + or since the last time this event was dequeued for this + filehandle. The messages lost are the oldest messages. So when a + new message arrives and there is no more room, then the oldest + message is discarded to make room for the new one. The internal + size of the message queue guarantees that all messages received in + the last two seconds will be stored. Since messages should be + replied to within a second according to the CEC specification, + this is more than enough. .. tabularcolumns:: |p{1.0cm}|p{4.2cm}|p{2.5cm}|p{8.8cm}| @@ -116,62 +101,32 @@ it is guaranteed that the state did change in between the two events. :stub-columns: 0 :widths: 1 1 1 8 + * - __u64 + - ``ts`` + - :cspan:`1` Timestamp of the event in ns. - - .. row 1 - - - __u64 - - - ``ts`` - - - :cspan:`1` Timestamp of the event in ns. - - The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access - the same clock from userspace use :c:func:`clock_gettime`. - - - .. row 2 - - - __u32 - - - ``event`` - - - :cspan:`1` The CEC event type, see :ref:`cec-events`. - - - .. row 3 - - - __u32 - - - ``flags`` - - - :cspan:`1` Event flags, see :ref:`cec-event-flags`. - - - .. row 4 - - - union - - - (anonymous) - - - - - - - - .. row 5 - - - - - struct cec_event_state_change - - - ``state_change`` - - - The new adapter state as sent by the :ref:`CEC_EVENT_STATE_CHANGE ` - event. - - - .. row 6 - - - - - struct cec_event_lost_msgs - - - ``lost_msgs`` - - - The number of lost messages as sent by the :ref:`CEC_EVENT_LOST_MSGS ` - event. + The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access + the same clock from userspace use :c:func:`clock_gettime`. + * - __u32 + - ``event`` + - :cspan:`1` The CEC event type, see :ref:`cec-events`. + * - __u32 + - ``flags`` + - :cspan:`1` Event flags, see :ref:`cec-event-flags`. + * - union + - (anonymous) + - + - + * - + - struct cec_event_state_change + - ``state_change`` + - The new adapter state as sent by the :ref:`CEC_EVENT_STATE_CHANGE ` + event. + * - + - struct cec_event_lost_msgs + - ``lost_msgs`` + - The number of lost messages as sent by the :ref:`CEC_EVENT_LOST_MSGS ` + event. .. tabularcolumns:: |p{5.6cm}|p{0.9cm}|p{11.0cm}| @@ -183,25 +138,19 @@ it is guaranteed that the state did change in between the two events. :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-EVENT-STATE-CHANGE`: - - .. _`CEC-EVENT-STATE-CHANGE`: + - ``CEC_EVENT_STATE_CHANGE`` + - 1 + - Generated when the CEC Adapter's state changes. When open() is + called an initial event will be generated for that filehandle with + the CEC Adapter's state at that time. + * .. _`CEC-EVENT-LOST-MSGS`: - - ``CEC_EVENT_STATE_CHANGE`` - - - 1 - - - Generated when the CEC Adapter's state changes. When open() is - called an initial event will be generated for that filehandle with - the CEC Adapter's state at that time. - - - .. _`CEC-EVENT-LOST-MSGS`: - - - ``CEC_EVENT_LOST_MSGS`` - - - 2 - - - Generated if one or more CEC messages were lost because the - application didn't dequeue CEC messages fast enough. + - ``CEC_EVENT_LOST_MSGS`` + - 2 + - Generated if one or more CEC messages were lost because the + application didn't dequeue CEC messages fast enough. .. tabularcolumns:: |p{6.0cm}|p{0.6cm}|p{10.9cm}| @@ -213,17 +162,14 @@ it is guaranteed that the state did change in between the two events. :stub-columns: 0 :widths: 3 1 8 + * .. _`CEC-EVENT-FL-INITIAL-VALUE`: - - .. _`CEC-EVENT-FL-INITIAL-VALUE`: - - - ``CEC_EVENT_FL_INITIAL_VALUE`` - - - 1 - - - Set for the initial events that are generated when the device is - opened. See the table above for which events do this. This allows - applications to learn the initial state of the CEC adapter at - open() time. + - ``CEC_EVENT_FL_INITIAL_VALUE`` + - 1 + - Set for the initial events that are generated when the device is + opened. See the table above for which events do this. This allows + applications to learn the initial state of the CEC adapter at + open() time. diff --git a/Documentation/media/uapi/cec/cec-ioc-g-mode.rst b/Documentation/media/uapi/cec/cec-ioc-g-mode.rst index 70a41902ab58..4f5818b9d277 100644 --- a/Documentation/media/uapi/cec/cec-ioc-g-mode.rst +++ b/Documentation/media/uapi/cec/cec-ioc-g-mode.rst @@ -83,37 +83,28 @@ Available initiator modes are: :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-MODE-NO-INITIATOR`: - - .. _`CEC-MODE-NO-INITIATOR`: + - ``CEC_MODE_NO_INITIATOR`` + - 0x0 + - This is not an initiator, i.e. it cannot transmit CEC messages or + make any other changes to the CEC adapter. + * .. _`CEC-MODE-INITIATOR`: - - ``CEC_MODE_NO_INITIATOR`` + - ``CEC_MODE_INITIATOR`` + - 0x1 + - This is an initiator (the default when the device is opened) and + it can transmit CEC messages and make changes to the CEC adapter, + unless there is an exclusive initiator. + * .. _`CEC-MODE-EXCL-INITIATOR`: - - 0x0 - - - This is not an initiator, i.e. it cannot transmit CEC messages or - make any other changes to the CEC adapter. - - - .. _`CEC-MODE-INITIATOR`: - - - ``CEC_MODE_INITIATOR`` - - - 0x1 - - - This is an initiator (the default when the device is opened) and - it can transmit CEC messages and make changes to the CEC adapter, - unless there is an exclusive initiator. - - - .. _`CEC-MODE-EXCL-INITIATOR`: - - - ``CEC_MODE_EXCL_INITIATOR`` - - - 0x2 - - - This is an exclusive initiator and this file descriptor is the - only one that can transmit CEC messages and make changes to the - CEC adapter. If someone else is already the exclusive initiator - then an attempt to become one will return the ``EBUSY`` error code - error. + - ``CEC_MODE_EXCL_INITIATOR`` + - 0x2 + - This is an exclusive initiator and this file descriptor is the + only one that can transmit CEC messages and make changes to the + CEC adapter. If someone else is already the exclusive initiator + then an attempt to become one will return the ``EBUSY`` error code + error. Available follower modes are: @@ -127,86 +118,68 @@ Available follower modes are: :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-MODE-NO-FOLLOWER`: - - .. _`CEC-MODE-NO-FOLLOWER`: + - ``CEC_MODE_NO_FOLLOWER`` + - 0x00 + - This is not a follower (the default when the device is opened). + * .. _`CEC-MODE-FOLLOWER`: - - ``CEC_MODE_NO_FOLLOWER`` + - ``CEC_MODE_FOLLOWER`` + - 0x10 + - This is a follower and it will receive CEC messages unless there + is an exclusive follower. You cannot become a follower if + :ref:`CEC_CAP_TRANSMIT ` is not set or if :ref:`CEC_MODE_NO_INITIATOR ` + was specified, the ``EINVAL`` error code is returned in that case. + * .. _`CEC-MODE-EXCL-FOLLOWER`: - - 0x00 + - ``CEC_MODE_EXCL_FOLLOWER`` + - 0x20 + - This is an exclusive follower and only this file descriptor will + receive CEC messages for processing. If someone else is already + the exclusive follower then an attempt to become one will return + the ``EBUSY`` error code. You cannot become a follower if + :ref:`CEC_CAP_TRANSMIT ` is not set or if :ref:`CEC_MODE_NO_INITIATOR ` + was specified, the ``EINVAL`` error code is returned in that case. + * .. _`CEC-MODE-EXCL-FOLLOWER-PASSTHRU`: - - This is not a follower (the default when the device is opened). + - ``CEC_MODE_EXCL_FOLLOWER_PASSTHRU`` + - 0x30 + - This is an exclusive follower and only this file descriptor will + receive CEC messages for processing. In addition it will put the + CEC device into passthrough mode, allowing the exclusive follower + to handle most core messages instead of relying on the CEC + framework for that. If someone else is already the exclusive + follower then an attempt to become one will return the ``EBUSY`` error + code. You cannot become a follower if :ref:`CEC_CAP_TRANSMIT ` + is not set or if :ref:`CEC_MODE_NO_INITIATOR ` was specified, + the ``EINVAL`` error code is returned in that case. + * .. _`CEC-MODE-MONITOR`: - - .. _`CEC-MODE-FOLLOWER`: + - ``CEC_MODE_MONITOR`` + - 0xe0 + - Put the file descriptor into monitor mode. Can only be used in + combination with :ref:`CEC_MODE_NO_INITIATOR `, otherwise EINVAL error + code will be returned. In monitor mode all messages this CEC + device transmits and all messages it receives (both broadcast + messages and directed messages for one its logical addresses) will + be reported. This is very useful for debugging. This is only + allowed if the process has the ``CAP_NET_ADMIN`` capability. If + that is not set, then the ``EPERM`` error code is returned. + * .. _`CEC-MODE-MONITOR-ALL`: - - ``CEC_MODE_FOLLOWER`` - - - 0x10 - - - This is a follower and it will receive CEC messages unless there - is an exclusive follower. You cannot become a follower if - :ref:`CEC_CAP_TRANSMIT ` is not set or if :ref:`CEC_MODE_NO_INITIATOR ` - was specified, the ``EINVAL`` error code is returned in that case. - - - .. _`CEC-MODE-EXCL-FOLLOWER`: - - - ``CEC_MODE_EXCL_FOLLOWER`` - - - 0x20 - - - This is an exclusive follower and only this file descriptor will - receive CEC messages for processing. If someone else is already - the exclusive follower then an attempt to become one will return - the ``EBUSY`` error code. You cannot become a follower if - :ref:`CEC_CAP_TRANSMIT ` is not set or if :ref:`CEC_MODE_NO_INITIATOR ` - was specified, the ``EINVAL`` error code is returned in that case. - - - .. _`CEC-MODE-EXCL-FOLLOWER-PASSTHRU`: - - - ``CEC_MODE_EXCL_FOLLOWER_PASSTHRU`` - - - 0x30 - - - This is an exclusive follower and only this file descriptor will - receive CEC messages for processing. In addition it will put the - CEC device into passthrough mode, allowing the exclusive follower - to handle most core messages instead of relying on the CEC - framework for that. If someone else is already the exclusive - follower then an attempt to become one will return the ``EBUSY`` error - code. You cannot become a follower if :ref:`CEC_CAP_TRANSMIT ` - is not set or if :ref:`CEC_MODE_NO_INITIATOR ` was specified, - the ``EINVAL`` error code is returned in that case. - - - .. _`CEC-MODE-MONITOR`: - - - ``CEC_MODE_MONITOR`` - - - 0xe0 - - - Put the file descriptor into monitor mode. Can only be used in - combination with :ref:`CEC_MODE_NO_INITIATOR `, otherwise EINVAL error - code will be returned. In monitor mode all messages this CEC - device transmits and all messages it receives (both broadcast - messages and directed messages for one its logical addresses) will - be reported. This is very useful for debugging. This is only - allowed if the process has the ``CAP_NET_ADMIN`` capability. If - that is not set, then the ``EPERM`` error code is returned. - - - .. _`CEC-MODE-MONITOR-ALL`: - - - ``CEC_MODE_MONITOR_ALL`` - - - 0xf0 - - - Put the file descriptor into 'monitor all' mode. Can only be used - in combination with :ref:`CEC_MODE_NO_INITIATOR `, otherwise - the ``EINVAL`` error code will be returned. In 'monitor all' mode all messages - this CEC device transmits and all messages it receives, including - directed messages for other CEC devices will be reported. This is - very useful for debugging, but not all devices support this. This - mode requires that the :ref:`CEC_CAP_MONITOR_ALL ` capability is set, - otherwise the ``EINVAL`` error code is returned. This is only allowed if - the process has the ``CAP_NET_ADMIN`` capability. If that is not - set, then the ``EPERM`` error code is returned. + - ``CEC_MODE_MONITOR_ALL`` + - 0xf0 + - Put the file descriptor into 'monitor all' mode. Can only be used + in combination with :ref:`CEC_MODE_NO_INITIATOR `, otherwise + the ``EINVAL`` error code will be returned. In 'monitor all' mode all messages + this CEC device transmits and all messages it receives, including + directed messages for other CEC devices will be reported. This is + very useful for debugging, but not all devices support this. This + mode requires that the :ref:`CEC_CAP_MONITOR_ALL ` capability is set, + otherwise the ``EINVAL`` error code is returned. This is only allowed if + the process has the ``CAP_NET_ADMIN`` capability. If that is not + set, then the ``EPERM`` error code is returned. Core message processing details: @@ -220,76 +193,58 @@ Core message processing details: :stub-columns: 0 :widths: 1 8 + * .. _`CEC-MSG-GET-CEC-VERSION`: - - .. _`CEC-MSG-GET-CEC-VERSION`: + - ``CEC_MSG_GET_CEC_VERSION`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will return the CEC version that was + set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. + * .. _`CEC-MSG-GIVE-DEVICE-VENDOR-ID`: - - ``CEC_MSG_GET_CEC_VERSION`` + - ``CEC_MSG_GIVE_DEVICE_VENDOR_ID`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will return the vendor ID that was + set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. + * .. _`CEC-MSG-ABORT`: - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will return the CEC version that was - set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. + - ``CEC_MSG_ABORT`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will return a feature refused + message as per the specification. + * .. _`CEC-MSG-GIVE-PHYSICAL-ADDR`: - - .. _`CEC-MSG-GIVE-DEVICE-VENDOR-ID`: + - ``CEC_MSG_GIVE_PHYSICAL_ADDR`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will report the current physical + address. + * .. _`CEC-MSG-GIVE-OSD-NAME`: - - ``CEC_MSG_GIVE_DEVICE_VENDOR_ID`` + - ``CEC_MSG_GIVE_OSD_NAME`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will report the current OSD name as + was set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. + * .. _`CEC-MSG-GIVE-FEATURES`: - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will return the vendor ID that was - set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. + - ``CEC_MSG_GIVE_FEATURES`` + - When in passthrough mode this message has to be handled by + userspace, otherwise the core will report the current features as + was set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS ` + or the message is ignored if the CEC version was older than 2.0. + * .. _`CEC-MSG-USER-CONTROL-PRESSED`: - - .. _`CEC-MSG-ABORT`: + - ``CEC_MSG_USER_CONTROL_PRESSED`` + - If :ref:`CEC_CAP_RC ` is set, then generate a remote control key + press. This message is always passed on to userspace. + * .. _`CEC-MSG-USER-CONTROL-RELEASED`: - - ``CEC_MSG_ABORT`` + - ``CEC_MSG_USER_CONTROL_RELEASED`` + - If :ref:`CEC_CAP_RC ` is set, then generate a remote control key + release. This message is always passed on to userspace. + * .. _`CEC-MSG-REPORT-PHYSICAL-ADDR`: - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will return a feature refused - message as per the specification. - - - .. _`CEC-MSG-GIVE-PHYSICAL-ADDR`: - - - ``CEC_MSG_GIVE_PHYSICAL_ADDR`` - - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will report the current physical - address. - - - .. _`CEC-MSG-GIVE-OSD-NAME`: - - - ``CEC_MSG_GIVE_OSD_NAME`` - - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will report the current OSD name as - was set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS `. - - - .. _`CEC-MSG-GIVE-FEATURES`: - - - ``CEC_MSG_GIVE_FEATURES`` - - - When in passthrough mode this message has to be handled by - userspace, otherwise the core will report the current features as - was set with :ref:`ioctl CEC_ADAP_S_LOG_ADDRS ` - or the message is ignored if the CEC version was older than 2.0. - - - .. _`CEC-MSG-USER-CONTROL-PRESSED`: - - - ``CEC_MSG_USER_CONTROL_PRESSED`` - - - If :ref:`CEC_CAP_RC ` is set, then generate a remote control key - press. This message is always passed on to userspace. - - - .. _`CEC-MSG-USER-CONTROL-RELEASED`: - - - ``CEC_MSG_USER_CONTROL_RELEASED`` - - - If :ref:`CEC_CAP_RC ` is set, then generate a remote control key - release. This message is always passed on to userspace. - - - .. _`CEC-MSG-REPORT-PHYSICAL-ADDR`: - - - ``CEC_MSG_REPORT_PHYSICAL_ADDR`` - - - The CEC framework will make note of the reported physical address - and then just pass the message on to userspace. + - ``CEC_MSG_REPORT_PHYSICAL_ADDR`` + - The CEC framework will make note of the reported physical address + and then just pass the message on to userspace. diff --git a/Documentation/media/uapi/cec/cec-ioc-receive.rst b/Documentation/media/uapi/cec/cec-ioc-receive.rst index d585b1bba6ac..bdf015b1d1dc 100644 --- a/Documentation/media/uapi/cec/cec-ioc-receive.rst +++ b/Documentation/media/uapi/cec/cec-ioc-receive.rst @@ -86,173 +86,126 @@ result. :stub-columns: 0 :widths: 1 1 16 + * - __u64 + - ``tx_ts`` + - Timestamp in ns of when the last byte of the message was transmitted. + The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access + the same clock from userspace use :c:func:`clock_gettime`. + * - __u64 + - ``rx_ts`` + - Timestamp in ns of when the last byte of the message was received. + The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access + the same clock from userspace use :c:func:`clock_gettime`. + * - __u32 + - ``len`` + - The length of the message. For :ref:`ioctl CEC_TRANSMIT ` this is filled in + by the application. The driver will fill this in for + :ref:`ioctl CEC_RECEIVE `. For :ref:`ioctl CEC_TRANSMIT ` it will be + filled in by the driver with the length of the reply message if ``reply`` was set. + * - __u32 + - ``timeout`` + - The timeout in milliseconds. This is the time the device will wait + for a message to be received before timing out. If it is set to 0, + then it will wait indefinitely when it is called by :ref:`ioctl CEC_RECEIVE `. + If it is 0 and it is called by :ref:`ioctl CEC_TRANSMIT `, + then it will be replaced by 1000 if the ``reply`` is non-zero or + ignored if ``reply`` is 0. + * - __u32 + - ``sequence`` + - A non-zero sequence number is automatically assigned by the CEC framework + for all transmitted messages. It is used by the CEC framework when it queues + the transmit result (when transmit was called in non-blocking mode). This + allows the application to associate the received message with the original + transmit. + * - __u32 + - ``flags`` + - Flags. See :ref:`cec-msg-flags` for a list of available flags. + * - __u8 + - ``tx_status`` + - The status bits of the transmitted message. See + :ref:`cec-tx-status` for the possible status values. It is 0 if + this messages was received, not transmitted. + * - __u8 + - ``msg[16]`` + - The message payload. For :ref:`ioctl CEC_TRANSMIT ` this is filled in by the + application. The driver will fill this in for :ref:`ioctl CEC_RECEIVE `. + For :ref:`ioctl CEC_TRANSMIT ` it will be filled in by the driver with + the payload of the reply message if ``timeout`` was set. + * - __u8 + - ``reply`` + - Wait until this message is replied. If ``reply`` is 0 and the + ``timeout`` is 0, then don't wait for a reply but return after + transmitting the message. Ignored by :ref:`ioctl CEC_RECEIVE `. + The case where ``reply`` is 0 (this is the opcode for the Feature Abort + message) and ``timeout`` is non-zero is specifically allowed to make it + possible to send a message and wait up to ``timeout`` milliseconds for a + Feature Abort reply. In this case ``rx_status`` will either be set + to :ref:`CEC_RX_STATUS_TIMEOUT ` or + :ref:`CEC_RX_STATUS_FEATURE_ABORT `. - - .. row 1 + If the transmitter message is ``CEC_MSG_INITIATE_ARC`` then the ``reply`` + values ``CEC_MSG_REPORT_ARC_INITIATED`` and ``CEC_MSG_REPORT_ARC_TERMINATED`` + are processed differently: either value will match both possible replies. + The reason is that the ``CEC_MSG_INITIATE_ARC`` message is the only CEC + message that has two possible replies other than Feature Abort. The + ``reply`` field will be updated with the actual reply so that it is + synchronized with the contents of the received message. + * - __u8 + - ``rx_status`` + - The status bits of the received message. See + :ref:`cec-rx-status` for the possible status values. It is 0 if + this message was transmitted, not received, unless this is the + reply to a transmitted message. In that case both ``rx_status`` + and ``tx_status`` are set. + * - __u8 + - ``tx_status`` + - The status bits of the transmitted message. See + :ref:`cec-tx-status` for the possible status values. It is 0 if + this messages was received, not transmitted. + * - __u8 + - ``tx_arb_lost_cnt`` + - A counter of the number of transmit attempts that resulted in the + Arbitration Lost error. This is only set if the hardware supports + this, otherwise it is always 0. This counter is only valid if the + :ref:`CEC_TX_STATUS_ARB_LOST ` status bit is set. + * - __u8 + - ``tx_nack_cnt`` + - A counter of the number of transmit attempts that resulted in the + Not Acknowledged error. This is only set if the hardware supports + this, otherwise it is always 0. This counter is only valid if the + :ref:`CEC_TX_STATUS_NACK ` status bit is set. + * - __u8 + - ``tx_low_drive_cnt`` + - A counter of the number of transmit attempts that resulted in the + Arbitration Lost error. This is only set if the hardware supports + this, otherwise it is always 0. This counter is only valid if the + :ref:`CEC_TX_STATUS_LOW_DRIVE ` status bit is set. + * - __u8 + - ``tx_error_cnt`` + - A counter of the number of transmit errors other than Arbitration + Lost or Not Acknowledged. This is only set if the hardware + supports this, otherwise it is always 0. This counter is only + valid if the :ref:`CEC_TX_STATUS_ERROR ` status bit is set. - - __u64 - - ``tx_ts`` +.. _cec-msg-flags: - - Timestamp in ns of when the last byte of the message was transmitted. - The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access - the same clock from userspace use :c:func:`clock_gettime`. +.. flat-table:: Flags for struct cec_msg + :header-rows: 0 + :stub-columns: 0 + :widths: 3 1 4 - - .. row 2 + * .. _`CEC-MSG-FL-REPLY-TO-FOLLOWERS`: - - __u64 - - - ``rx_ts`` - - - Timestamp in ns of when the last byte of the message was received. - The timestamp has been taken from the ``CLOCK_MONOTONIC`` clock. To access - the same clock from userspace use :c:func:`clock_gettime`. - - - .. row 3 - - - __u32 - - - ``len`` - - - The length of the message. For :ref:`ioctl CEC_TRANSMIT ` this is filled in - by the application. The driver will fill this in for - :ref:`ioctl CEC_RECEIVE `. For :ref:`ioctl CEC_TRANSMIT ` it will be - filled in by the driver with the length of the reply message if ``reply`` was set. - - - .. row 4 - - - __u32 - - - ``timeout`` - - - The timeout in milliseconds. This is the time the device will wait - for a message to be received before timing out. If it is set to 0, - then it will wait indefinitely when it is called by :ref:`ioctl CEC_RECEIVE `. - If it is 0 and it is called by :ref:`ioctl CEC_TRANSMIT `, - then it will be replaced by 1000 if the ``reply`` is non-zero or - ignored if ``reply`` is 0. - - - .. row 5 - - - __u32 - - - ``sequence`` - - - A non-zero sequence number is automatically assigned by the CEC framework - for all transmitted messages. It is used by the CEC framework when it queues - the transmit result (when transmit was called in non-blocking mode). This - allows the application to associate the received message with the original - transmit. - - - .. row 6 - - - __u32 - - - ``flags`` - - - Flags. No flags are defined yet, so set this to 0. - - - .. row 7 - - - __u8 - - - ``tx_status`` - - - The status bits of the transmitted message. See - :ref:`cec-tx-status` for the possible status values. It is 0 if - this messages was received, not transmitted. - - - .. row 8 - - - __u8 - - - ``msg[16]`` - - - The message payload. For :ref:`ioctl CEC_TRANSMIT ` this is filled in by the - application. The driver will fill this in for :ref:`ioctl CEC_RECEIVE `. - For :ref:`ioctl CEC_TRANSMIT ` it will be filled in by the driver with - the payload of the reply message if ``timeout`` was set. - - - .. row 8 - - - __u8 - - - ``reply`` - - - Wait until this message is replied. If ``reply`` is 0 and the - ``timeout`` is 0, then don't wait for a reply but return after - transmitting the message. Ignored by :ref:`ioctl CEC_RECEIVE `. - The case where ``reply`` is 0 (this is the opcode for the Feature Abort - message) and ``timeout`` is non-zero is specifically allowed to make it - possible to send a message and wait up to ``timeout`` milliseconds for a - Feature Abort reply. In this case ``rx_status`` will either be set - to :ref:`CEC_RX_STATUS_TIMEOUT ` or - :ref:`CEC_RX_STATUS_FEATURE_ABORT `. - - - .. row 9 - - - __u8 - - - ``rx_status`` - - - The status bits of the received message. See - :ref:`cec-rx-status` for the possible status values. It is 0 if - this message was transmitted, not received, unless this is the - reply to a transmitted message. In that case both ``rx_status`` - and ``tx_status`` are set. - - - .. row 10 - - - __u8 - - - ``tx_status`` - - - The status bits of the transmitted message. See - :ref:`cec-tx-status` for the possible status values. It is 0 if - this messages was received, not transmitted. - - - .. row 11 - - - __u8 - - - ``tx_arb_lost_cnt`` - - - A counter of the number of transmit attempts that resulted in the - Arbitration Lost error. This is only set if the hardware supports - this, otherwise it is always 0. This counter is only valid if the - :ref:`CEC_TX_STATUS_ARB_LOST ` status bit is set. - - - .. row 12 - - - __u8 - - - ``tx_nack_cnt`` - - - A counter of the number of transmit attempts that resulted in the - Not Acknowledged error. This is only set if the hardware supports - this, otherwise it is always 0. This counter is only valid if the - :ref:`CEC_TX_STATUS_NACK ` status bit is set. - - - .. row 13 - - - __u8 - - - ``tx_low_drive_cnt`` - - - A counter of the number of transmit attempts that resulted in the - Arbitration Lost error. This is only set if the hardware supports - this, otherwise it is always 0. This counter is only valid if the - :ref:`CEC_TX_STATUS_LOW_DRIVE ` status bit is set. - - - .. row 14 - - - __u8 - - - ``tx_error_cnt`` - - - A counter of the number of transmit errors other than Arbitration - Lost or Not Acknowledged. This is only set if the hardware - supports this, otherwise it is always 0. This counter is only - valid if the :ref:`CEC_TX_STATUS_ERROR ` status bit is set. + - ``CEC_MSG_FL_REPLY_TO_FOLLOWERS`` + - 1 + - If a CEC transmit expects a reply, then by default that reply is only sent to + the filehandle that called :ref:`ioctl CEC_TRANSMIT `. If this + flag is set, then the reply is also sent to all followers, if any. If the + filehandle that called :ref:`ioctl CEC_TRANSMIT ` is also a + follower, then that filehandle will receive the reply twice: once as the + result of the :ref:`ioctl CEC_TRANSMIT `, and once via + :ref:`ioctl CEC_RECEIVE `. .. tabularcolumns:: |p{5.6cm}|p{0.9cm}|p{11.0cm}| @@ -264,64 +217,46 @@ result. :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-TX-STATUS-OK`: - - .. _`CEC-TX-STATUS-OK`: + - ``CEC_TX_STATUS_OK`` + - 0x01 + - The message was transmitted successfully. This is mutually + exclusive with :ref:`CEC_TX_STATUS_MAX_RETRIES `. Other bits can still + be set if earlier attempts met with failure before the transmit + was eventually successful. + * .. _`CEC-TX-STATUS-ARB-LOST`: - - ``CEC_TX_STATUS_OK`` + - ``CEC_TX_STATUS_ARB_LOST`` + - 0x02 + - CEC line arbitration was lost. + * .. _`CEC-TX-STATUS-NACK`: - - 0x01 + - ``CEC_TX_STATUS_NACK`` + - 0x04 + - Message was not acknowledged. + * .. _`CEC-TX-STATUS-LOW-DRIVE`: - - The message was transmitted successfully. This is mutually - exclusive with :ref:`CEC_TX_STATUS_MAX_RETRIES `. Other bits can still - be set if earlier attempts met with failure before the transmit - was eventually successful. + - ``CEC_TX_STATUS_LOW_DRIVE`` + - 0x08 + - Low drive was detected on the CEC bus. This indicates that a + follower detected an error on the bus and requests a + retransmission. + * .. _`CEC-TX-STATUS-ERROR`: - - .. _`CEC-TX-STATUS-ARB-LOST`: + - ``CEC_TX_STATUS_ERROR`` + - 0x10 + - Some error occurred. This is used for any errors that do not fit + the previous two, either because the hardware could not tell which + error occurred, or because the hardware tested for other + conditions besides those two. + * .. _`CEC-TX-STATUS-MAX-RETRIES`: - - ``CEC_TX_STATUS_ARB_LOST`` - - - 0x02 - - - CEC line arbitration was lost. - - - .. _`CEC-TX-STATUS-NACK`: - - - ``CEC_TX_STATUS_NACK`` - - - 0x04 - - - Message was not acknowledged. - - - .. _`CEC-TX-STATUS-LOW-DRIVE`: - - - ``CEC_TX_STATUS_LOW_DRIVE`` - - - 0x08 - - - Low drive was detected on the CEC bus. This indicates that a - follower detected an error on the bus and requests a - retransmission. - - - .. _`CEC-TX-STATUS-ERROR`: - - - ``CEC_TX_STATUS_ERROR`` - - - 0x10 - - - Some error occurred. This is used for any errors that do not fit - the previous two, either because the hardware could not tell which - error occurred, or because the hardware tested for other - conditions besides those two. - - - .. _`CEC-TX-STATUS-MAX-RETRIES`: - - - ``CEC_TX_STATUS_MAX_RETRIES`` - - - 0x20 - - - The transmit failed after one or more retries. This status bit is - mutually exclusive with :ref:`CEC_TX_STATUS_OK `. Other bits can still - be set to explain which failures were seen. + - ``CEC_TX_STATUS_MAX_RETRIES`` + - 0x20 + - The transmit failed after one or more retries. This status bit is + mutually exclusive with :ref:`CEC_TX_STATUS_OK `. Other bits can still + be set to explain which failures were seen. .. tabularcolumns:: |p{5.6cm}|p{0.9cm}|p{11.0cm}| @@ -333,32 +268,23 @@ result. :stub-columns: 0 :widths: 3 1 16 + * .. _`CEC-RX-STATUS-OK`: - - .. _`CEC-RX-STATUS-OK`: + - ``CEC_RX_STATUS_OK`` + - 0x01 + - The message was received successfully. + * .. _`CEC-RX-STATUS-TIMEOUT`: - - ``CEC_RX_STATUS_OK`` + - ``CEC_RX_STATUS_TIMEOUT`` + - 0x02 + - The reply to an earlier transmitted message timed out. + * .. _`CEC-RX-STATUS-FEATURE-ABORT`: - - 0x01 - - - The message was received successfully. - - - .. _`CEC-RX-STATUS-TIMEOUT`: - - - ``CEC_RX_STATUS_TIMEOUT`` - - - 0x02 - - - The reply to an earlier transmitted message timed out. - - - .. _`CEC-RX-STATUS-FEATURE-ABORT`: - - - ``CEC_RX_STATUS_FEATURE_ABORT`` - - - 0x04 - - - The message was received successfully but the reply was - ``CEC_MSG_FEATURE_ABORT``. This status is only set if this message - was the reply to an earlier transmitted message. + - ``CEC_RX_STATUS_FEATURE_ABORT`` + - 0x04 + - The message was received successfully but the reply was + ``CEC_MSG_FEATURE_ABORT``. This status is only set if this message + was the reply to an earlier transmitted message. diff --git a/Documentation/media/uapi/v4l/control.rst b/Documentation/media/uapi/v4l/control.rst index d3f1450c4b08..51112badb804 100644 --- a/Documentation/media/uapi/v4l/control.rst +++ b/Documentation/media/uapi/v4l/control.rst @@ -312,21 +312,20 @@ more menu type controls. .. _enum_all_controls: -Example: Enumerating all user controls -====================================== +Example: Enumerating all controls +================================= .. code-block:: c - struct v4l2_queryctrl queryctrl; struct v4l2_querymenu querymenu; - static void enumerate_menu(void) + static void enumerate_menu(__u32 id) { printf(" Menu items:\\n"); memset(&querymenu, 0, sizeof(querymenu)); - querymenu.id = queryctrl.id; + querymenu.id = id; for (querymenu.index = queryctrl.minimum; querymenu.index <= queryctrl.maximum; @@ -337,6 +336,55 @@ Example: Enumerating all user controls } } + memset(&queryctrl, 0, sizeof(queryctrl)); + + queryctrl.id = V4L2_CTRL_FLAG_NEXT_CTRL; + while (0 == ioctl(fd, VIDIOC_QUERYCTRL, &queryctrl)) { + if (!(queryctrl.flags & V4L2_CTRL_FLAG_DISABLED)) { + printf("Control %s\\n", queryctrl.name); + + if (queryctrl.type == V4L2_CTRL_TYPE_MENU) + enumerate_menu(queryctrl.id); + } + + queryctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL; + } + if (errno != EINVAL) { + perror("VIDIOC_QUERYCTRL"); + exit(EXIT_FAILURE); + } + +Example: Enumerating all controls including compound controls +============================================================= + +.. code-block:: c + + struct v4l2_query_ext_ctrl query_ext_ctrl; + + memset(&query_ext_ctrl, 0, sizeof(query_ext_ctrl)); + + query_ext_ctrl.id = V4L2_CTRL_FLAG_NEXT_CTRL | V4L2_CTRL_FLAG_NEXT_COMPOUND; + while (0 == ioctl(fd, VIDIOC_QUERY_EXT_CTRL, &query_ext_ctrl)) { + if (!(query_ext_ctrl.flags & V4L2_CTRL_FLAG_DISABLED)) { + printf("Control %s\\n", query_ext_ctrl.name); + + if (query_ext_ctrl.type == V4L2_CTRL_TYPE_MENU) + enumerate_menu(query_ext_ctrl.id); + } + + query_ext_ctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL | V4L2_CTRL_FLAG_NEXT_COMPOUND; + } + if (errno != EINVAL) { + perror("VIDIOC_QUERY_EXT_CTRL"); + exit(EXIT_FAILURE); + } + +Example: Enumerating all user controls (old style) +================================================== + +.. code-block:: c + + memset(&queryctrl, 0, sizeof(queryctrl)); for (queryctrl.id = V4L2_CID_BASE; @@ -349,7 +397,7 @@ Example: Enumerating all user controls printf("Control %s\\n", queryctrl.name); if (queryctrl.type == V4L2_CTRL_TYPE_MENU) - enumerate_menu(); + enumerate_menu(queryctrl.id); } else { if (errno == EINVAL) continue; @@ -368,7 +416,7 @@ Example: Enumerating all user controls printf("Control %s\\n", queryctrl.name); if (queryctrl.type == V4L2_CTRL_TYPE_MENU) - enumerate_menu(); + enumerate_menu(queryctrl.id); } else { if (errno == EINVAL) break; @@ -379,32 +427,6 @@ Example: Enumerating all user controls } -Example: Enumerating all user controls (alternative) -==================================================== - -.. code-block:: c - - memset(&queryctrl, 0, sizeof(queryctrl)); - - queryctrl.id = V4L2_CTRL_CLASS_USER | V4L2_CTRL_FLAG_NEXT_CTRL; - while (0 == ioctl(fd, VIDIOC_QUERYCTRL, &queryctrl)) { - if (V4L2_CTRL_ID2CLASS(queryctrl.id) != V4L2_CTRL_CLASS_USER) - break; - if (queryctrl.flags & V4L2_CTRL_FLAG_DISABLED) - continue; - - printf("Control %s\\n", queryctrl.name); - - if (queryctrl.type == V4L2_CTRL_TYPE_MENU) - enumerate_menu(); - - queryctrl.id |= V4L2_CTRL_FLAG_NEXT_CTRL; - } - if (errno != EINVAL) { - perror("VIDIOC_QUERYCTRL"); - exit(EXIT_FAILURE); - } - Example: Changing controls ========================== diff --git a/Documentation/media/uapi/v4l/dev-codec.rst b/Documentation/media/uapi/v4l/dev-codec.rst index d9f218449ddd..c61e938bd8dc 100644 --- a/Documentation/media/uapi/v4l/dev-codec.rst +++ b/Documentation/media/uapi/v4l/dev-codec.rst @@ -26,7 +26,7 @@ parameters The MPEG controls actually support many more codecs than just MPEG. See :ref:`mpeg-controls`. -Memory-to-memory devices can often be used as a shared resource: you can +Memory-to-memory devices function as a shared resource: you can open the video node multiple times, each application setting up their own codec properties that are local to the file handle, and each can use it independently from the others. The driver will arbitrate access to diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst index 7725c33d8b69..abb105724c05 100644 --- a/Documentation/media/uapi/v4l/extended-controls.rst +++ b/Documentation/media/uapi/v4l/extended-controls.rst @@ -2846,7 +2846,7 @@ JPEG Control IDs input image is sampled, in respect to maximum sample rate in each spatial dimension. See :ref:`itu-t81`, clause A.1.1. for more details. The ``V4L2_CID_JPEG_CHROMA_SUBSAMPLING`` control determines - how Cb and Cr components are downsampled after coverting an input + how Cb and Cr components are downsampled after converting an input image from RGB to Y'CbCr color space. .. tabularcolumns:: |p{7.0cm}|p{10.5cm}| @@ -3017,6 +3017,10 @@ Image Process Control IDs test pattern images. These hardware specific test patterns can be used to test if a device is working properly. +``V4L2_CID_DEINTERLACING_MODE (menu)`` + The video deinterlacing mode (such as Bob, Weave, ...). The menu items are + driver specific and are documented in :ref:`v4l-drivers`. + .. _dv-controls: diff --git a/Documentation/media/uapi/v4l/hsv-formats.rst b/Documentation/media/uapi/v4l/hsv-formats.rst new file mode 100644 index 000000000000..f0f2615eaa95 --- /dev/null +++ b/Documentation/media/uapi/v4l/hsv-formats.rst @@ -0,0 +1,19 @@ +.. -*- coding: utf-8; mode: rst -*- + +.. _hsv-formats: + +*********** +HSV Formats +*********** + +These formats store the color information of the image +in a geometrical representation. The colors are mapped into a +cylinder, where the angle is the HUE, the height is the VALUE +and the distance to the center is the SATURATION. This is a very +useful format for image segmentation algorithms. + + +.. toctree:: + :maxdepth: 1 + + pixfmt-packed-hsv diff --git a/Documentation/media/uapi/v4l/pixfmt-002.rst b/Documentation/media/uapi/v4l/pixfmt-002.rst index 0d9e697f5d4e..2ee164c25637 100644 --- a/Documentation/media/uapi/v4l/pixfmt-002.rst +++ b/Documentation/media/uapi/v4l/pixfmt-002.rst @@ -121,6 +121,11 @@ Single-planar format structure - This information supplements the ``colorspace`` and must be set by the driver for capture streams and by the application for output streams, see :ref:`colorspaces`. + * - enum :c:type:`v4l2_hsv_encoding` + - ``hsv_enc`` + - This information supplements the ``colorspace`` and must be set by + the driver for capture streams and by the application for output + streams, see :ref:`colorspaces`. * - enum :c:type:`v4l2_quantization` - ``quantization`` - This information supplements the ``colorspace`` and must be set by diff --git a/Documentation/media/uapi/v4l/pixfmt-003.rst b/Documentation/media/uapi/v4l/pixfmt-003.rst index ae9ea7a791de..337e8188caf1 100644 --- a/Documentation/media/uapi/v4l/pixfmt-003.rst +++ b/Documentation/media/uapi/v4l/pixfmt-003.rst @@ -78,6 +78,11 @@ describing all planes of that format. - This information supplements the ``colorspace`` and must be set by the driver for capture streams and by the application for output streams, see :ref:`colorspaces`. + * - enum :c:type:`v4l2_hsv_encoding` + - ``hsv_enc`` + - This information supplements the ``colorspace`` and must be set by + the driver for capture streams and by the application for output + streams, see :ref:`colorspaces`. * - enum :c:type:`v4l2_quantization` - ``quantization`` - This information supplements the ``colorspace`` and must be set by diff --git a/Documentation/media/uapi/v4l/pixfmt-006.rst b/Documentation/media/uapi/v4l/pixfmt-006.rst index a9890ff6038b..7ae7dcf73f63 100644 --- a/Documentation/media/uapi/v4l/pixfmt-006.rst +++ b/Documentation/media/uapi/v4l/pixfmt-006.rst @@ -19,9 +19,16 @@ colorspace field of struct :c:type:`v4l2_pix_format` or struct :c:type:`v4l2_pix_format_mplane` needs to be filled in. -.. note:: +.. _hsv-colorspace: - The default R'G'B' quantization is full range for all +On :ref:`HSV formats ` the *Hue* is defined as the angle on +the cylindrical color representation. Usually this angle is measured in +degrees, i.e. 0-360. When we map this angle value into 8 bits, there are +two basic ways to do it: Divide the angular value by 2 (0-179), or use the +whole range, 0-255, dividing the angular value by 1.41. The enum +:c:type:`v4l2_hsv_encoding` specifies which encoding is used. + +.. note:: The default R'G'B' quantization is full range for all colorspaces except for BT.2020 which uses limited range R'G'B' quantization. @@ -123,6 +130,24 @@ needs to be filled in. +.. c:type:: v4l2_hsv_encoding + +.. tabularcolumns:: |p{6.5cm}|p{11.0cm}| + +.. flat-table:: V4L2 HSV Encodings + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Details + * - ``V4L2_HSV_ENC_180`` + - For the Hue, each LSB is two degrees. + * - ``V4L2_HSV_ENC_256`` + - For the Hue, the 360 degrees are mapped into 8 bits, i.e. each + LSB is roughly 1.41 degrees. + + + .. c:type:: v4l2_quantization .. tabularcolumns:: |p{6.5cm}|p{11.0cm}| @@ -136,7 +161,7 @@ needs to be filled in. * - ``V4L2_QUANTIZATION_DEFAULT`` - Use the default quantization encoding as defined by the colorspace. This is always full range for R'G'B' (except for the - BT.2020 colorspace) and usually limited range for Y'CbCr. + BT.2020 colorspace) and HSV. It is usually limited range for Y'CbCr. * - ``V4L2_QUANTIZATION_FULL_RANGE`` - Use the full range quantization encoding. I.e. the range [0…1] is mapped to [0…255] (with possible clipping to [1…254] to avoid the diff --git a/Documentation/media/uapi/v4l/pixfmt-013.rst b/Documentation/media/uapi/v4l/pixfmt-013.rst index 542c087152e3..728d7ede10fa 100644 --- a/Documentation/media/uapi/v4l/pixfmt-013.rst +++ b/Documentation/media/uapi/v4l/pixfmt-013.rst @@ -85,3 +85,8 @@ Compressed Formats - ``V4L2_PIX_FMT_VP8`` - 'VP80' - VP8 video elementary stream. + * .. _V4L2-PIX-FMT-VP9: + + - ``V4L2_PIX_FMT_VP9`` + - 'VP90' + - VP9 video elementary stream. diff --git a/Documentation/media/uapi/v4l/pixfmt-packed-hsv.rst b/Documentation/media/uapi/v4l/pixfmt-packed-hsv.rst new file mode 100644 index 000000000000..3fdb34ce2f09 --- /dev/null +++ b/Documentation/media/uapi/v4l/pixfmt-packed-hsv.rst @@ -0,0 +1,157 @@ +.. -*- coding: utf-8; mode: rst -*- + +.. _packed-hsv: + +****************** +Packed HSV formats +****************** + +Description +=========== + +The *hue* (h) is measured in degrees, the equivalence between degrees and LSBs +depends on the hsv-encoding used, see :ref:`colorspaces`. +The *saturation* (s) and the *value* (v) are measured in percentage of the +cylinder: 0 being the smallest value and 255 the maximum. + + +The values are packed in 24 or 32 bit formats. + +.. raw:: latex + + \newline\begin{adjustbox}{width=\columnwidth} + +.. tabularcolumns:: |p{4.2cm}|p{1.0cm}|p{0.7cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.2cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.2cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.2cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{0.4cm}|p{1.7cm}| + +.. _packed-hsv-formats: + +.. flat-table:: Packed HSV Image Formats + :header-rows: 2 + :stub-columns: 0 + + * - Identifier + - Code + - + - :cspan:`7` Byte 0 in memory + - + - :cspan:`7` Byte 1 + - + - :cspan:`7` Byte 2 + - + - :cspan:`7` Byte 3 + * - + - + - Bit + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + - + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + - + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + - + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * .. _V4L2-PIX-FMT-HSV32: + + - ``V4L2_PIX_FMT_HSV32`` + - 'HSV4' + - + - + - + - + - + - + - + - + - + - + - h\ :sub:`7` + - h\ :sub:`6` + - h\ :sub:`5` + - h\ :sub:`4` + - h\ :sub:`3` + - h\ :sub:`2` + - h\ :sub:`1` + - h\ :sub:`0` + - + - s\ :sub:`7` + - s\ :sub:`6` + - s\ :sub:`5` + - s\ :sub:`4` + - s\ :sub:`3` + - s\ :sub:`2` + - s\ :sub:`1` + - s\ :sub:`0` + - + - v\ :sub:`7` + - v\ :sub:`6` + - v\ :sub:`5` + - v\ :sub:`4` + - v\ :sub:`3` + - v\ :sub:`2` + - v\ :sub:`1` + - v\ :sub:`0` + * .. _V4L2-PIX-FMT-HSV24: + + - ``V4L2_PIX_FMT_HSV24`` + - 'HSV3' + - + - h\ :sub:`7` + - h\ :sub:`6` + - h\ :sub:`5` + - h\ :sub:`4` + - h\ :sub:`3` + - h\ :sub:`2` + - h\ :sub:`1` + - h\ :sub:`0` + - + - s\ :sub:`7` + - s\ :sub:`6` + - s\ :sub:`5` + - s\ :sub:`4` + - s\ :sub:`3` + - s\ :sub:`2` + - s\ :sub:`1` + - s\ :sub:`0` + - + - v\ :sub:`7` + - v\ :sub:`6` + - v\ :sub:`5` + - v\ :sub:`4` + - v\ :sub:`3` + - v\ :sub:`2` + - v\ :sub:`1` + - v\ :sub:`0` + - + - +.. raw:: latex + + \end{adjustbox}\newline\newline + +Bit 7 is the most significant bit. diff --git a/Documentation/media/uapi/v4l/pixfmt-reserved.rst b/Documentation/media/uapi/v4l/pixfmt-reserved.rst index bd7bf3dae6af..521adb795535 100644 --- a/Documentation/media/uapi/v4l/pixfmt-reserved.rst +++ b/Documentation/media/uapi/v4l/pixfmt-reserved.rst @@ -234,7 +234,15 @@ please make a proposal on the linux-media mailing list. repeated for each line, i.e. the number of entries in the pointer array. Anything what's in between the UYVY lines is JPEG data and should be concatenated to form the JPEG stream. + * .. _V4L2-PIX-FMT-MT21C: + - ``V4L2_PIX_FMT_MT21C`` + - 'MT21' + - Compressed two-planar YVU420 format used by Mediatek MT8173. + The compression is lossless. + It is an opaque intermediate format and the MDP hardware must be + used to convert ``V4L2_PIX_FMT_MT21C`` to ``V4L2_PIX_FMT_NV12M``, + ``V4L2_PIX_FMT_YUV420M`` or ``V4L2_PIX_FMT_YVU420``. .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| diff --git a/Documentation/media/uapi/v4l/pixfmt-rgb.rst b/Documentation/media/uapi/v4l/pixfmt-rgb.rst index 9cc980882e80..b0f35136021e 100644 --- a/Documentation/media/uapi/v4l/pixfmt-rgb.rst +++ b/Documentation/media/uapi/v4l/pixfmt-rgb.rst @@ -12,9 +12,9 @@ RGB Formats pixfmt-packed-rgb pixfmt-srggb8 - pixfmt-sbggr16 pixfmt-srggb10 pixfmt-srggb10p pixfmt-srggb10alaw8 pixfmt-srggb10dpcm8 pixfmt-srggb12 + pixfmt-srggb16 diff --git a/Documentation/media/uapi/v4l/pixfmt-srggb10p.rst b/Documentation/media/uapi/v4l/pixfmt-srggb10p.rst index 9a41c8d811d0..b6d426c70ccd 100644 --- a/Documentation/media/uapi/v4l/pixfmt-srggb10p.rst +++ b/Documentation/media/uapi/v4l/pixfmt-srggb10p.rst @@ -28,7 +28,7 @@ bits of each pixel, in the same order. Each n-pixel row contains n/2 green samples and n/2 blue or red samples, with alternating green-red and green-blue rows. They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example -of one of these formats: +of a small V4L2_PIX_FMT_SBGGR10P image: **Byte Order.** Each cell is one byte. diff --git a/Documentation/media/uapi/v4l/pixfmt-srggb12.rst b/Documentation/media/uapi/v4l/pixfmt-srggb12.rst index a50ee143cb08..15041e568a0a 100644 --- a/Documentation/media/uapi/v4l/pixfmt-srggb12.rst +++ b/Documentation/media/uapi/v4l/pixfmt-srggb12.rst @@ -26,7 +26,7 @@ high bits filled with zeros. Each n-pixel row contains n/2 green samples and n/2 blue or red samples, with alternating red and blue rows. Bytes are stored in memory in little endian order. They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example -of one of these formats: +of a small V4L2_PIX_FMT_SBGGR12 image: **Byte Order.** Each cell is one byte, the 4 most significant bits in the high bytes are diff --git a/Documentation/media/uapi/v4l/pixfmt-sbggr16.rst b/Documentation/media/uapi/v4l/pixfmt-srggb16.rst similarity index 52% rename from Documentation/media/uapi/v4l/pixfmt-sbggr16.rst rename to Documentation/media/uapi/v4l/pixfmt-srggb16.rst index 6f7f327db85c..d407b2b2050f 100644 --- a/Documentation/media/uapi/v4l/pixfmt-sbggr16.rst +++ b/Documentation/media/uapi/v4l/pixfmt-srggb16.rst @@ -1,21 +1,28 @@ .. -*- coding: utf-8; mode: rst -*- -.. _V4L2-PIX-FMT-SBGGR16: +.. _V4L2-PIX-FMT-SRGGB16: +.. _v4l2-pix-fmt-sbggr16: +.. _v4l2-pix-fmt-sgbrg16: +.. _v4l2-pix-fmt-sgrbg16: -***************************** -V4L2_PIX_FMT_SBGGR16 ('BYR2') -***************************** -Bayer RGB format +*************************************************************************************************************************** +V4L2_PIX_FMT_SRGGB16 ('RG16'), V4L2_PIX_FMT_SGRBG16 ('GR16'), V4L2_PIX_FMT_SGBRG16 ('GB16'), V4L2_PIX_FMT_SBGGR16 ('BYR2'), +*************************************************************************************************************************** + + +16-bit Bayer formats Description =========== -This format is similar to -:ref:`V4L2_PIX_FMT_SBGGR8 `, except each pixel -has a depth of 16 bits. The least significant byte is stored at lower -memory addresses (little-endian). +These four pixel formats are raw sRGB / Bayer formats with 16 bits per +sample. Each sample is stored in a 16-bit word. Each n-pixel row contains +n/2 green samples and n/2 blue or red samples, with alternating red and blue +rows. Bytes are stored in memory in little endian order. They are +conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is +an example of a small V4L2_PIX_FMT_SBGGR16 image: **Byte Order.** Each cell is one byte. diff --git a/Documentation/media/uapi/v4l/pixfmt-srggb8.rst b/Documentation/media/uapi/v4l/pixfmt-srggb8.rst index a3987d2e97fd..5ac25a634d30 100644 --- a/Documentation/media/uapi/v4l/pixfmt-srggb8.rst +++ b/Documentation/media/uapi/v4l/pixfmt-srggb8.rst @@ -20,7 +20,7 @@ These four pixel formats are raw sRGB / Bayer formats with 8 bits per sample. Each sample is stored in a byte. Each n-pixel row contains n/2 green samples and n/2 blue or red samples, with alternating red and blue rows. They are conventionally described as GRGR... BGBG..., -RGRG... GBGB..., etc. Below is an example of one of these formats: +RGRG... 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SDR API. +- Ribalda, Ricardo + + - Introduce HSV formats and other minor changes. + - Rubli, Martin - Designed and documented the VIDIOC_ENUM_FRAMESIZES and VIDIOC_ENUM_FRAMEINTERVALS ioctls. @@ -89,6 +93,11 @@ part can be used and distributed without restrictions. Revision History **************** +:revision: 4.10 / 2016-07-15 (*rr*) + +Introduce HSV formats. + + :revision: 4.5 / 2015-10-29 (*rr*) Extend VIDIOC_G_EXT_CTRLS;. Replace ctrl_class with a new union with diff --git a/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst b/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst index 7dd943ff14cd..aea276502f5e 100644 --- a/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst +++ b/Documentation/media/uapi/v4l/vidioc-g-dv-timings.rst @@ -270,3 +270,14 @@ EBUSY - Some formats like SMPTE-125M have an interlaced signal with a odd total height. For these formats, if this flag is set, the first field has the extra line. Else, it is the second field. + * - ``V4L2_DV_FL_HAS_PICTURE_ASPECT`` + - If set, then the picture_aspect field is valid. Otherwise assume that + the pixels are square, so the picture aspect ratio is the same as the + width to height ratio. + * - ``V4L2_DV_FL_HAS_CEA861_VIC`` + - If set, then the cea861_vic field is valid and contains the Video + Identification Code as per the CEA-861 standard. + * - ``V4L2_DV_FL_HAS_HDMI_VIC`` + - If set, then the hdmi_vic field is valid and contains the Video + Identification Code as per the HDMI standard (HDMI Vendor Specific + InfoFrame). diff --git a/Documentation/media/uapi/v4l/vidioc-g-tuner.rst b/Documentation/media/uapi/v4l/vidioc-g-tuner.rst index e8aa8cd7065f..57c79fa43866 100644 --- a/Documentation/media/uapi/v4l/vidioc-g-tuner.rst +++ b/Documentation/media/uapi/v4l/vidioc-g-tuner.rst @@ -201,10 +201,10 @@ To change the radio frequency the * - ``V4L2_TUNER_SDR`` - 4 - Tuner controls the A/D and/or D/A block of a - Sofware Digital Radio (SDR) + Software Digital Radio (SDR) * - ``V4L2_TUNER_RF`` - 5 - - Tuner controls the RF part of a Sofware Digital Radio (SDR) + - Tuner controls the RF part of a Software Digital Radio (SDR) .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| diff --git a/Documentation/media/v4l-drivers/au0828-cardlist.rst b/Documentation/media/v4l-drivers/au0828-cardlist.rst index aed51b4ffb46..82d2567bc7c1 100644 --- a/Documentation/media/v4l-drivers/au0828-cardlist.rst +++ b/Documentation/media/v4l-drivers/au0828-cardlist.rst @@ -1,11 +1,13 @@ AU0828 cards list ================= -.. code-block:: none - - 0 -> Unknown board (au0828) - 1 -> Hauppauge HVR950Q (au0828) [2040:7200,2040:7210,2040:7217,2040:721b,2040:721e,2040:721f,2040:7280,0fd9:0008,2040:7260,2040:7213,2040:7270] - 2 -> Hauppauge HVR850 (au0828) [2040:7240] - 3 -> DViCO FusionHDTV USB (au0828) [0fe9:d620] - 4 -> Hauppauge HVR950Q rev xxF8 (au0828) [2040:7201,2040:7211,2040:7281] - 5 -> Hauppauge Woodbury (au0828) [05e1:0480,2040:8200] +=========== ========================== ======================================================================================================================= +Card number Card name USB IDs +=========== ========================== ======================================================================================================================= +0 Unknown board +1 Hauppauge HVR950Q 2040:7200, 2040:7210, 2040:7217, 2040:721b, 2040:721e, 2040:721f, 2040:7280, 0fd9:0008, 2040:7260, 2040:7213, 2040:7270 +2 Hauppauge HVR850 2040:7240 +3 DViCO FusionHDTV USB 0fe9:d620 +4 Hauppauge HVR950Q rev xxF8 2040:7201, 2040:7211, 2040:7281 +5 Hauppauge Woodbury 05e1:0480, 2040:8200 +=========== ========================== ======================================================================================================================= diff --git a/Documentation/media/v4l-drivers/bttv-cardlist.rst b/Documentation/media/v4l-drivers/bttv-cardlist.rst index 97a966e7f9c4..28a01cd6cf2e 100644 --- a/Documentation/media/v4l-drivers/bttv-cardlist.rst +++ b/Documentation/media/v4l-drivers/bttv-cardlist.rst @@ -1,172 +1,174 @@ BTTV cards list =============== -.. code-block:: none - - 0 -> *** UNKNOWN/GENERIC *** - 1 -> MIRO PCTV - 2 -> Hauppauge (bt848) - 3 -> STB, Gateway P/N 6000699 (bt848) - 4 -> Intel Create and Share PCI/ Smart Video Recorder III - 5 -> Diamond DTV2000 - 6 -> AVerMedia TVPhone - 7 -> MATRIX-Vision MV-Delta - 8 -> Lifeview FlyVideo II (Bt848) LR26 / MAXI TV Video PCI2 LR26 - 9 -> IMS/IXmicro TurboTV - 10 -> Hauppauge (bt878) [0070:13eb,0070:3900,2636:10b4] - 11 -> MIRO PCTV pro - 12 -> ADS Technologies Channel Surfer TV (bt848) - 13 -> AVerMedia TVCapture 98 [1461:0002,1461:0004,1461:0300] - 14 -> Aimslab Video Highway Xtreme (VHX) - 15 -> Zoltrix TV-Max [a1a0:a0fc] - 16 -> Prolink Pixelview PlayTV (bt878) - 17 -> Leadtek WinView 601 - 18 -> AVEC Intercapture - 19 -> Lifeview FlyVideo II EZ /FlyKit LR38 Bt848 (capture only) - 20 -> CEI Raffles Card - 21 -> Lifeview FlyVideo 98/ Lucky Star Image World ConferenceTV LR50 - 22 -> Askey CPH050/ Phoebe Tv Master + FM [14ff:3002] - 23 -> Modular Technology MM201/MM202/MM205/MM210/MM215 PCTV, bt878 [14c7:0101] - 24 -> Askey CPH05X/06X (bt878) [many vendors] [144f:3002,144f:3005,144f:5000,14ff:3000] - 25 -> Terratec TerraTV+ Version 1.0 (Bt848)/ Terra TValue Version 1.0/ Vobis TV-Boostar - 26 -> Hauppauge WinCam newer (bt878) - 27 -> Lifeview FlyVideo 98/ MAXI TV Video PCI2 LR50 - 28 -> Terratec TerraTV+ Version 1.1 (bt878) [153b:1127,1852:1852] - 29 -> Imagenation PXC200 [1295:200a] - 30 -> Lifeview FlyVideo 98 LR50 [1f7f:1850] - 31 -> Formac iProTV, Formac ProTV I (bt848) - 32 -> Intel Create and Share PCI/ Smart Video Recorder III - 33 -> Terratec TerraTValue Version Bt878 [153b:1117,153b:1118,153b:1119,153b:111a,153b:1134,153b:5018] - 34 -> Leadtek WinFast 2000/ WinFast 2000 XP [107d:6606,107d:6609,6606:217d,f6ff:fff6] - 35 -> Lifeview FlyVideo 98 LR50 / Chronos Video Shuttle II [1851:1850,1851:a050] - 36 -> Lifeview FlyVideo 98FM LR50 / Typhoon TView TV/FM Tuner [1852:1852] - 37 -> Prolink PixelView PlayTV pro - 38 -> Askey CPH06X TView99 [144f:3000,144f:a005,a04f:a0fc] - 39 -> Pinnacle PCTV Studio/Rave [11bd:0012,bd11:1200,bd11:ff00,11bd:ff12] - 40 -> STB TV PCI FM, Gateway P/N 6000704 (bt878), 3Dfx VoodooTV 100 [10b4:2636,10b4:2645,121a:3060] - 41 -> AVerMedia TVPhone 98 [1461:0001,1461:0003] - 42 -> ProVideo PV951 [aa0c:146c] - 43 -> Little OnAir TV - 44 -> Sigma TVII-FM - 45 -> MATRIX-Vision MV-Delta 2 - 46 -> Zoltrix Genie TV/FM [15b0:4000,15b0:400a,15b0:400d,15b0:4010,15b0:4016] - 47 -> Terratec TV/Radio+ [153b:1123] - 48 -> Askey CPH03x/ Dynalink Magic TView - 49 -> IODATA GV-BCTV3/PCI [10fc:4020] - 50 -> Prolink PV-BT878P+4E / PixelView PlayTV PAK / Lenco MXTV-9578 CP - 51 -> Eagle Wireless Capricorn2 (bt878A) - 52 -> Pinnacle PCTV Studio Pro - 53 -> Typhoon TView RDS + FM Stereo / KNC1 TV Station RDS - 54 -> Lifeview FlyVideo 2000 /FlyVideo A2/ Lifetec LT 9415 TV [LR90] - 55 -> Askey CPH031/ BESTBUY Easy TV - 56 -> Lifeview FlyVideo 98FM LR50 [a051:41a0] - 57 -> GrandTec 'Grand Video Capture' (Bt848) [4344:4142] - 58 -> Askey CPH060/ Phoebe TV Master Only (No FM) - 59 -> Askey CPH03x TV Capturer - 60 -> Modular Technology MM100PCTV - 61 -> AG Electronics GMV1 [15cb:0101] - 62 -> Askey CPH061/ BESTBUY Easy TV (bt878) - 63 -> ATI TV-Wonder [1002:0001] - 64 -> ATI TV-Wonder VE [1002:0003] - 65 -> Lifeview FlyVideo 2000S LR90 - 66 -> Terratec TValueRadio [153b:1135,153b:ff3b] - 67 -> IODATA GV-BCTV4/PCI [10fc:4050] - 68 -> 3Dfx VoodooTV FM (Euro) [10b4:2637] - 69 -> Active Imaging AIMMS - 70 -> Prolink Pixelview PV-BT878P+ (Rev.4C,8E) - 71 -> Lifeview FlyVideo 98EZ (capture only) LR51 [1851:1851] - 72 -> Prolink Pixelview PV-BT878P+9B (PlayTV Pro rev.9B FM+NICAM) [1554:4011] - 73 -> Sensoray 311/611 [6000:0311,6000:0611] - 74 -> RemoteVision MX (RV605) - 75 -> Powercolor MTV878/ MTV878R/ MTV878F - 76 -> Canopus WinDVR PCI (COMPAQ Presario 3524JP, 5112JP) [0e11:0079] - 77 -> GrandTec Multi Capture Card (Bt878) - 78 -> Jetway TV/Capture JW-TV878-FBK, Kworld KW-TV878RF [0a01:17de] - 79 -> DSP Design TCVIDEO - 80 -> Hauppauge WinTV PVR [0070:4500] - 81 -> IODATA GV-BCTV5/PCI [10fc:4070,10fc:d018] - 82 -> Osprey 100/150 (878) [0070:ff00] - 83 -> Osprey 100/150 (848) - 84 -> Osprey 101 (848) - 85 -> Osprey 101/151 - 86 -> Osprey 101/151 w/ svid - 87 -> Osprey 200/201/250/251 - 88 -> Osprey 200/250 [0070:ff01] - 89 -> Osprey 210/220/230 - 90 -> Osprey 500 [0070:ff02] - 91 -> Osprey 540 [0070:ff04] - 92 -> Osprey 2000 [0070:ff03] - 93 -> IDS Eagle - 94 -> Pinnacle PCTV Sat [11bd:001c] - 95 -> Formac ProTV II (bt878) - 96 -> MachTV - 97 -> Euresys Picolo - 98 -> ProVideo PV150 [aa00:1460,aa01:1461,aa02:1462,aa03:1463,aa04:1464,aa05:1465,aa06:1466,aa07:1467] - 99 -> AD-TVK503 - 100 -> Hercules Smart TV Stereo - 101 -> Pace TV & Radio Card - 102 -> IVC-200 [0000:a155,0001:a155,0002:a155,0003:a155,0100:a155,0101:a155,0102:a155,0103:a155,0800:a155,0801:a155,0802:a155,0803:a155] - 103 -> Grand X-Guard / Trust 814PCI [0304:0102] - 104 -> Nebula Electronics DigiTV [0071:0101] - 105 -> ProVideo PV143 [aa00:1430,aa00:1431,aa00:1432,aa00:1433,aa03:1433] - 106 -> PHYTEC VD-009-X1 VD-011 MiniDIN (bt878) - 107 -> PHYTEC VD-009-X1 VD-011 Combi (bt878) - 108 -> PHYTEC VD-009 MiniDIN (bt878) - 109 -> PHYTEC VD-009 Combi (bt878) - 110 -> IVC-100 [ff00:a132] - 111 -> IVC-120G [ff00:a182,ff01:a182,ff02:a182,ff03:a182,ff04:a182,ff05:a182,ff06:a182,ff07:a182,ff08:a182,ff09:a182,ff0a:a182,ff0b:a182,ff0c:a182,ff0d:a182,ff0e:a182,ff0f:a182] - 112 -> pcHDTV HD-2000 TV [7063:2000] - 113 -> Twinhan DST + clones [11bd:0026,1822:0001,270f:fc00,1822:0026] - 114 -> Winfast VC100 [107d:6607] - 115 -> Teppro TEV-560/InterVision IV-560 - 116 -> SIMUS GVC1100 [aa6a:82b2] - 117 -> NGS NGSTV+ - 118 -> LMLBT4 - 119 -> Tekram M205 PRO - 120 -> Conceptronic CONTVFMi - 121 -> Euresys Picolo Tetra [1805:0105,1805:0106,1805:0107,1805:0108] - 122 -> Spirit TV Tuner - 123 -> AVerMedia AVerTV DVB-T 771 [1461:0771] - 124 -> AverMedia AverTV DVB-T 761 [1461:0761] - 125 -> MATRIX Vision Sigma-SQ - 126 -> MATRIX Vision Sigma-SLC - 127 -> APAC Viewcomp 878(AMAX) - 128 -> DViCO FusionHDTV DVB-T Lite [18ac:db10,18ac:db11] - 129 -> V-Gear MyVCD - 130 -> Super TV Tuner - 131 -> Tibet Systems 'Progress DVR' CS16 - 132 -> Kodicom 4400R (master) - 133 -> Kodicom 4400R (slave) - 134 -> Adlink RTV24 - 135 -> DViCO FusionHDTV 5 Lite [18ac:d500] - 136 -> Acorp Y878F [9511:1540] - 137 -> Conceptronic CTVFMi v2 [036e:109e] - 138 -> Prolink Pixelview PV-BT878P+ (Rev.2E) - 139 -> Prolink PixelView PlayTV MPEG2 PV-M4900 - 140 -> Osprey 440 [0070:ff07] - 141 -> Asound Skyeye PCTV - 142 -> Sabrent TV-FM (bttv version) - 143 -> Hauppauge ImpactVCB (bt878) [0070:13eb] - 144 -> MagicTV - 145 -> SSAI Security Video Interface [4149:5353] - 146 -> SSAI Ultrasound Video Interface [414a:5353] - 147 -> VoodooTV 200 (USA) [121a:3000] - 148 -> DViCO FusionHDTV 2 [dbc0:d200] - 149 -> Typhoon TV-Tuner PCI (50684) - 150 -> Geovision GV-600 [008a:763c] - 151 -> Kozumi KTV-01C - 152 -> Encore ENL TV-FM-2 [1000:1801] - 153 -> PHYTEC VD-012 (bt878) - 154 -> PHYTEC VD-012-X1 (bt878) - 155 -> PHYTEC VD-012-X2 (bt878) - 156 -> IVCE-8784 [0000:f050,0001:f050,0002:f050,0003:f050] - 157 -> Geovision GV-800(S) (master) [800a:763d] - 158 -> Geovision GV-800(S) (slave) [800b:763d,800c:763d,800d:763d] - 159 -> ProVideo PV183 [1830:1540,1831:1540,1832:1540,1833:1540,1834:1540,1835:1540,1836:1540,1837:1540] - 160 -> Tongwei Video Technology TD-3116 [f200:3116] - 161 -> Aposonic W-DVR [0279:0228] - 162 -> Adlink MPG24 - 163 -> Bt848 Capture 14MHz - 164 -> CyberVision CV06 (SV) - 165 -> Kworld V-Stream Xpert TV PVR878 - 166 -> PCI-8604PW +=========== ================================================================================= ============================================================================================================================================================================== +Card number Card name PCI IDs +=========== ================================================================================= ============================================================================================================================================================================== +0 *** UNKNOWN/GENERIC *** +1 MIRO PCTV +2 Hauppauge (bt848) +3 STB, Gateway P/N 6000699 (bt848) +4 Intel Create and Share PCI/ Smart Video Recorder III +5 Diamond DTV2000 +6 AVerMedia TVPhone +7 MATRIX-Vision MV-Delta +8 Lifeview FlyVideo II (Bt848) LR26 / MAXI TV Video PCI2 LR26 +9 IMS/IXmicro TurboTV +10 Hauppauge (bt878) 0070:13eb, 0070:3900, 2636:10b4 +11 MIRO PCTV pro +12 ADS Technologies Channel Surfer TV (bt848) +13 AVerMedia TVCapture 98 1461:0002, 1461:0004, 1461:0300 +14 Aimslab Video Highway Xtreme (VHX) +15 Zoltrix TV-Max a1a0:a0fc +16 Prolink Pixelview PlayTV (bt878) +17 Leadtek WinView 601 +18 AVEC Intercapture +19 Lifeview FlyVideo II EZ /FlyKit LR38 Bt848 (capture only) +20 CEI Raffles Card +21 Lifeview FlyVideo 98/ Lucky Star Image World ConferenceTV LR50 +22 Askey CPH050/ Phoebe Tv Master + FM 14ff:3002 +23 Modular Technology MM201/MM202/MM205/MM210/MM215 PCTV, bt878 14c7:0101 +24 Askey CPH05X/06X (bt878) [many vendors] 144f:3002, 144f:3005, 144f:5000, 14ff:3000 +25 Terratec TerraTV+ Version 1.0 (Bt848)/ Terra TValue Version 1.0/ Vobis TV-Boostar +26 Hauppauge WinCam newer (bt878) +27 Lifeview FlyVideo 98/ MAXI TV Video PCI2 LR50 +28 Terratec TerraTV+ Version 1.1 (bt878) 153b:1127, 1852:1852 +29 Imagenation PXC200 1295:200a +30 Lifeview FlyVideo 98 LR50 1f7f:1850 +31 Formac iProTV, Formac ProTV I (bt848) +32 Intel Create and Share PCI/ Smart Video Recorder III +33 Terratec TerraTValue Version Bt878 153b:1117, 153b:1118, 153b:1119, 153b:111a, 153b:1134, 153b:5018 +34 Leadtek WinFast 2000/ WinFast 2000 XP 107d:6606, 107d:6609, 6606:217d, f6ff:fff6 +35 Lifeview FlyVideo 98 LR50 / Chronos Video Shuttle II 1851:1850, 1851:a050 +36 Lifeview FlyVideo 98FM LR50 / Typhoon TView TV/FM Tuner 1852:1852 +37 Prolink PixelView PlayTV pro +38 Askey CPH06X TView99 144f:3000, 144f:a005, a04f:a0fc +39 Pinnacle PCTV Studio/Rave 11bd:0012, bd11:1200, bd11:ff00, 11bd:ff12 +40 STB TV PCI FM, Gateway P/N 6000704 (bt878), 3Dfx VoodooTV 100 10b4:2636, 10b4:2645, 121a:3060 +41 AVerMedia TVPhone 98 1461:0001, 1461:0003 +42 ProVideo PV951 aa0c:146c +43 Little OnAir TV +44 Sigma TVII-FM +45 MATRIX-Vision MV-Delta 2 +46 Zoltrix Genie TV/FM 15b0:4000, 15b0:400a, 15b0:400d, 15b0:4010, 15b0:4016 +47 Terratec TV/Radio+ 153b:1123 +48 Askey CPH03x/ Dynalink Magic TView +49 IODATA GV-BCTV3/PCI 10fc:4020 +50 Prolink PV-BT878P+4E / PixelView PlayTV PAK / Lenco MXTV-9578 CP +51 Eagle Wireless Capricorn2 (bt878A) +52 Pinnacle PCTV Studio Pro +53 Typhoon TView RDS + FM Stereo / KNC1 TV Station RDS +54 Lifeview FlyVideo 2000 /FlyVideo A2/ Lifetec LT 9415 TV [LR90] +55 Askey CPH031/ BESTBUY Easy TV +56 Lifeview FlyVideo 98FM LR50 a051:41a0 +57 GrandTec 'Grand Video Capture' (Bt848) 4344:4142 +58 Askey CPH060/ Phoebe TV Master Only (No FM) +59 Askey CPH03x TV Capturer +60 Modular Technology MM100PCTV +61 AG Electronics GMV1 15cb:0101 +62 Askey CPH061/ BESTBUY Easy TV (bt878) +63 ATI TV-Wonder 1002:0001 +64 ATI TV-Wonder VE 1002:0003 +65 Lifeview FlyVideo 2000S LR90 +66 Terratec TValueRadio 153b:1135, 153b:ff3b +67 IODATA GV-BCTV4/PCI 10fc:4050 +68 3Dfx VoodooTV FM (Euro) 10b4:2637 +69 Active Imaging AIMMS +70 Prolink Pixelview PV-BT878P+ (Rev.4C,8E) +71 Lifeview FlyVideo 98EZ (capture only) LR51 1851:1851 +72 Prolink Pixelview PV-BT878P+9B (PlayTV Pro rev.9B FM+NICAM) 1554:4011 +73 Sensoray 311/611 6000:0311, 6000:0611 +74 RemoteVision MX (RV605) +75 Powercolor MTV878/ MTV878R/ MTV878F +76 Canopus WinDVR PCI (COMPAQ Presario 3524JP, 5112JP) 0e11:0079 +77 GrandTec Multi Capture Card (Bt878) +78 Jetway TV/Capture JW-TV878-FBK, Kworld KW-TV878RF 0a01:17de +79 DSP Design TCVIDEO +80 Hauppauge WinTV PVR 0070:4500 +81 IODATA GV-BCTV5/PCI 10fc:4070, 10fc:d018 +82 Osprey 100/150 (878) 0070:ff00 +83 Osprey 100/150 (848) +84 Osprey 101 (848) +85 Osprey 101/151 +86 Osprey 101/151 w/ svid +87 Osprey 200/201/250/251 +88 Osprey 200/250 0070:ff01 +89 Osprey 210/220/230 +90 Osprey 500 0070:ff02 +91 Osprey 540 0070:ff04 +92 Osprey 2000 0070:ff03 +93 IDS Eagle +94 Pinnacle PCTV Sat 11bd:001c +95 Formac ProTV II (bt878) +96 MachTV +97 Euresys Picolo +98 ProVideo PV150 aa00:1460, aa01:1461, aa02:1462, aa03:1463, aa04:1464, aa05:1465, aa06:1466, aa07:1467 +99 AD-TVK503 +100 Hercules Smart TV Stereo +101 Pace TV & Radio Card +102 IVC-200 0000:a155, 0001:a155, 0002:a155, 0003:a155, 0100:a155, 0101:a155, 0102:a155, 0103:a155, 0800:a155, 0801:a155, 0802:a155, 0803:a155 +103 Grand X-Guard / Trust 814PCI 0304:0102 +104 Nebula Electronics DigiTV 0071:0101 +105 ProVideo PV143 aa00:1430, aa00:1431, aa00:1432, aa00:1433, aa03:1433 +106 PHYTEC VD-009-X1 VD-011 MiniDIN (bt878) +107 PHYTEC VD-009-X1 VD-011 Combi (bt878) +108 PHYTEC VD-009 MiniDIN (bt878) +109 PHYTEC VD-009 Combi (bt878) +110 IVC-100 ff00:a132 +111 IVC-120G ff00:a182, ff01:a182, ff02:a182, ff03:a182, ff04:a182, ff05:a182, ff06:a182, ff07:a182, ff08:a182, ff09:a182, ff0a:a182, ff0b:a182, ff0c:a182, ff0d:a182, ff0e:a182, ff0f:a182 +112 pcHDTV HD-2000 TV 7063:2000 +113 Twinhan DST + clones 11bd:0026, 1822:0001, 270f:fc00, 1822:0026 +114 Winfast VC100 107d:6607 +115 Teppro TEV-560/InterVision IV-560 +116 SIMUS GVC1100 aa6a:82b2 +117 NGS NGSTV+ +118 LMLBT4 +119 Tekram M205 PRO +120 Conceptronic CONTVFMi +121 Euresys Picolo Tetra 1805:0105, 1805:0106, 1805:0107, 1805:0108 +122 Spirit TV Tuner +123 AVerMedia AVerTV DVB-T 771 1461:0771 +124 AverMedia AverTV DVB-T 761 1461:0761 +125 MATRIX Vision Sigma-SQ +126 MATRIX Vision Sigma-SLC +127 APAC Viewcomp 878(AMAX) +128 DViCO FusionHDTV DVB-T Lite 18ac:db10, 18ac:db11 +129 V-Gear MyVCD +130 Super TV Tuner +131 Tibet Systems 'Progress DVR' CS16 +132 Kodicom 4400R (master) +133 Kodicom 4400R (slave) +134 Adlink RTV24 +135 DViCO FusionHDTV 5 Lite 18ac:d500 +136 Acorp Y878F 9511:1540 +137 Conceptronic CTVFMi v2 036e:109e +138 Prolink Pixelview PV-BT878P+ (Rev.2E) +139 Prolink PixelView PlayTV MPEG2 PV-M4900 +140 Osprey 440 0070:ff07 +141 Asound Skyeye PCTV +142 Sabrent TV-FM (bttv version) +143 Hauppauge ImpactVCB (bt878) 0070:13eb +144 MagicTV +145 SSAI Security Video Interface 4149:5353 +146 SSAI Ultrasound Video Interface 414a:5353 +147 VoodooTV 200 (USA) 121a:3000 +148 DViCO FusionHDTV 2 dbc0:d200 +149 Typhoon TV-Tuner PCI (50684) +150 Geovision GV-600 008a:763c +151 Kozumi KTV-01C +152 Encore ENL TV-FM-2 1000:1801 +153 PHYTEC VD-012 (bt878) +154 PHYTEC VD-012-X1 (bt878) +155 PHYTEC VD-012-X2 (bt878) +156 IVCE-8784 0000:f050, 0001:f050, 0002:f050, 0003:f050 +157 Geovision GV-800(S) (master) 800a:763d +158 Geovision GV-800(S) (slave) 800b:763d, 800c:763d, 800d:763d +159 ProVideo PV183 1830:1540, 1831:1540, 1832:1540, 1833:1540, 1834:1540, 1835:1540, 1836:1540, 1837:1540 +160 Tongwei Video Technology TD-3116 f200:3116 +161 Aposonic W-DVR 0279:0228 +162 Adlink MPG24 +163 Bt848 Capture 14MHz +164 CyberVision CV06 (SV) +165 Kworld V-Stream Xpert TV PVR878 +166 PCI-8604PW +=========== ================================================================================= ============================================================================================================================================================================== diff --git a/Documentation/media/v4l-drivers/cx23885-cardlist.rst b/Documentation/media/v4l-drivers/cx23885-cardlist.rst index f38003255b9a..fd20b50d2c1d 100644 --- a/Documentation/media/v4l-drivers/cx23885-cardlist.rst +++ b/Documentation/media/v4l-drivers/cx23885-cardlist.rst @@ -1,63 +1,65 @@ cx23885 cards list ================== -.. code-block:: none - - 0 -> UNKNOWN/GENERIC [0070:3400] - 1 -> Hauppauge WinTV-HVR1800lp [0070:7600] - 2 -> Hauppauge WinTV-HVR1800 [0070:7800,0070:7801,0070:7809] - 3 -> Hauppauge WinTV-HVR1250 [0070:7911] - 4 -> DViCO FusionHDTV5 Express [18ac:d500] - 5 -> Hauppauge WinTV-HVR1500Q [0070:7790,0070:7797] - 6 -> Hauppauge WinTV-HVR1500 [0070:7710,0070:7717] - 7 -> Hauppauge WinTV-HVR1200 [0070:71d1,0070:71d3] - 8 -> Hauppauge WinTV-HVR1700 [0070:8101] - 9 -> Hauppauge WinTV-HVR1400 [0070:8010] - 10 -> DViCO FusionHDTV7 Dual Express [18ac:d618] - 11 -> DViCO FusionHDTV DVB-T Dual Express [18ac:db78] - 12 -> Leadtek Winfast PxDVR3200 H [107d:6681] - 13 -> Compro VideoMate E650F [185b:e800] - 14 -> TurboSight TBS 6920 [6920:8888] - 15 -> TeVii S470 [d470:9022] - 16 -> DVBWorld DVB-S2 2005 [0001:2005] - 17 -> NetUP Dual DVB-S2 CI [1b55:2a2c] - 18 -> Hauppauge WinTV-HVR1270 [0070:2211] - 19 -> Hauppauge WinTV-HVR1275 [0070:2215,0070:221d,0070:22f2] - 20 -> Hauppauge WinTV-HVR1255 [0070:2251,0070:22f1] - 21 -> Hauppauge WinTV-HVR1210 [0070:2291,0070:2295,0070:2299,0070:229d,0070:22f0,0070:22f3,0070:22f4,0070:22f5] - 22 -> Mygica X8506 DMB-TH [14f1:8651] - 23 -> Magic-Pro ProHDTV Extreme 2 [14f1:8657] - 24 -> Hauppauge WinTV-HVR1850 [0070:8541] - 25 -> Compro VideoMate E800 [1858:e800] - 26 -> Hauppauge WinTV-HVR1290 [0070:8551] - 27 -> Mygica X8558 PRO DMB-TH [14f1:8578] - 28 -> LEADTEK WinFast PxTV1200 [107d:6f22] - 29 -> GoTView X5 3D Hybrid [5654:2390] - 30 -> NetUP Dual DVB-T/C-CI RF [1b55:e2e4] - 31 -> Leadtek Winfast PxDVR3200 H XC4000 [107d:6f39] - 32 -> MPX-885 - 33 -> Mygica X8502/X8507 ISDB-T [14f1:8502] - 34 -> TerraTec Cinergy T PCIe Dual [153b:117e] - 35 -> TeVii S471 [d471:9022] - 36 -> Hauppauge WinTV-HVR1255 [0070:2259] - 37 -> Prof Revolution DVB-S2 8000 [8000:3034] - 38 -> Hauppauge WinTV-HVR4400/HVR5500 [0070:c108,0070:c138,0070:c1f8] - 39 -> AVerTV Hybrid Express Slim HC81R [1461:d939] - 40 -> TurboSight TBS 6981 [6981:8888] - 41 -> TurboSight TBS 6980 [6980:8888] - 42 -> Leadtek Winfast PxPVR2200 [107d:6f21] - 43 -> Hauppauge ImpactVCB-e [0070:7133] - 44 -> DViCO FusionHDTV DVB-T Dual Express2 [18ac:db98] - 45 -> DVBSky T9580 [4254:9580] - 46 -> DVBSky T980C [4254:980c] - 47 -> DVBSky S950C [4254:950c] - 48 -> Technotrend TT-budget CT2-4500 CI [13c2:3013] - 49 -> DVBSky S950 [4254:0950] - 50 -> DVBSky S952 [4254:0952] - 51 -> DVBSky T982 [4254:0982] - 52 -> Hauppauge WinTV-HVR5525 [0070:f038] - 53 -> Hauppauge WinTV Starburst [0070:c12a] - 54 -> ViewCast 260e [1576:0260] - 55 -> ViewCast 460e [1576:0460] - 56 -> Hauppauge WinTV-QuadHD-DVB [0070:6a28,0070:6b28] - 57 -> Hauppauge WinTV-QuadHD-ATSC [0070:6a18,0070:6b18] +=========== ==================================== ====================================================================================== +Card number Card name PCI IDs +=========== ==================================== ====================================================================================== +0 UNKNOWN/GENERIC 0070:3400 +1 Hauppauge WinTV-HVR1800lp 0070:7600 +2 Hauppauge WinTV-HVR1800 0070:7800, 0070:7801, 0070:7809 +3 Hauppauge WinTV-HVR1250 0070:7911 +4 DViCO FusionHDTV5 Express 18ac:d500 +5 Hauppauge WinTV-HVR1500Q 0070:7790, 0070:7797 +6 Hauppauge WinTV-HVR1500 0070:7710, 0070:7717 +7 Hauppauge WinTV-HVR1200 0070:71d1, 0070:71d3 +8 Hauppauge WinTV-HVR1700 0070:8101 +9 Hauppauge WinTV-HVR1400 0070:8010 +10 DViCO FusionHDTV7 Dual Express 18ac:d618 +11 DViCO FusionHDTV DVB-T Dual Express 18ac:db78 +12 Leadtek Winfast PxDVR3200 H 107d:6681 +13 Compro VideoMate E650F 185b:e800 +14 TurboSight TBS 6920 6920:8888 +15 TeVii S470 d470:9022 +16 DVBWorld DVB-S2 2005 0001:2005 +17 NetUP Dual DVB-S2 CI 1b55:2a2c +18 Hauppauge WinTV-HVR1270 0070:2211 +19 Hauppauge WinTV-HVR1275 0070:2215, 0070:221d, 0070:22f2 +20 Hauppauge WinTV-HVR1255 0070:2251, 0070:22f1 +21 Hauppauge WinTV-HVR1210 0070:2291, 0070:2295, 0070:2299, 0070:229d, 0070:22f0, 0070:22f3, 0070:22f4, 0070:22f5 +22 Mygica X8506 DMB-TH 14f1:8651 +23 Magic-Pro ProHDTV Extreme 2 14f1:8657 +24 Hauppauge WinTV-HVR1850 0070:8541 +25 Compro VideoMate E800 1858:e800 +26 Hauppauge WinTV-HVR1290 0070:8551 +27 Mygica X8558 PRO DMB-TH 14f1:8578 +28 LEADTEK WinFast PxTV1200 107d:6f22 +29 GoTView X5 3D Hybrid 5654:2390 +30 NetUP Dual DVB-T/C-CI RF 1b55:e2e4 +31 Leadtek Winfast PxDVR3200 H XC4000 107d:6f39 +32 MPX-885 +33 Mygica X8502/X8507 ISDB-T 14f1:8502 +34 TerraTec Cinergy T PCIe Dual 153b:117e +35 TeVii S471 d471:9022 +36 Hauppauge WinTV-HVR1255 0070:2259 +37 Prof Revolution DVB-S2 8000 8000:3034 +38 Hauppauge WinTV-HVR4400/HVR5500 0070:c108, 0070:c138, 0070:c1f8 +39 AVerTV Hybrid Express Slim HC81R 1461:d939 +40 TurboSight TBS 6981 6981:8888 +41 TurboSight TBS 6980 6980:8888 +42 Leadtek Winfast PxPVR2200 107d:6f21 +43 Hauppauge ImpactVCB-e 0070:7133 +44 DViCO FusionHDTV DVB-T Dual Express2 18ac:db98 +45 DVBSky T9580 4254:9580 +46 DVBSky T980C 4254:980c +47 DVBSky S950C 4254:950c +48 Technotrend TT-budget CT2-4500 CI 13c2:3013 +49 DVBSky S950 4254:0950 +50 DVBSky S952 4254:0952 +51 DVBSky T982 4254:0982 +52 Hauppauge WinTV-HVR5525 0070:f038 +53 Hauppauge WinTV Starburst 0070:c12a +54 ViewCast 260e 1576:0260 +55 ViewCast 460e 1576:0460 +56 Hauppauge WinTV-QuadHD-DVB 0070:6a28, 0070:6b28 +57 Hauppauge WinTV-QuadHD-ATSC 0070:6a18, 0070:6b18 +=========== ==================================== ====================================================================================== diff --git a/Documentation/media/v4l-drivers/cx88-cardlist.rst b/Documentation/media/v4l-drivers/cx88-cardlist.rst index 01128341e1ea..8cc1cea17035 100644 --- a/Documentation/media/v4l-drivers/cx88-cardlist.rst +++ b/Documentation/media/v4l-drivers/cx88-cardlist.rst @@ -1,96 +1,98 @@ CX88 cards list =============== -.. code-block:: none - - 0 -> UNKNOWN/GENERIC - 1 -> Hauppauge WinTV 34xxx models [0070:3400,0070:3401] - 2 -> GDI Black Gold [14c7:0106,14c7:0107] - 3 -> PixelView [1554:4811] - 4 -> ATI TV Wonder Pro [1002:00f8,1002:00f9] - 5 -> Leadtek Winfast 2000XP Expert [107d:6611,107d:6613] - 6 -> AverTV Studio 303 (M126) [1461:000b] - 7 -> MSI TV-@nywhere Master [1462:8606] - 8 -> Leadtek Winfast DV2000 [107d:6620,107d:6621] - 9 -> Leadtek PVR 2000 [107d:663b,107d:663c,107d:6632,107d:6630,107d:6638,107d:6631,107d:6637,107d:663d] - 10 -> IODATA GV-VCP3/PCI [10fc:d003] - 11 -> Prolink PlayTV PVR - 12 -> ASUS PVR-416 [1043:4823,1461:c111] - 13 -> MSI TV-@nywhere - 14 -> KWorld/VStream XPert DVB-T [17de:08a6] - 15 -> DViCO FusionHDTV DVB-T1 [18ac:db00] - 16 -> KWorld LTV883RF - 17 -> DViCO FusionHDTV 3 Gold-Q [18ac:d810,18ac:d800] - 18 -> Hauppauge Nova-T DVB-T [0070:9002,0070:9001,0070:9000] - 19 -> Conexant DVB-T reference design [14f1:0187] - 20 -> Provideo PV259 [1540:2580] - 21 -> DViCO FusionHDTV DVB-T Plus [18ac:db10,18ac:db11] - 22 -> pcHDTV HD3000 HDTV [7063:3000] - 23 -> digitalnow DNTV Live! DVB-T [17de:a8a6] - 24 -> Hauppauge WinTV 28xxx (Roslyn) models [0070:2801] - 25 -> Digital-Logic MICROSPACE Entertainment Center (MEC) [14f1:0342] - 26 -> IODATA GV/BCTV7E [10fc:d035] - 27 -> PixelView PlayTV Ultra Pro (Stereo) - 28 -> DViCO FusionHDTV 3 Gold-T [18ac:d820] - 29 -> ADS Tech Instant TV DVB-T PCI [1421:0334] - 30 -> TerraTec Cinergy 1400 DVB-T [153b:1166] - 31 -> DViCO FusionHDTV 5 Gold [18ac:d500] - 32 -> AverMedia UltraTV Media Center PCI 550 [1461:8011] - 33 -> Kworld V-Stream Xpert DVD - 34 -> ATI HDTV Wonder [1002:a101] - 35 -> WinFast DTV1000-T [107d:665f] - 36 -> AVerTV 303 (M126) [1461:000a] - 37 -> Hauppauge Nova-S-Plus DVB-S [0070:9201,0070:9202] - 38 -> Hauppauge Nova-SE2 DVB-S [0070:9200] - 39 -> KWorld DVB-S 100 [17de:08b2,1421:0341] - 40 -> Hauppauge WinTV-HVR1100 DVB-T/Hybrid [0070:9400,0070:9402] - 41 -> Hauppauge WinTV-HVR1100 DVB-T/Hybrid (Low Profile) [0070:9800,0070:9802] - 42 -> digitalnow DNTV Live! DVB-T Pro [1822:0025,1822:0019] - 43 -> KWorld/VStream XPert DVB-T with cx22702 [17de:08a1,12ab:2300] - 44 -> DViCO FusionHDTV DVB-T Dual Digital [18ac:db50,18ac:db54] - 45 -> KWorld HardwareMpegTV XPert [17de:0840,1421:0305] - 46 -> DViCO FusionHDTV DVB-T Hybrid [18ac:db40,18ac:db44] - 47 -> pcHDTV HD5500 HDTV [7063:5500] - 48 -> Kworld MCE 200 Deluxe [17de:0841] - 49 -> PixelView PlayTV P7000 [1554:4813] - 50 -> NPG Tech Real TV FM Top 10 [14f1:0842] - 51 -> WinFast DTV2000 H [107d:665e] - 52 -> Geniatech DVB-S [14f1:0084] - 53 -> Hauppauge WinTV-HVR3000 TriMode Analog/DVB-S/DVB-T [0070:1404,0070:1400,0070:1401,0070:1402] - 54 -> Norwood Micro TV Tuner - 55 -> Shenzhen Tungsten Ages Tech TE-DTV-250 / Swann OEM [c180:c980] - 56 -> Hauppauge WinTV-HVR1300 DVB-T/Hybrid MPEG Encoder [0070:9600,0070:9601,0070:9602] - 57 -> ADS Tech Instant Video PCI [1421:0390] - 58 -> Pinnacle PCTV HD 800i [11bd:0051] - 59 -> DViCO FusionHDTV 5 PCI nano [18ac:d530] - 60 -> Pinnacle Hybrid PCTV [12ab:1788] - 61 -> Leadtek TV2000 XP Global [107d:6f18,107d:6618,107d:6619] - 62 -> PowerColor RA330 [14f1:ea3d] - 63 -> Geniatech X8000-MT DVBT [14f1:8852] - 64 -> DViCO FusionHDTV DVB-T PRO [18ac:db30] - 65 -> DViCO FusionHDTV 7 Gold [18ac:d610] - 66 -> Prolink Pixelview MPEG 8000GT [1554:4935] - 67 -> Kworld PlusTV HD PCI 120 (ATSC 120) [17de:08c1] - 68 -> Hauppauge WinTV-HVR4000 DVB-S/S2/T/Hybrid [0070:6900,0070:6904,0070:6902] - 69 -> Hauppauge WinTV-HVR4000(Lite) DVB-S/S2 [0070:6905,0070:6906] - 70 -> TeVii S460 DVB-S/S2 [d460:9022] - 71 -> Omicom SS4 DVB-S/S2 PCI [A044:2011] - 72 -> TBS 8920 DVB-S/S2 [8920:8888] - 73 -> TeVii S420 DVB-S [d420:9022] - 74 -> Prolink Pixelview Global Extreme [1554:4976] - 75 -> PROF 7300 DVB-S/S2 [B033:3033] - 76 -> SATTRADE ST4200 DVB-S/S2 [b200:4200] - 77 -> TBS 8910 DVB-S [8910:8888] - 78 -> Prof 6200 DVB-S [b022:3022] - 79 -> Terratec Cinergy HT PCI MKII [153b:1177] - 80 -> Hauppauge WinTV-IR Only [0070:9290] - 81 -> Leadtek WinFast DTV1800 Hybrid [107d:6654] - 82 -> WinFast DTV2000 H rev. J [107d:6f2b] - 83 -> Prof 7301 DVB-S/S2 [b034:3034] - 84 -> Samsung SMT 7020 DVB-S [18ac:dc00,18ac:dccd] - 85 -> Twinhan VP-1027 DVB-S [1822:0023] - 86 -> TeVii S464 DVB-S/S2 [d464:9022] - 87 -> Leadtek WinFast DTV2000 H PLUS [107d:6f42] - 88 -> Leadtek WinFast DTV1800 H (XC4000) [107d:6f38] - 89 -> Leadtek TV2000 XP Global (SC4100) [107d:6f36] - 90 -> Leadtek TV2000 XP Global (XC4100) [107d:6f43] +=========== =================================================== ====================================================================================== +Card number Card name PCI IDs +=========== =================================================== ====================================================================================== +0 UNKNOWN/GENERIC +1 Hauppauge WinTV 34xxx models 0070:3400, 0070:3401 +2 GDI Black Gold 14c7:0106, 14c7:0107 +3 PixelView 1554:4811 +4 ATI TV Wonder Pro 1002:00f8, 1002:00f9 +5 Leadtek Winfast 2000XP Expert 107d:6611, 107d:6613 +6 AverTV Studio 303 (M126) 1461:000b +7 MSI TV-@nywhere Master 1462:8606 +8 Leadtek Winfast DV2000 107d:6620, 107d:6621 +9 Leadtek PVR 2000 107d:663b, 107d:663c, 107d:6632, 107d:6630, 107d:6638, 107d:6631, 107d:6637, 107d:663d +10 IODATA GV-VCP3/PCI 10fc:d003 +11 Prolink PlayTV PVR +12 ASUS PVR-416 1043:4823, 1461:c111 +13 MSI TV-@nywhere +14 KWorld/VStream XPert DVB-T 17de:08a6 +15 DViCO FusionHDTV DVB-T1 18ac:db00 +16 KWorld LTV883RF +17 DViCO FusionHDTV 3 Gold-Q 18ac:d810, 18ac:d800 +18 Hauppauge Nova-T DVB-T 0070:9002, 0070:9001, 0070:9000 +19 Conexant DVB-T reference design 14f1:0187 +20 Provideo PV259 1540:2580 +21 DViCO FusionHDTV DVB-T Plus 18ac:db10, 18ac:db11 +22 pcHDTV HD3000 HDTV 7063:3000 +23 digitalnow DNTV Live! DVB-T 17de:a8a6 +24 Hauppauge WinTV 28xxx (Roslyn) models 0070:2801 +25 Digital-Logic MICROSPACE Entertainment Center (MEC) 14f1:0342 +26 IODATA GV/BCTV7E 10fc:d035 +27 PixelView PlayTV Ultra Pro (Stereo) +28 DViCO FusionHDTV 3 Gold-T 18ac:d820 +29 ADS Tech Instant TV DVB-T PCI 1421:0334 +30 TerraTec Cinergy 1400 DVB-T 153b:1166 +31 DViCO FusionHDTV 5 Gold 18ac:d500 +32 AverMedia UltraTV Media Center PCI 550 1461:8011 +33 Kworld V-Stream Xpert DVD +34 ATI HDTV Wonder 1002:a101 +35 WinFast DTV1000-T 107d:665f +36 AVerTV 303 (M126) 1461:000a +37 Hauppauge Nova-S-Plus DVB-S 0070:9201, 0070:9202 +38 Hauppauge Nova-SE2 DVB-S 0070:9200 +39 KWorld DVB-S 100 17de:08b2, 1421:0341 +40 Hauppauge WinTV-HVR1100 DVB-T/Hybrid 0070:9400, 0070:9402 +41 Hauppauge WinTV-HVR1100 DVB-T/Hybrid (Low Profile) 0070:9800, 0070:9802 +42 digitalnow DNTV Live! DVB-T Pro 1822:0025, 1822:0019 +43 KWorld/VStream XPert DVB-T with cx22702 17de:08a1, 12ab:2300 +44 DViCO FusionHDTV DVB-T Dual Digital 18ac:db50, 18ac:db54 +45 KWorld HardwareMpegTV XPert 17de:0840, 1421:0305 +46 DViCO FusionHDTV DVB-T Hybrid 18ac:db40, 18ac:db44 +47 pcHDTV HD5500 HDTV 7063:5500 +48 Kworld MCE 200 Deluxe 17de:0841 +49 PixelView PlayTV P7000 1554:4813 +50 NPG Tech Real TV FM Top 10 14f1:0842 +51 WinFast DTV2000 H 107d:665e +52 Geniatech DVB-S 14f1:0084 +53 Hauppauge WinTV-HVR3000 TriMode Analog/DVB-S/DVB-T 0070:1404, 0070:1400, 0070:1401, 0070:1402 +54 Norwood Micro TV Tuner +55 Shenzhen Tungsten Ages Tech TE-DTV-250 / Swann OEM c180:c980 +56 Hauppauge WinTV-HVR1300 DVB-T/Hybrid MPEG Encoder 0070:9600, 0070:9601, 0070:9602 +57 ADS Tech Instant Video PCI 1421:0390 +58 Pinnacle PCTV HD 800i 11bd:0051 +59 DViCO FusionHDTV 5 PCI nano 18ac:d530 +60 Pinnacle Hybrid PCTV 12ab:1788 +61 Leadtek TV2000 XP Global 107d:6f18, 107d:6618, 107d:6619 +62 PowerColor RA330 14f1:ea3d +63 Geniatech X8000-MT DVBT 14f1:8852 +64 DViCO FusionHDTV DVB-T PRO 18ac:db30 +65 DViCO FusionHDTV 7 Gold 18ac:d610 +66 Prolink Pixelview MPEG 8000GT 1554:4935 +67 Kworld PlusTV HD PCI 120 (ATSC 120) 17de:08c1 +68 Hauppauge WinTV-HVR4000 DVB-S/S2/T/Hybrid 0070:6900, 0070:6904, 0070:6902 +69 Hauppauge WinTV-HVR4000(Lite) DVB-S/S2 0070:6905, 0070:6906 +70 TeVii S460 DVB-S/S2 d460:9022 +71 Omicom SS4 DVB-S/S2 PCI A044:2011 +72 TBS 8920 DVB-S/S2 8920:8888 +73 TeVii S420 DVB-S d420:9022 +74 Prolink Pixelview Global Extreme 1554:4976 +75 PROF 7300 DVB-S/S2 B033:3033 +76 SATTRADE ST4200 DVB-S/S2 b200:4200 +77 TBS 8910 DVB-S 8910:8888 +78 Prof 6200 DVB-S b022:3022 +79 Terratec Cinergy HT PCI MKII 153b:1177 +80 Hauppauge WinTV-IR Only 0070:9290 +81 Leadtek WinFast DTV1800 Hybrid 107d:6654 +82 WinFast DTV2000 H rev. J 107d:6f2b +83 Prof 7301 DVB-S/S2 b034:3034 +84 Samsung SMT 7020 DVB-S 18ac:dc00, 18ac:dccd +85 Twinhan VP-1027 DVB-S 1822:0023 +86 TeVii S464 DVB-S/S2 d464:9022 +87 Leadtek WinFast DTV2000 H PLUS 107d:6f42 +88 Leadtek WinFast DTV1800 H (XC4000) 107d:6f38 +89 Leadtek TV2000 XP Global (SC4100) 107d:6f36 +90 Leadtek TV2000 XP Global (XC4100) 107d:6f43 +=========== =================================================== ====================================================================================== diff --git a/Documentation/media/v4l-drivers/em28xx-cardlist.rst b/Documentation/media/v4l-drivers/em28xx-cardlist.rst index e72f2e5c0898..76b1d301754c 100644 --- a/Documentation/media/v4l-drivers/em28xx-cardlist.rst +++ b/Documentation/media/v4l-drivers/em28xx-cardlist.rst @@ -1,105 +1,107 @@ EM28xx cards list ================= -.. code-block:: none - - 0 -> Unknown EM2800 video grabber (em2800) [eb1a:2800] - 1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2710,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2862,eb1a:2863,eb1a:2870,eb1a:2881,eb1a:2883,eb1a:2868,eb1a:2875] - 2 -> Terratec Cinergy 250 USB (em2820/em2840) [0ccd:0036] - 3 -> Pinnacle PCTV USB 2 (em2820/em2840) [2304:0208] - 4 -> Hauppauge WinTV USB 2 (em2820/em2840) [2040:4200,2040:4201] - 5 -> MSI VOX USB 2.0 (em2820/em2840) - 6 -> Terratec Cinergy 200 USB (em2800) - 7 -> Leadtek Winfast USB II (em2800) [0413:6023] - 8 -> Kworld USB2800 (em2800) - 9 -> Pinnacle Dazzle DVC 90/100/101/107 / Kaiser Baas Video to DVD maker (em2820/em2840) [1b80:e302,1b80:e304,2304:0207,2304:021a,093b:a003] - 10 -> Hauppauge WinTV HVR 900 (em2880) [2040:6500] - 11 -> Terratec Hybrid XS (em2880) - 12 -> Kworld PVR TV 2800 RF (em2820/em2840) - 13 -> Terratec Prodigy XS (em2880) - 14 -> SIIG AVTuner-PVR / Pixelview Prolink PlayTV USB 2.0 (em2820/em2840) - 15 -> V-Gear PocketTV (em2800) - 16 -> Hauppauge WinTV HVR 950 (em2883) [2040:6513,2040:6517,2040:651b] - 17 -> Pinnacle PCTV HD Pro Stick (em2880) [2304:0227] - 18 -> Hauppauge WinTV HVR 900 (R2) (em2880) [2040:6502] - 19 -> EM2860/SAA711X Reference Design (em2860) - 20 -> AMD ATI TV Wonder HD 600 (em2880) [0438:b002] - 21 -> eMPIA Technology, Inc. GrabBeeX+ Video Encoder (em2800) [eb1a:2801] - 22 -> EM2710/EM2750/EM2751 webcam grabber (em2750) [eb1a:2750,eb1a:2751] - 23 -> Huaqi DLCW-130 (em2750) - 24 -> D-Link DUB-T210 TV Tuner (em2820/em2840) [2001:f112] - 25 -> Gadmei UTV310 (em2820/em2840) - 26 -> Hercules Smart TV USB 2.0 (em2820/em2840) - 27 -> Pinnacle PCTV USB 2 (Philips FM1216ME) (em2820/em2840) - 28 -> Leadtek Winfast USB II Deluxe (em2820/em2840) - 29 -> EM2860/TVP5150 Reference Design (em2860) - 30 -> Videology 20K14XUSB USB2.0 (em2820/em2840) - 31 -> Usbgear VD204v9 (em2821) - 32 -> Supercomp USB 2.0 TV (em2821) - 33 -> Elgato Video Capture (em2860) [0fd9:0033] - 34 -> Terratec Cinergy A Hybrid XS (em2860) [0ccd:004f] - 35 -> Typhoon DVD Maker (em2860) - 36 -> NetGMBH Cam (em2860) - 37 -> Gadmei UTV330 (em2860) [eb1a:50a6] - 38 -> Yakumo MovieMixer (em2861) - 39 -> KWorld PVRTV 300U (em2861) [eb1a:e300] - 40 -> Plextor ConvertX PX-TV100U (em2861) [093b:a005] - 41 -> Kworld 350 U DVB-T (em2870) [eb1a:e350] - 42 -> Kworld 355 U DVB-T (em2870) [eb1a:e355,eb1a:e357,eb1a:e359] - 43 -> Terratec Cinergy T XS (em2870) - 44 -> Terratec Cinergy T XS (MT2060) (em2870) [0ccd:0043] - 45 -> Pinnacle PCTV DVB-T (em2870) - 46 -> Compro, VideoMate U3 (em2870) [185b:2870] - 47 -> KWorld DVB-T 305U (em2880) [eb1a:e305] - 48 -> KWorld DVB-T 310U (em2880) - 49 -> MSI DigiVox A/D (em2880) [eb1a:e310] - 50 -> MSI DigiVox A/D II (em2880) [eb1a:e320] - 51 -> Terratec Hybrid XS Secam (em2880) [0ccd:004c] - 52 -> DNT DA2 Hybrid (em2881) - 53 -> Pinnacle Hybrid Pro (em2881) - 54 -> Kworld VS-DVB-T 323UR (em2882) [eb1a:e323] - 55 -> Terratec Cinnergy Hybrid T USB XS (em2882) (em2882) [0ccd:005e,0ccd:0042] - 56 -> Pinnacle Hybrid Pro (330e) (em2882) [2304:0226] - 57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316] - 58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041] - 59 -> Pinnacle PCTV HD Mini (em2874) [2304:023f] - 60 -> Hauppauge WinTV HVR 850 (em2883) [2040:651f] - 61 -> Pixelview PlayTV Box 4 USB 2.0 (em2820/em2840) - 62 -> Gadmei TVR200 (em2820/em2840) - 63 -> Kaiomy TVnPC U2 (em2860) [eb1a:e303] - 64 -> Easy Cap Capture DC-60 (em2860) [1b80:e309] - 65 -> IO-DATA GV-MVP/SZ (em2820/em2840) [04bb:0515] - 66 -> Empire dual TV (em2880) - 67 -> Terratec Grabby (em2860) [0ccd:0096,0ccd:10AF] - 68 -> Terratec AV350 (em2860) [0ccd:0084] - 69 -> KWorld ATSC 315U HDTV TV Box (em2882) [eb1a:a313] - 70 -> Evga inDtube (em2882) - 71 -> Silvercrest Webcam 1.3mpix (em2820/em2840) - 72 -> Gadmei UTV330+ (em2861) - 73 -> Reddo DVB-C USB TV Box (em2870) - 74 -> Actionmaster/LinXcel/Digitus VC211A (em2800) - 75 -> Dikom DK300 (em2882) - 76 -> KWorld PlusTV 340U or UB435-Q (ATSC) (em2870) [1b80:a340] - 77 -> EM2874 Leadership ISDBT (em2874) - 78 -> PCTV nanoStick T2 290e (em28174) [2013:024f] - 79 -> Terratec Cinergy H5 (em2884) [eb1a:2885,0ccd:10a2,0ccd:10ad,0ccd:10b6] - 80 -> PCTV DVB-S2 Stick (460e) (em28174) [2013:024c] - 81 -> Hauppauge WinTV HVR 930C (em2884) [2040:1605] - 82 -> Terratec Cinergy HTC Stick (em2884) [0ccd:00b2] - 83 -> Honestech Vidbox NW03 (em2860) [eb1a:5006] - 84 -> MaxMedia UB425-TC (em2874) [1b80:e425] - 85 -> PCTV QuatroStick (510e) (em2884) [2304:0242] - 86 -> PCTV QuatroStick nano (520e) (em2884) [2013:0251] - 87 -> Terratec Cinergy HTC USB XS (em2884) [0ccd:008e,0ccd:00ac] - 88 -> C3 Tech Digital Duo HDTV/SDTV USB (em2884) [1b80:e755] - 89 -> Delock 61959 (em2874) [1b80:e1cc] - 90 -> KWorld USB ATSC TV Stick UB435-Q V2 (em2874) [1b80:e346] - 91 -> SpeedLink Vicious And Devine Laplace webcam (em2765) [1ae7:9003,1ae7:9004] - 92 -> PCTV DVB-S2 Stick (461e) (em28178) [2013:0258] - 93 -> KWorld USB ATSC TV Stick UB435-Q V3 (em2874) [1b80:e34c] - 94 -> PCTV tripleStick (292e) (em28178) [2013:025f,2040:0264] - 95 -> Leadtek VC100 (em2861) [0413:6f07] - 96 -> Terratec Cinergy T2 Stick HD (em28178) [eb1a:8179] - 97 -> Elgato EyeTV Hybrid 2008 INT (em2884) [0fd9:0018] - 98 -> PLEX PX-BCUD (em28178) [3275:0085] - 99 -> Hauppauge WinTV-dualHD DVB (em28174) [2040:0265] +=========== ==================================================================== ================ ================================================================================================================================== +Card number Card name Empia Chip USB IDs +=========== ==================================================================== ================ ================================================================================================================================== +0 Unknown EM2800 video grabber em2800 eb1a:2800 +1 Unknown EM2750/28xx video grabber em2820 or em2840 eb1a:2710, eb1a:2820, eb1a:2821, eb1a:2860, eb1a:2861, eb1a:2862, eb1a:2863, eb1a:2870, eb1a:2881, eb1a:2883, eb1a:2868, eb1a:2875 +2 Terratec Cinergy 250 USB em2820 or em2840 0ccd:0036 +3 Pinnacle PCTV USB 2 em2820 or em2840 2304:0208 +4 Hauppauge WinTV USB 2 em2820 or em2840 2040:4200, 2040:4201 +5 MSI VOX USB 2.0 em2820 or em2840 +6 Terratec Cinergy 200 USB em2800 +7 Leadtek Winfast USB II em2800 0413:6023 +8 Kworld USB2800 em2800 +9 Pinnacle Dazzle DVC 90/100/101/107 / Kaiser Baas Video to DVD maker em2820 or em2840 1b80:e302, 1b80:e304, 2304:0207, 2304:021a, 093b:a003 +10 Hauppauge WinTV HVR 900 em2880 2040:6500 +11 Terratec Hybrid XS em2880 +12 Kworld PVR TV 2800 RF em2820 or em2840 +13 Terratec Prodigy XS em2880 +14 SIIG AVTuner-PVR / Pixelview Prolink PlayTV USB 2.0 em2820 or em2840 +15 V-Gear PocketTV em2800 +16 Hauppauge WinTV HVR 950 em2883 2040:6513, 2040:6517, 2040:651b +17 Pinnacle PCTV HD Pro Stick em2880 2304:0227 +18 Hauppauge WinTV HVR 900 (R2) em2880 2040:6502 +19 EM2860/SAA711X Reference Design em2860 +20 AMD ATI TV Wonder HD 600 em2880 0438:b002 +21 eMPIA Technology, Inc. GrabBeeX+ Video Encoder em2800 eb1a:2801 +22 EM2710/EM2750/EM2751 webcam grabber em2750 eb1a:2750, eb1a:2751 +23 Huaqi DLCW-130 em2750 +24 D-Link DUB-T210 TV Tuner em2820 or em2840 2001:f112 +25 Gadmei UTV310 em2820 or em2840 +26 Hercules Smart TV USB 2.0 em2820 or em2840 +27 Pinnacle PCTV USB 2 (Philips FM1216ME) em2820 or em2840 +28 Leadtek Winfast USB II Deluxe em2820 or em2840 +29 EM2860/TVP5150 Reference Design em2860 +30 Videology 20K14XUSB USB2.0 em2820 or em2840 +31 Usbgear VD204v9 em2821 +32 Supercomp USB 2.0 TV em2821 +33 Elgato Video Capture em2860 0fd9:0033 +34 Terratec Cinergy A Hybrid XS em2860 0ccd:004f +35 Typhoon DVD Maker em2860 +36 NetGMBH Cam em2860 +37 Gadmei UTV330 em2860 eb1a:50a6 +38 Yakumo MovieMixer em2861 +39 KWorld PVRTV 300U em2861 eb1a:e300 +40 Plextor ConvertX PX-TV100U em2861 093b:a005 +41 Kworld 350 U DVB-T em2870 eb1a:e350 +42 Kworld 355 U DVB-T em2870 eb1a:e355, eb1a:e357, eb1a:e359 +43 Terratec Cinergy T XS em2870 +44 Terratec Cinergy T XS (MT2060) em2870 0ccd:0043 +45 Pinnacle PCTV DVB-T em2870 +46 Compro, VideoMate U3 em2870 185b:2870 +47 KWorld DVB-T 305U em2880 eb1a:e305 +48 KWorld DVB-T 310U em2880 +49 MSI DigiVox A/D em2880 eb1a:e310 +50 MSI DigiVox A/D II em2880 eb1a:e320 +51 Terratec Hybrid XS Secam em2880 0ccd:004c +52 DNT DA2 Hybrid em2881 +53 Pinnacle Hybrid Pro em2881 +54 Kworld VS-DVB-T 323UR em2882 eb1a:e323 +55 Terratec Cinnergy Hybrid T USB XS (em2882) em2882 0ccd:005e, 0ccd:0042 +56 Pinnacle Hybrid Pro (330e) em2882 2304:0226 +57 Kworld PlusTV HD Hybrid 330 em2883 eb1a:a316 +58 Compro VideoMate ForYou/Stereo em2820 or em2840 185b:2041 +59 Pinnacle PCTV HD Mini em2874 2304:023f +60 Hauppauge WinTV HVR 850 em2883 2040:651f +61 Pixelview PlayTV Box 4 USB 2.0 em2820 or em2840 +62 Gadmei TVR200 em2820 or em2840 +63 Kaiomy TVnPC U2 em2860 eb1a:e303 +64 Easy Cap Capture DC-60 em2860 1b80:e309 +65 IO-DATA GV-MVP/SZ em2820 or em2840 04bb:0515 +66 Empire dual TV em2880 +67 Terratec Grabby em2860 0ccd:0096, 0ccd:10AF +68 Terratec AV350 em2860 0ccd:0084 +69 KWorld ATSC 315U HDTV TV Box em2882 eb1a:a313 +70 Evga inDtube em2882 +71 Silvercrest Webcam 1.3mpix em2820 or em2840 +72 Gadmei UTV330+ em2861 +73 Reddo DVB-C USB TV Box em2870 +74 Actionmaster/LinXcel/Digitus VC211A em2800 +75 Dikom DK300 em2882 +76 KWorld PlusTV 340U or UB435-Q (ATSC) em2870 1b80:a340 +77 EM2874 Leadership ISDBT em2874 +78 PCTV nanoStick T2 290e em28174 2013:024f +79 Terratec Cinergy H5 em2884 eb1a:2885, 0ccd:10a2, 0ccd:10ad, 0ccd:10b6 +80 PCTV DVB-S2 Stick (460e) em28174 2013:024c +81 Hauppauge WinTV HVR 930C em2884 2040:1605 +82 Terratec Cinergy HTC Stick em2884 0ccd:00b2 +83 Honestech Vidbox NW03 em2860 eb1a:5006 +84 MaxMedia UB425-TC em2874 1b80:e425 +85 PCTV QuatroStick (510e) em2884 2304:0242 +86 PCTV QuatroStick nano (520e) em2884 2013:0251 +87 Terratec Cinergy HTC USB XS em2884 0ccd:008e, 0ccd:00ac +88 C3 Tech Digital Duo HDTV/SDTV USB em2884 1b80:e755 +89 Delock 61959 em2874 1b80:e1cc +90 KWorld USB ATSC TV Stick UB435-Q V2 em2874 1b80:e346 +91 SpeedLink Vicious And Devine Laplace webcam em2765 1ae7:9003, 1ae7:9004 +92 PCTV DVB-S2 Stick (461e) em28178 2013:0258 +93 KWorld USB ATSC TV Stick UB435-Q V3 em2874 1b80:e34c +94 PCTV tripleStick (292e) em28178 2013:025f, 2040:0264 +95 Leadtek VC100 em2861 0413:6f07 +96 Terratec Cinergy T2 Stick HD em28178 eb1a:8179 +97 Elgato EyeTV Hybrid 2008 INT em2884 0fd9:0018 +98 PLEX PX-BCUD em28178 3275:0085 +99 Hauppauge WinTV-dualHD DVB em28174 2040:0265 +=========== ==================================================================== ================ ================================================================================================================================== diff --git a/Documentation/media/v4l-drivers/gspca-cardlist.rst b/Documentation/media/v4l-drivers/gspca-cardlist.rst index 33a8ac7d73ab..e18d87e80d78 100644 --- a/Documentation/media/v4l-drivers/gspca-cardlist.rst +++ b/Documentation/media/v4l-drivers/gspca-cardlist.rst @@ -6,407 +6,444 @@ The modules for the gspca webcam drivers are: - gspca_main: main driver - gspca\_\ *driver*: subdriver module with *driver* as follows -========= ========= ==================================================================== +========= ========= =================================================================== *driver* vend:prod Device -========= ========= ==================================================================== -spca501 0000:0000 MystFromOri Unknown Camera -spca508 0130:0130 Clone Digital Webcam 11043 -zc3xx 03f0:1b07 HP Premium Starter Cam -m5602 0402:5602 ALi Video Camera Controller -spca501 040a:0002 Kodak DVC-325 -spca500 040a:0300 Kodak EZ200 -zc3xx 041e:041e Creative WebCam Live! -ov519 041e:4003 Video Blaster WebCam Go Plus -spca500 041e:400a Creative PC-CAM 300 -sunplus 041e:400b Creative PC-CAM 600 -sunplus 041e:4012 PC-Cam350 -sunplus 041e:4013 Creative Pccam750 -zc3xx 041e:4017 Creative Webcam Mobile PD1090 -spca508 041e:4018 Creative Webcam Vista (PD1100) -spca561 041e:401a Creative Webcam Vista (PD1100) -zc3xx 041e:401c Creative NX -spca505 041e:401d Creative Webcam NX ULTRA -zc3xx 041e:401e Creative Nx Pro -zc3xx 041e:401f Creative Webcam Notebook PD1171 -pac207 041e:4028 Creative Webcam Vista Plus -zc3xx 041e:4029 Creative WebCam Vista Pro -zc3xx 041e:4034 Creative Instant P0620 -zc3xx 041e:4035 Creative Instant P0620D -zc3xx 041e:4036 Creative Live ! -sq930x 041e:4038 Creative Joy-IT -zc3xx 041e:403a Creative Nx Pro 2 -spca561 041e:403b Creative Webcam Vista (VF0010) -sq930x 041e:403c Creative Live! Ultra -sq930x 041e:403d Creative Live! Ultra for Notebooks -sq930x 041e:4041 Creative Live! Motion -zc3xx 041e:4051 Creative Live!Cam Notebook Pro (VF0250) -ov519 041e:4052 Creative Live! VISTA IM -zc3xx 041e:4053 Creative Live!Cam Video IM -vc032x 041e:405b Creative Live! Cam Notebook Ultra (VC0130) -ov519 041e:405f Creative Live! VISTA VF0330 -ov519 041e:4060 Creative Live! VISTA VF0350 -ov519 041e:4061 Creative Live! VISTA VF0400 -ov519 041e:4064 Creative Live! VISTA VF0420 -ov519 041e:4067 Creative Live! Cam Video IM (VF0350) -ov519 041e:4068 Creative Live! VISTA VF0470 -spca561 0458:7004 Genius VideoCAM Express V2 -sn9c2028 0458:7005 Genius Smart 300, version 2 -sunplus 0458:7006 Genius Dsc 1.3 Smart -zc3xx 0458:7007 Genius VideoCam V2 -zc3xx 0458:700c Genius VideoCam V3 -zc3xx 0458:700f Genius VideoCam Web V2 -sonixj 0458:7025 Genius Eye 311Q -sn9c20x 0458:7029 Genius Look 320s -sonixj 0458:702e Genius Slim 310 NB -sn9c20x 0458:7045 Genius Look 1320 V2 -sn9c20x 0458:704a Genius Slim 1320 -sn9c20x 0458:704c Genius i-Look 1321 -sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650) -sonixj 045e:00f5 MicroSoft VX3000 -sonixj 045e:00f7 MicroSoft VX1000 -ov519 045e:028c Micro$oft xbox cam -spca508 0461:0815 Micro Innovation IC200 -sunplus 0461:0821 Fujifilm MV-1 -zc3xx 0461:0a00 MicroInnovation WebCam320 -stv06xx 046d:0840 QuickCam Express -stv06xx 046d:0850 LEGO cam / QuickCam Web -stv06xx 046d:0870 Dexxa WebCam USB -spca500 046d:0890 Logitech QuickCam traveler -vc032x 046d:0892 Logitech Orbicam -vc032x 046d:0896 Logitech Orbicam -vc032x 046d:0897 Logitech QuickCam for Dell notebooks -zc3xx 046d:089d Logitech QuickCam E2500 -zc3xx 046d:08a0 Logitech QC IM -zc3xx 046d:08a1 Logitech QC IM 0x08A1 +sound -zc3xx 046d:08a2 Labtec Webcam Pro -zc3xx 046d:08a3 Logitech QC Chat -zc3xx 046d:08a6 Logitech QCim -zc3xx 046d:08a7 Logitech QuickCam Image -zc3xx 046d:08a9 Logitech Notebook Deluxe -zc3xx 046d:08aa Labtec Webcam Notebook -zc3xx 046d:08ac Logitech QuickCam Cool -zc3xx 046d:08ad Logitech QCCommunicate STX -zc3xx 046d:08ae Logitech QuickCam for Notebooks -zc3xx 046d:08af Logitech QuickCam Cool -zc3xx 046d:08b9 Logitech QuickCam Express -zc3xx 046d:08d7 Logitech QCam STX -zc3xx 046d:08d9 Logitech QuickCam IM/Connect -zc3xx 046d:08d8 Logitech Notebook Deluxe -zc3xx 046d:08da Logitech QuickCam Messenger -zc3xx 046d:08dd Logitech QuickCam for Notebooks -spca500 046d:0900 Logitech Inc. ClickSmart 310 -spca500 046d:0901 Logitech Inc. ClickSmart 510 -sunplus 046d:0905 Logitech ClickSmart 820 -tv8532 046d:0920 Logitech QuickCam Express -tv8532 046d:0921 Labtec Webcam -spca561 046d:0928 Logitech QC Express Etch2 -spca561 046d:0929 Labtec Webcam Elch2 -spca561 046d:092a Logitech QC for Notebook -spca561 046d:092b Labtec Webcam Plus -spca561 046d:092c Logitech QC chat Elch2 -spca561 046d:092d Logitech QC Elch2 -spca561 046d:092e Logitech QC Elch2 -spca561 046d:092f Logitech QuickCam Express Plus -sunplus 046d:0960 Logitech ClickSmart 420 -nw80x 046d:d001 Logitech QuickCam Pro (dark focus ring) -sunplus 0471:0322 Philips DMVC1300K -zc3xx 0471:0325 Philips SPC 200 NC -zc3xx 0471:0326 Philips SPC 300 NC -sonixj 0471:0327 Philips SPC 600 NC -sonixj 0471:0328 Philips SPC 700 NC -zc3xx 0471:032d Philips SPC 210 NC -zc3xx 0471:032e Philips SPC 315 NC -sonixj 0471:0330 Philips SPC 710 NC -spca501 0497:c001 Smile International -sunplus 04a5:3003 Benq DC 1300 -sunplus 04a5:3008 Benq DC 1500 -sunplus 04a5:300a Benq DC 3410 -spca500 04a5:300c Benq DC 1016 -benq 04a5:3035 Benq DC E300 -finepix 04cb:0104 Fujifilm FinePix 4800 -finepix 04cb:0109 Fujifilm FinePix A202 -finepix 04cb:010b Fujifilm FinePix A203 -finepix 04cb:010f Fujifilm FinePix A204 -finepix 04cb:0111 Fujifilm FinePix A205 -finepix 04cb:0113 Fujifilm FinePix A210 -finepix 04cb:0115 Fujifilm FinePix A303 -finepix 04cb:0117 Fujifilm FinePix A310 -finepix 04cb:0119 Fujifilm FinePix F401 -finepix 04cb:011b Fujifilm FinePix F402 -finepix 04cb:011d Fujifilm FinePix F410 -finepix 04cb:0121 Fujifilm FinePix F601 -finepix 04cb:0123 Fujifilm FinePix F700 -finepix 04cb:0125 Fujifilm FinePix M603 -finepix 04cb:0127 Fujifilm FinePix S300 -finepix 04cb:0129 Fujifilm FinePix S304 -finepix 04cb:012b Fujifilm FinePix S500 -finepix 04cb:012d Fujifilm FinePix S602 -finepix 04cb:012f Fujifilm FinePix S700 -finepix 04cb:0131 Fujifilm FinePix unknown model -finepix 04cb:013b Fujifilm FinePix unknown model -finepix 04cb:013d Fujifilm FinePix unknown model -finepix 04cb:013f Fujifilm FinePix F420 -sunplus 04f1:1001 JVC GC A50 -spca561 04fc:0561 Flexcam 100 -spca1528 04fc:1528 Sunplus MD80 clone -sunplus 04fc:500c Sunplus CA500C -sunplus 04fc:504a Aiptek Mini PenCam 1.3 -sunplus 04fc:504b Maxell MaxPocket LE 1.3 -sunplus 04fc:5330 Digitrex 2110 -sunplus 04fc:5360 Sunplus Generic -spca500 04fc:7333 PalmPixDC85 -sunplus 04fc:ffff Pure DigitalDakota -nw80x 0502:d001 DVC V6 -spca501 0506:00df 3Com HomeConnect Lite -sunplus 052b:1507 Megapixel 5 Pretec DC-1007 -sunplus 052b:1513 Megapix V4 -sunplus 052b:1803 MegaImage VI -nw80x 052b:d001 EZCam Pro p35u -tv8532 0545:808b Veo Stingray -tv8532 0545:8333 Veo Stingray -sunplus 0546:3155 Polaroid PDC3070 -sunplus 0546:3191 Polaroid Ion 80 -sunplus 0546:3273 Polaroid PDC2030 -ov519 054c:0154 Sonny toy4 -ov519 054c:0155 Sonny toy5 -cpia1 0553:0002 CPIA CPiA (version1) based cameras -zc3xx 055f:c005 Mustek Wcam300A -spca500 055f:c200 Mustek Gsmart 300 -sunplus 055f:c211 Kowa Bs888e Microcamera -spca500 055f:c220 Gsmart Mini -sunplus 055f:c230 Mustek Digicam 330K -sunplus 055f:c232 Mustek MDC3500 -sunplus 055f:c360 Mustek DV4000 Mpeg4 -sunplus 055f:c420 Mustek gSmart Mini 2 -sunplus 055f:c430 Mustek Gsmart LCD 2 -sunplus 055f:c440 Mustek DV 3000 -sunplus 055f:c520 Mustek gSmart Mini 3 -sunplus 055f:c530 Mustek Gsmart LCD 3 -sunplus 055f:c540 Gsmart D30 -sunplus 055f:c630 Mustek MDC4000 -sunplus 055f:c650 Mustek MDC5500Z -nw80x 055f:d001 Mustek Wcam 300 mini -zc3xx 055f:d003 Mustek WCam300A -zc3xx 055f:d004 Mustek WCam300 AN -conex 0572:0041 Creative Notebook cx11646 -ov519 05a9:0511 Video Blaster WebCam 3/WebCam Plus, D-Link USB Digital Video Camera -ov519 05a9:0518 Creative WebCam -ov519 05a9:0519 OV519 Microphone -ov519 05a9:0530 OmniVision -ov534_9 05a9:1550 OmniVision VEHO Filmscanner -ov519 05a9:2800 OmniVision SuperCAM -ov519 05a9:4519 Webcam Classic -ov534_9 05a9:8065 OmniVision test kit ov538+ov9712 -ov519 05a9:8519 OmniVision -ov519 05a9:a511 D-Link USB Digital Video Camera -ov519 05a9:a518 D-Link DSB-C310 Webcam -sunplus 05da:1018 Digital Dream Enigma 1.3 -stk014 05e1:0893 Syntek DV4000 -gl860 05e3:0503 Genesys Logic PC Camera -gl860 05e3:f191 Genesys Logic PC Camera -spca561 060b:a001 Maxell Compact Pc PM3 -zc3xx 0698:2003 CTX M730V built in -topro 06a2:0003 TP6800 PC Camera, CmoX CX0342 webcam -topro 06a2:6810 Creative Qmax -nw80x 06a5:0000 Typhoon Webcam 100 USB -nw80x 06a5:d001 Divio based webcams -nw80x 06a5:d800 Divio Chicony TwinkleCam, Trust SpaceCam -spca500 06bd:0404 Agfa CL20 -spca500 06be:0800 Optimedia -nw80x 06be:d001 EZCam Pro p35u -sunplus 06d6:0031 Trust 610 LCD PowerC@m Zoom -spca506 06e1:a190 ADS Instant VCD -ov534 06f8:3002 Hercules Blog Webcam -ov534_9 06f8:3003 Hercules Dualpix HD Weblog -sonixj 06f8:3004 Hercules Classic Silver -sonixj 06f8:3008 Hercules Deluxe Optical Glass -pac7302 06f8:3009 Hercules Classic Link -pac7302 06f8:301b Hercules Link -nw80x 0728:d001 AVerMedia Camguard -spca508 0733:0110 ViewQuest VQ110 -spca501 0733:0401 Intel Create and Share -spca501 0733:0402 ViewQuest M318B -spca505 0733:0430 Intel PC Camera Pro -sunplus 0733:1311 Digital Dream Epsilon 1.3 -sunplus 0733:1314 Mercury 2.1MEG Deluxe Classic Cam -sunplus 0733:2211 Jenoptik jdc 21 LCD -sunplus 0733:2221 Mercury Digital Pro 3.1p -sunplus 0733:3261 Concord 3045 spca536a -sunplus 0733:3281 Cyberpix S550V -spca506 0734:043b 3DeMon USB Capture aka -cpia1 0813:0001 QX3 camera -ov519 0813:0002 Dual Mode USB Camera Plus -spca500 084d:0003 D-Link DSC-350 -spca500 08ca:0103 Aiptek PocketDV -sunplus 08ca:0104 Aiptek PocketDVII 1.3 -sunplus 08ca:0106 Aiptek Pocket DV3100+ -mr97310a 08ca:0110 Trust Spyc@m 100 -mr97310a 08ca:0111 Aiptek PenCam VGA+ -sunplus 08ca:2008 Aiptek Mini PenCam 2 M -sunplus 08ca:2010 Aiptek PocketCam 3M -sunplus 08ca:2016 Aiptek PocketCam 2 Mega -sunplus 08ca:2018 Aiptek Pencam SD 2M -sunplus 08ca:2020 Aiptek Slim 3000F -sunplus 08ca:2022 Aiptek Slim 3200 -sunplus 08ca:2024 Aiptek DV3500 Mpeg4 -sunplus 08ca:2028 Aiptek PocketCam4M -sunplus 08ca:2040 Aiptek PocketDV4100M -sunplus 08ca:2042 Aiptek PocketDV5100 -sunplus 08ca:2050 Medion MD 41437 -sunplus 08ca:2060 Aiptek PocketDV5300 -tv8532 0923:010f ICM532 cams -mars 093a:050f Mars-Semi Pc-Camera -mr97310a 093a:010e All known CIF cams with this ID -mr97310a 093a:010f All known VGA cams with this ID -pac207 093a:2460 Qtec Webcam 100 -pac207 093a:2461 HP Webcam -pac207 093a:2463 Philips SPC 220 NC -pac207 093a:2464 Labtec Webcam 1200 -pac207 093a:2468 Webcam WB-1400T -pac207 093a:2470 Genius GF112 -pac207 093a:2471 Genius VideoCam ge111 -pac207 093a:2472 Genius VideoCam ge110 -pac207 093a:2474 Genius iLook 111 -pac207 093a:2476 Genius e-Messenger 112 -pac7311 093a:2600 PAC7311 Typhoon -pac7311 093a:2601 Philips SPC 610 NC -pac7311 093a:2603 Philips SPC 500 NC -pac7311 093a:2608 Trust WB-3300p -pac7311 093a:260e Gigaware VGA PC Camera, Trust WB-3350p, SIGMA cam 2350 -pac7311 093a:260f SnakeCam -pac7302 093a:2620 Apollo AC-905 -pac7302 093a:2621 PAC731x -pac7302 093a:2622 Genius Eye 312 -pac7302 093a:2624 PAC7302 -pac7302 093a:2625 Genius iSlim 310 -pac7302 093a:2626 Labtec 2200 -pac7302 093a:2627 Genius FaceCam 300 -pac7302 093a:2628 Genius iLook 300 -pac7302 093a:2629 Genious iSlim 300 -pac7302 093a:262a Webcam 300k -pac7302 093a:262c Philips SPC 230 NC -jl2005bcd 0979:0227 Various brands, 19 known cameras supported -jeilinj 0979:0280 Sakar 57379 -jeilinj 0979:0280 Sportscam DV15 -zc3xx 0ac8:0302 Z-star Vimicro zc0302 -vc032x 0ac8:0321 Vimicro generic vc0321 -vc032x 0ac8:0323 Vimicro Vc0323 -vc032x 0ac8:0328 A4Tech PK-130MG -zc3xx 0ac8:301b Z-Star zc301b -zc3xx 0ac8:303b Vimicro 0x303b -zc3xx 0ac8:305b Z-star Vimicro zc0305b -zc3xx 0ac8:307b PC Camera (ZS0211) -vc032x 0ac8:c001 Sony embedded vimicro -vc032x 0ac8:c002 Sony embedded vimicro -vc032x 0ac8:c301 Samsung Q1 Ultra Premium -spca508 0af9:0010 Hama USB Sightcam 100 -spca508 0af9:0011 Hama USB Sightcam 100 -ov519 0b62:0059 iBOT2 Webcam -sonixb 0c45:6001 Genius VideoCAM NB -sonixb 0c45:6005 Microdia Sweex Mini Webcam -sonixb 0c45:6007 Sonix sn9c101 + Tas5110D -sonixb 0c45:6009 spcaCam@120 -sonixb 0c45:600d spcaCam@120 -sonixb 0c45:6011 Microdia PC Camera (SN9C102) -sonixb 0c45:6019 Generic Sonix OV7630 -sonixb 0c45:6024 Generic Sonix Tas5130c -sonixb 0c45:6025 Xcam Shanga -sonixb 0c45:6028 Sonix Btc Pc380 -sonixb 0c45:6029 spcaCam@150 -sonixb 0c45:602c Generic Sonix OV7630 -sonixb 0c45:602d LIC-200 LG -sonixb 0c45:602e Genius VideoCam Messenger -sonixj 0c45:6040 Speed NVC 350K -sonixj 0c45:607c Sonix sn9c102p Hv7131R -sonixj 0c45:60c0 Sangha Sn535 -sonixj 0c45:60ce USB-PC-Camera-168 (TALK-5067) -sonixj 0c45:60ec SN9C105+MO4000 -sonixj 0c45:60fb Surfer NoName -sonixj 0c45:60fc LG-LIC300 -sonixj 0c45:60fe Microdia Audio -sonixj 0c45:6100 PC Camera (SN9C128) -sonixj 0c45:6102 PC Camera (SN9C128) -sonixj 0c45:610a PC Camera (SN9C128) -sonixj 0c45:610b PC Camera (SN9C128) -sonixj 0c45:610c PC Camera (SN9C128) -sonixj 0c45:610e PC Camera (SN9C128) -sonixj 0c45:6128 Microdia/Sonix SNP325 -sonixj 0c45:612a Avant Camera -sonixj 0c45:612b Speed-Link REFLECT2 -sonixj 0c45:612c Typhoon Rasy Cam 1.3MPix -sonixj 0c45:6130 Sonix Pccam -sonixj 0c45:6138 Sn9c120 Mo4000 -sonixj 0c45:613a Microdia Sonix PC Camera -sonixj 0c45:613b Surfer SN-206 -sonixj 0c45:613c Sonix Pccam168 -sonixj 0c45:6142 Hama PC-Webcam AC-150 -sonixj 0c45:6143 Sonix Pccam168 -sonixj 0c45:6148 Digitus DA-70811/ZSMC USB PC Camera ZS211/Microdia -sonixj 0c45:614a Frontech E-Ccam (JIL-2225) -sn9c20x 0c45:6240 PC Camera (SN9C201 + MT9M001) -sn9c20x 0c45:6242 PC Camera (SN9C201 + MT9M111) -sn9c20x 0c45:6248 PC Camera (SN9C201 + OV9655) -sn9c20x 0c45:624c PC Camera (SN9C201 + MT9M112) -sn9c20x 0c45:624e PC Camera (SN9C201 + SOI968) -sn9c20x 0c45:624f PC Camera (SN9C201 + OV9650) -sn9c20x 0c45:6251 PC Camera (SN9C201 + OV9650) -sn9c20x 0c45:6253 PC Camera (SN9C201 + OV9650) -sn9c20x 0c45:6260 PC Camera (SN9C201 + OV7670) -sn9c20x 0c45:6270 PC Camera (SN9C201 + MT9V011/MT9V111/MT9V112) -sn9c20x 0c45:627b PC Camera (SN9C201 + OV7660) -sn9c20x 0c45:627c PC Camera (SN9C201 + HV7131R) -sn9c20x 0c45:627f PC Camera (SN9C201 + OV9650) -sn9c20x 0c45:6280 PC Camera (SN9C202 + MT9M001) -sn9c20x 0c45:6282 PC Camera (SN9C202 + MT9M111) -sn9c20x 0c45:6288 PC Camera (SN9C202 + OV9655) -sn9c20x 0c45:628c PC Camera (SN9C201 + MT9M112) -sn9c20x 0c45:628e PC Camera (SN9C202 + SOI968) -sn9c20x 0c45:628f PC Camera (SN9C202 + OV9650) -sn9c20x 0c45:62a0 PC Camera (SN9C202 + OV7670) -sn9c20x 0c45:62b0 PC Camera (SN9C202 + MT9V011/MT9V111/MT9V112) -sn9c20x 0c45:62b3 PC Camera (SN9C202 + OV9655) -sn9c20x 0c45:62bb PC Camera (SN9C202 + OV7660) -sn9c20x 0c45:62bc PC Camera (SN9C202 + HV7131R) -sn9c2028 0c45:8001 Wild Planet Digital Spy Camera -sn9c2028 0c45:8003 Sakar #11199, #6637x, #67480 keychain cams -sn9c2028 0c45:8008 Mini-Shotz ms-350 -sn9c2028 0c45:800a Vivitar Vivicam 3350B -sunplus 0d64:0303 Sunplus FashionCam DXG -ov519 0e96:c001 TRUST 380 USB2 SPACEC@M -etoms 102c:6151 Qcam Sangha CIF -etoms 102c:6251 Qcam xxxxxx VGA -ov519 1046:9967 W9967CF/W9968CF WebCam IC, Video Blaster WebCam Go -zc3xx 10fd:0128 Typhoon Webshot II USB 300k 0x0128 -spca561 10fd:7e50 FlyCam Usb 100 -zc3xx 10fd:8050 Typhoon Webshot II USB 300k -ov534 1415:2000 Sony HD Eye for PS3 (SLEH 00201) -pac207 145f:013a Trust WB-1300N -sn9c20x 145f:013d Trust WB-3600R -vc032x 15b8:6001 HP 2.0 Megapixel -vc032x 15b8:6002 HP 2.0 Megapixel rz406aa -spca501 1776:501c Arowana 300K CMOS Camera -t613 17a1:0128 TASCORP JPEG Webcam, NGS Cyclops -vc032x 17ef:4802 Lenovo Vc0323+MI1310_SOC -pac207 2001:f115 D-Link DSB-C120 -sq905c 2770:9050 Disney pix micro (CIF) -sq905c 2770:9051 Lego Bionicle -sq905c 2770:9052 Disney pix micro 2 (VGA) -sq905c 2770:905c All 11 known cameras with this ID -sq905 2770:9120 All 24 known cameras with this ID -sq905c 2770:913d All 4 known cameras with this ID -sq930x 2770:930b Sweex Motion Tracking / I-Tec iCam Tracer -sq930x 2770:930c Trust WB-3500T / NSG Robbie 2.0 -spca500 2899:012c Toptro Industrial -ov519 8020:ef04 ov519 -spca508 8086:0110 Intel Easy PC Camera -spca500 8086:0630 Intel Pocket PC Camera -spca506 99fa:8988 Grandtec V.cap -sn9c20x a168:0610 Dino-Lite Digital Microscope (SN9C201 + HV7131R) -sn9c20x a168:0611 Dino-Lite Digital Microscope (SN9C201 + HV7131R) -sn9c20x a168:0613 Dino-Lite Digital Microscope (SN9C201 + HV7131R) -sn9c20x a168:0618 Dino-Lite Digital Microscope (SN9C201 + HV7131R) -sn9c20x a168:0614 Dino-Lite Digital Microscope (SN9C201 + MT9M111) -sn9c20x a168:0615 Dino-Lite Digital Microscope (SN9C201 + MT9M111) -sn9c20x a168:0617 Dino-Lite Digital Microscope (SN9C201 + MT9M111) -spca561 abcd:cdee Petcam -========= ========= ==================================================================== +========= ========= =================================================================== +spca501 0000:0000 MystFromOri Unknown Camera +spca508 0130:0130 Clone Digital Webcam 11043 +se401 03e8:0004 Endpoints/AoxSE401 +zc3xx 03f0:1b07 HP Premium Starter Cam +m5602 0402:5602 ALi Video Camera Controller +spca501 040a:0002 Kodak DVC-325 +spca500 040a:0300 Kodak EZ200 +zc3xx 041e:041e Creative WebCam Live! +ov519 041e:4003 Video Blaster WebCam Go Plus +stv0680 041e:4007 Go Mini +spca500 041e:400a Creative PC-CAM 300 +sunplus 041e:400b Creative PC-CAM 600 +sunplus 041e:4012 PC-Cam350 +sunplus 041e:4013 Creative Pccam750 +zc3xx 041e:4017 Creative Webcam Mobile PD1090 +spca508 041e:4018 Creative Webcam Vista (PD1100) +spca561 041e:401a Creative Webcam Vista (PD1100) +zc3xx 041e:401c Creative NX +spca505 041e:401d Creative Webcam NX ULTRA +zc3xx 041e:401e Creative Nx Pro +zc3xx 041e:401f Creative Webcam Notebook PD1171 +zc3xx 041e:4022 Webcam NX Pro +pac207 041e:4028 Creative Webcam Vista Plus +zc3xx 041e:4029 Creative WebCam Vista Pro +zc3xx 041e:4034 Creative Instant P0620 +zc3xx 041e:4035 Creative Instant P0620D +zc3xx 041e:4036 Creative Live ! +sq930x 041e:4038 Creative Joy-IT +zc3xx 041e:403a Creative Nx Pro 2 +spca561 041e:403b Creative Webcam Vista (VF0010) +sq930x 041e:403c Creative Live! Ultra +sq930x 041e:403d Creative Live! Ultra for Notebooks +sq930x 041e:4041 Creative Live! Motion +zc3xx 041e:4051 Creative Live!Cam Notebook Pro (VF0250) +ov519 041e:4052 Creative Live! VISTA IM +zc3xx 041e:4053 Creative Live!Cam Video IM +vc032x 041e:405b Creative Live! Cam Notebook Ultra (VC0130) +ov519 041e:405f Creative Live! VISTA VF0330 +ov519 041e:4060 Creative Live! VISTA VF0350 +ov519 041e:4061 Creative Live! VISTA VF0400 +ov519 041e:4064 Creative Live! VISTA VF0420 +ov519 041e:4067 Creative Live! Cam Video IM (VF0350) +ov519 041e:4068 Creative Live! VISTA VF0470 +sn9c2028 0458:7003 GeniusVideocam Live v2 +spca561 0458:7004 Genius VideoCAM Express V2 +sn9c2028 0458:7005 Genius Smart 300, version 2 +sunplus 0458:7006 Genius Dsc 1.3 Smart +zc3xx 0458:7007 Genius VideoCam V2 +zc3xx 0458:700c Genius VideoCam V3 +zc3xx 0458:700f Genius VideoCam Web V2 +sonixj 0458:7025 Genius Eye 311Q +sn9c20x 0458:7029 Genius Look 320s +sonixj 0458:702e Genius Slim 310 NB +sn9c20x 0458:7045 Genius Look 1320 V2 +sn9c20x 0458:704a Genius Slim 1320 +sn9c20x 0458:704c Genius i-Look 1321 +sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650) +sonixj 045e:00f5 MicroSoft VX3000 +sonixj 045e:00f7 MicroSoft VX1000 +ov519 045e:028c Micro$oft xbox cam +kinect 045e:02ae Xbox NUI Camera +kinect 045e:02bf Kinect for Windows NUI Camera +spca561 0461:0815 Micro Innovations IC200 Webcam +sunplus 0461:0821 Fujifilm MV-1 +zc3xx 0461:0a00 MicroInnovation WebCam320 +stv06xx 046D:08F0 QuickCamMessenger +stv06xx 046D:08F5 QuickCamCommunicate +stv06xx 046D:08F6 QuickCamMessenger (new) +stv06xx 046d:0840 QuickCamExpress +stv06xx 046d:0850 LEGOcam / QuickCam Web +stv06xx 046d:0870 DexxaWebCam USB +spca500 046d:0890 Logitech QuickCam traveler +vc032x 046d:0892 Logitech Orbicam +vc032x 046d:0896 Logitech Orbicam +vc032x 046d:0897 Logitech QuickCam for Dell notebooks +zc3xx 046d:089d Logitech QuickCam E2500 +zc3xx 046d:08a0 Logitech QC IM +zc3xx 046d:08a1 Logitech QC IM 0x08A1 +sound +zc3xx 046d:08a2 Labtec Webcam Pro +zc3xx 046d:08a3 Logitech QC Chat +zc3xx 046d:08a6 Logitech QCim +zc3xx 046d:08a7 Logitech QuickCam Image +zc3xx 046d:08a9 Logitech Notebook Deluxe +zc3xx 046d:08aa Labtec Webcam Notebook +zc3xx 046d:08ac Logitech QuickCam Cool +zc3xx 046d:08ad Logitech QCCommunicate STX +zc3xx 046d:08ae Logitech QuickCam for Notebooks +zc3xx 046d:08af Logitech QuickCam Cool +zc3xx 046d:08b9 Logitech QuickCam Express +zc3xx 046d:08d7 Logitech QCam STX +zc3xx 046d:08d8 Logitech Notebook Deluxe +zc3xx 046d:08d9 Logitech QuickCam IM/Connect +zc3xx 046d:08da Logitech QuickCam Messenger +zc3xx 046d:08dd Logitech QuickCam for Notebooks +spca500 046d:0900 Logitech Inc. ClickSmart 310 +spca500 046d:0901 Logitech Inc. ClickSmart 510 +sunplus 046d:0905 Logitech ClickSmart 820 +tv8532 046d:0920 Logitech QuickCam Express +tv8532 046d:0921 Labtec Webcam +spca561 046d:0928 Logitech QC Express Etch2 +spca561 046d:0929 Labtec Webcam Elch2 +spca561 046d:092a Logitech QC for Notebook +spca561 046d:092b Labtec Webcam Plus +spca561 046d:092c Logitech QC chat Elch2 +spca561 046d:092d Logitech QC Elch2 +spca561 046d:092e Logitech QC Elch2 +spca561 046d:092f Logitech QuickCam Express Plus +sunplus 046d:0960 Logitech ClickSmart 420 +nw80x 046d:d001 Logitech QuickCam Pro (dark focus ring) +se401 0471:030b PhilipsPCVC665K +sunplus 0471:0322 Philips DMVC1300K +zc3xx 0471:0325 Philips SPC 200 NC +zc3xx 0471:0326 Philips SPC 300 NC +sonixj 0471:0327 Philips SPC 600 NC +sonixj 0471:0328 Philips SPC 700 NC +zc3xx 0471:032d Philips SPC 210 NC +zc3xx 0471:032e Philips SPC 315 NC +sonixj 0471:0330 Philips SPC 710 NC +se401 047d:5001 Kensington67014 +se401 047d:5002 Kensington6701(5/7) +se401 047d:5003 Kensington67016 +spca501 0497:c001 Smile International +sunplus 04a5:3003 Benq DC 1300 +sunplus 04a5:3008 Benq DC 1500 +sunplus 04a5:300a Benq DC 3410 +spca500 04a5:300c Benq DC 1016 +benq 04a5:3035 Benq DC E300 +vicam 04c1:009d HomeConnect Webcam [vicam] +konica 04c8:0720 IntelYC 76 +finepix 04cb:0104 Fujifilm FinePix 4800 +finepix 04cb:0109 Fujifilm FinePix A202 +finepix 04cb:010b Fujifilm FinePix A203 +finepix 04cb:010f Fujifilm FinePix A204 +finepix 04cb:0111 Fujifilm FinePix A205 +finepix 04cb:0113 Fujifilm FinePix A210 +finepix 04cb:0115 Fujifilm FinePix A303 +finepix 04cb:0117 Fujifilm FinePix A310 +finepix 04cb:0119 Fujifilm FinePix F401 +finepix 04cb:011b Fujifilm FinePix F402 +finepix 04cb:011d Fujifilm FinePix F410 +finepix 04cb:0121 Fujifilm FinePix F601 +finepix 04cb:0123 Fujifilm FinePix F700 +finepix 04cb:0125 Fujifilm FinePix M603 +finepix 04cb:0127 Fujifilm FinePix S300 +finepix 04cb:0129 Fujifilm FinePix S304 +finepix 04cb:012b Fujifilm FinePix S500 +finepix 04cb:012d Fujifilm FinePix S602 +finepix 04cb:012f Fujifilm FinePix S700 +finepix 04cb:0131 Fujifilm FinePix unknown model +finepix 04cb:013b Fujifilm FinePix unknown model +finepix 04cb:013d Fujifilm FinePix unknown model +finepix 04cb:013f Fujifilm FinePix F420 +sunplus 04f1:1001 JVC GC A50 +spca561 04fc:0561 Flexcam 100 +spca1528 04fc:1528 Sunplus MD80 clone +sunplus 04fc:500c Sunplus CA500C +sunplus 04fc:504a Aiptek Mini PenCam 1.3 +sunplus 04fc:504b Maxell MaxPocket LE 1.3 +sunplus 04fc:5330 Digitrex 2110 +sunplus 04fc:5360 Sunplus Generic +spca500 04fc:7333 PalmPixDC85 +sunplus 04fc:ffff Pure DigitalDakota +nw80x 0502:d001 DVC V6 +spca501 0506:00df 3Com HomeConnect Lite +sunplus 052b:1507 Megapixel 5 Pretec DC-1007 +sunplus 052b:1513 Megapix V4 +sunplus 052b:1803 MegaImage VI +nw80x 052b:d001 EZCam Pro p35u +tv8532 0545:808b Veo Stingray +tv8532 0545:8333 Veo Stingray +sunplus 0546:3155 Polaroid PDC3070 +sunplus 0546:3191 Polaroid Ion 80 +sunplus 0546:3273 Polaroid PDC2030 +touptek 0547:6801 TTUCMOS08000KPB, AS MU800 +dtcs033 0547:7303 Anchor Chips, Inc +ov519 054c:0154 Sonny toy4 +ov519 054c:0155 Sonny toy5 +cpia1 0553:0002 CPIA CPiA (version1) based cameras +stv0680 0553:0202 STV0680 Camera +zc3xx 055f:c005 Mustek Wcam300A +spca500 055f:c200 Mustek Gsmart 300 +sunplus 055f:c211 Kowa Bs888e Microcamera +spca500 055f:c220 Gsmart Mini +sunplus 055f:c230 Mustek Digicam 330K +sunplus 055f:c232 Mustek MDC3500 +sunplus 055f:c360 Mustek DV4000 Mpeg4 +sunplus 055f:c420 Mustek gSmart Mini 2 +sunplus 055f:c430 Mustek Gsmart LCD 2 +sunplus 055f:c440 Mustek DV 3000 +sunplus 055f:c520 Mustek gSmart Mini 3 +sunplus 055f:c530 Mustek Gsmart LCD 3 +sunplus 055f:c540 Gsmart D30 +sunplus 055f:c630 Mustek MDC4000 +sunplus 055f:c650 Mustek MDC5500Z +nw80x 055f:d001 Mustek Wcam 300 mini +zc3xx 055f:d003 Mustek WCam300A +zc3xx 055f:d004 Mustek WCam300 AN +conex 0572:0041 Creative Notebook cx11646 +ov519 05a9:0511 Video Blaster WebCam 3/WebCam Plus, D-Link USB Digital Video Camera +ov519 05a9:0518 Creative WebCam +ov519 05a9:0519 OV519 Microphone +ov519 05a9:0530 OmniVision +ov534_9 05a9:1550 OmniVision VEHO Filmscanner +ov519 05a9:2800 OmniVision SuperCAM +ov519 05a9:4519 Webcam Classic +ov534_9 05a9:8065 OmniVision test kit ov538+ov9712 +ov519 05a9:8519 OmniVision +ov519 05a9:a511 D-Link USB Digital Video Camera +ov519 05a9:a518 D-Link DSB-C310 Webcam +sunplus 05da:1018 Digital Dream Enigma 1.3 +stk014 05e1:0893 Syntek DV4000 +gl860 05e3:0503 Genesys Logic PC Camera +gl860 05e3:f191 Genesys Logic PC Camera +vicam 0602:1001 ViCam Webcam +spca561 060b:a001 Maxell Compact Pc PM3 +zc3xx 0698:2003 CTX M730V built in +topro 06a2:0003 TP6800 PC Camera, CmoX CX0342 webcam +topro 06a2:6810 Creative Qmax +nw80x 06a5:0000 Typhoon Webcam 100 USB +nw80x 06a5:d001 Divio based webcams +nw80x 06a5:d800 Divio Chicony TwinkleCam, Trust SpaceCam +spca500 06bd:0404 Agfa CL20 +spca500 06be:0800 Optimedia +nw80x 06be:d001 EZCam Pro p35u +sunplus 06d6:0031 Trust 610 LCD PowerC@m Zoom +sunplus 06d6:0041 Aashima Technology B.V. +spca506 06e1:a190 ADS Instant VCD +ov534 06f8:3002 Hercules Blog Webcam +ov534_9 06f8:3003 Hercules Dualpix HD Weblog +sonixj 06f8:3004 Hercules Classic Silver +sonixj 06f8:3008 Hercules Deluxe Optical Glass +pac7302 06f8:3009 Hercules Classic Link +pac7302 06f8:301b Hercules Link +nw80x 0728:d001 AVerMedia Camguard +spca508 0733:0110 ViewQuest VQ110 +spca501 0733:0401 Intel Create and Share +spca501 0733:0402 ViewQuest M318B +spca505 0733:0430 Intel PC Camera Pro +sunplus 0733:1311 Digital Dream Epsilon 1.3 +sunplus 0733:1314 Mercury 2.1MEG Deluxe Classic Cam +sunplus 0733:2211 Jenoptik jdc 21 LCD +sunplus 0733:2221 Mercury Digital Pro 3.1p +sunplus 0733:3261 Concord 3045 spca536a +sunplus 0733:3281 Cyberpix S550V +spca506 0734:043b 3DeMon USB Capture aka +cpia1 0813:0001 QX3 camera +ov519 0813:0002 Dual Mode USB Camera Plus +spca500 084d:0003 D-Link DSC-350 +spca500 08ca:0103 Aiptek PocketDV +sunplus 08ca:0104 Aiptek PocketDVII 1.3 +sunplus 08ca:0106 Aiptek Pocket DV3100+ +mr97310a 08ca:0110 Trust Spyc@m 100 +mr97310a 08ca:0111 Aiptek PenCam VGA+ +sunplus 08ca:2008 Aiptek Mini PenCam 2 M +sunplus 08ca:2010 Aiptek PocketCam 3M +sunplus 08ca:2016 Aiptek PocketCam 2 Mega +sunplus 08ca:2018 Aiptek Pencam SD 2M +sunplus 08ca:2020 Aiptek Slim 3000F +sunplus 08ca:2022 Aiptek Slim 3200 +sunplus 08ca:2024 Aiptek DV3500 Mpeg4 +sunplus 08ca:2028 Aiptek PocketCam4M +sunplus 08ca:2040 Aiptek PocketDV4100M +sunplus 08ca:2042 Aiptek PocketDV5100 +sunplus 08ca:2050 Medion MD 41437 +sunplus 08ca:2060 Aiptek PocketDV5300 +tv8532 0923:010f ICM532 cams +mr97310a 093a:010e All known CIF cams with this ID +mr97310a 093a:010f All known VGA cams with this ID +mars 093a:050f Mars-Semi Pc-Camera +pac207 093a:2460 Qtec Webcam 100 +pac207 093a:2461 HP Webcam +pac207 093a:2463 Philips SPC 220 NC +pac207 093a:2464 Labtec Webcam 1200 +pac207 093a:2468 Webcam WB-1400T +pac207 093a:2470 Genius GF112 +pac207 093a:2471 Genius VideoCam ge111 +pac207 093a:2472 Genius VideoCam ge110 +pac207 093a:2474 Genius iLook 111 +pac207 093a:2476 Genius e-Messenger 112 +pac7311 093a:2600 PAC7311 Typhoon +pac7311 093a:2601 Philips SPC 610 NC +pac7311 093a:2603 Philips SPC 500 NC +pac7311 093a:2608 Trust WB-3300p +pac7311 093a:260e Gigaware VGA PC Camera, Trust WB-3350p, SIGMA cam 2350 +pac7311 093a:260f SnakeCam +pac7302 093a:2620 Apollo AC-905 +pac7302 093a:2621 PAC731x +pac7302 093a:2622 Genius Eye 312 +pac7302 093a:2623 Pixart Imaging, Inc. +pac7302 093a:2624 PAC7302 +pac7302 093a:2625 Genius iSlim 310 +pac7302 093a:2626 Labtec 2200 +pac7302 093a:2627 Genius FaceCam 300 +pac7302 093a:2628 Genius iLook 300 +pac7302 093a:2629 Genious iSlim 300 +pac7302 093a:262a Webcam 300k +pac7302 093a:262c Philips SPC 230 NC +jl2005bcd 0979:0227 Various brands, 19 known cameras supported +jeilinj 0979:0270 Sakar 57379 +jeilinj 0979:0280 Sportscam DV15, Sakar 57379 +zc3xx 0ac8:0301 Web Camera +zc3xx 0ac8:0302 Z-star Vimicro zc0302 +vc032x 0ac8:0321 Vimicro generic vc0321 +vc032x 0ac8:0323 Vimicro Vc0323 +vc032x 0ac8:0328 A4Tech PK-130MG +zc3xx 0ac8:301b Z-Star zc301b +zc3xx 0ac8:303b Vimicro 0x303b +zc3xx 0ac8:305b Z-star Vimicro zc0305b +zc3xx 0ac8:307b PC Camera (ZS0211) +vc032x 0ac8:c001 Sony embedded vimicro +vc032x 0ac8:c002 Sony embedded vimicro +vc032x 0ac8:c301 Samsung Q1 Ultra Premium +spca508 0af9:0010 Hama USB Sightcam 100 +spca508 0af9:0011 Hama USB Sightcam 100 +ov519 0b62:0059 iBOT2 Webcam +sonixb 0c45:6001 Genius VideoCAM NB +sonixb 0c45:6005 Microdia Sweex Mini Webcam +sonixb 0c45:6007 Sonix sn9c101 + Tas5110D +sonixb 0c45:6009 spcaCam@120 +sonixb 0c45:600d spcaCam@120 +sonixb 0c45:6011 Microdia PC Camera (SN9C102) +sonixb 0c45:6019 Generic Sonix OV7630 +sonixb 0c45:6024 Generic Sonix Tas5130c +sonixb 0c45:6025 Xcam Shanga +sonixb 0c45:6027 GeniusEye 310 +sonixb 0c45:6028 Sonix Btc Pc380 +sonixb 0c45:6029 spcaCam@150 +sonixb 0c45:602a Meade ETX-105EC Camera +sonixb 0c45:602c Generic Sonix OV7630 +sonixb 0c45:602d LIC-200 LG +sonixb 0c45:602e Genius VideoCam Messenger +sonixj 0c45:6040 Speed NVC 350K +sonixj 0c45:607c Sonix sn9c102p Hv7131R +sonixb 0c45:6083 VideoCAM Look +sonixb 0c45:608c VideoCAM Look +sonixb 0c45:608f PC Camera (SN9C103 + OV7630) +sonixb 0c45:60a8 VideoCAM Look +sonixb 0c45:60aa VideoCAM Look +sonixb 0c45:60af VideoCAM Look +sonixb 0c45:60b0 Genius VideoCam Look +sonixj 0c45:60c0 Sangha Sn535 +sonixj 0c45:60ce USB-PC-Camera-168 (TALK-5067) +sonixj 0c45:60ec SN9C105+MO4000 +sonixj 0c45:60fb Surfer NoName +sonixj 0c45:60fc LG-LIC300 +sonixj 0c45:60fe Microdia Audio +sonixj 0c45:6100 PC Camera (SN9C128) +sonixj 0c45:6102 PC Camera (SN9C128) +sonixj 0c45:610a PC Camera (SN9C128) +sonixj 0c45:610b PC Camera (SN9C128) +sonixj 0c45:610c PC Camera (SN9C128) +sonixj 0c45:610e PC Camera (SN9C128) +sonixj 0c45:6128 Microdia/Sonix SNP325 +sonixj 0c45:612a Avant Camera +sonixj 0c45:612b Speed-Link REFLECT2 +sonixj 0c45:612c Typhoon Rasy Cam 1.3MPix +sonixj 0c45:612e PC Camera (SN9C110) +sonixj 0c45:6130 Sonix Pccam +sonixj 0c45:6138 Sn9c120 Mo4000 +sonixj 0c45:613a Microdia Sonix PC Camera +sonixj 0c45:613b Surfer SN-206 +sonixj 0c45:613c Sonix Pccam168 +sonixj 0c45:613e PC Camera (SN9C120) +sonixj 0c45:6142 Hama PC-Webcam AC-150 +sonixj 0c45:6143 Sonix Pccam168 +sonixj 0c45:6148 Digitus DA-70811/ZSMC USB PC Camera ZS211/Microdia +sonixj 0c45:614a Frontech E-Ccam (JIL-2225) +sn9c20x 0c45:6240 PC Camera (SN9C201 + MT9M001) +sn9c20x 0c45:6242 PC Camera (SN9C201 + MT9M111) +sn9c20x 0c45:6248 PC Camera (SN9C201 + OV9655) +sn9c20x 0c45:624c PC Camera (SN9C201 + MT9M112) +sn9c20x 0c45:624e PC Camera (SN9C201 + SOI968) +sn9c20x 0c45:624f PC Camera (SN9C201 + OV9650) +sn9c20x 0c45:6251 PC Camera (SN9C201 + OV9650) +sn9c20x 0c45:6253 PC Camera (SN9C201 + OV9650) +sn9c20x 0c45:6260 PC Camera (SN9C201 + OV7670) +sn9c20x 0c45:6270 PC Camera (SN9C201 + MT9V011/MT9V111/MT9V112) +sn9c20x 0c45:627b PC Camera (SN9C201 + OV7660) +sn9c20x 0c45:627c PC Camera (SN9C201 + HV7131R) +sn9c20x 0c45:627f PC Camera (SN9C201 + OV9650) +sn9c20x 0c45:6280 PC Camera (SN9C202 + MT9M001) +sn9c20x 0c45:6282 PC Camera (SN9C202 + MT9M111) +sn9c20x 0c45:6288 PC Camera (SN9C202 + OV9655) +sn9c20x 0c45:628c PC Camera (SN9C201 + MT9M112) +sn9c20x 0c45:628e PC Camera (SN9C202 + SOI968) +sn9c20x 0c45:628f PC Camera (SN9C202 + OV9650) +sn9c20x 0c45:62a0 PC Camera (SN9C202 + OV7670) +sn9c20x 0c45:62b0 PC Camera (SN9C202 + MT9V011/MT9V111/MT9V112) +sn9c20x 0c45:62b3 PC Camera (SN9C202 + OV9655) +sn9c20x 0c45:62bb PC Camera (SN9C202 + OV7660) +sn9c20x 0c45:62bc PC Camera (SN9C202 + HV7131R) +sn9c2028 0c45:8001 Wild Planet Digital Spy Camera +sn9c2028 0c45:8003 Sakar #11199, #6637x, #67480 keychain cams +sn9c2028 0c45:8008 Mini-Shotz ms-350 +sn9c2028 0c45:800a Vivitar Vivicam 3350B +sunplus 0d64:0303 Sunplus FashionCam DXG +ov519 0e96:c001 TRUST 380 USB2 SPACEC@M +etoms 102c:6151 Qcam Sangha CIF +etoms 102c:6251 Qcam xxxxxx VGA +ov519 1046:9967 W9967CF/W9968CF WebCam IC, Video Blaster WebCam Go +zc3xx 10fd:0128 Typhoon Webshot II USB 300k 0x0128 +spca561 10fd:7e50 FlyCam Usb 100 +zc3xx 10fd:804d Typhoon Webshot II Webcam [zc0301] +zc3xx 10fd:8050 Typhoon Webshot II USB 300k +ov534 1415:2000 Sony HD Eye for PS3 (SLEH 00201) +pac207 145f:013a Trust WB-1300N +pac7302 145f:013c Trust +sn9c20x 145f:013d Trust WB-3600R +vc032x 15b8:6001 HP 2.0 Megapixel +vc032x 15b8:6002 HP 2.0 Megapixel rz406aa +stk1135 174f:6a31 ASUSlaptop, MT9M112 sensor +spca501 1776:501c Arowana 300K CMOS Camera +t613 17a1:0128 TASCORP JPEG Webcam, NGS Cyclops +vc032x 17ef:4802 Lenovo Vc0323+MI1310_SOC +pac7302 1ae7:2001 SpeedLinkSnappy Mic SL-6825-SBK +pac207 2001:f115 D-Link DSB-C120 +sq905c 2770:9050 Disney pix micro (CIF) +sq905c 2770:9051 Lego Bionicle +sq905c 2770:9052 Disney pix micro 2 (VGA) +sq905c 2770:905c All 11 known cameras with this ID +sq905 2770:9120 All 24 known cameras with this ID +sq905c 2770:913d All 4 known cameras with this ID +sq930x 2770:930b Sweex Motion Tracking / I-Tec iCam Tracer +sq930x 2770:930c Trust WB-3500T / NSG Robbie 2.0 +spca500 2899:012c Toptro Industrial +ov519 8020:ef04 ov519 +spca508 8086:0110 Intel Easy PC Camera +spca500 8086:0630 Intel Pocket PC Camera +spca506 99fa:8988 Grandtec V.cap +sn9c20x a168:0610 Dino-Lite Digital Microscope (SN9C201 + HV7131R) +sn9c20x a168:0611 Dino-Lite Digital Microscope (SN9C201 + HV7131R) +sn9c20x a168:0613 Dino-Lite Digital Microscope (SN9C201 + HV7131R) +sn9c20x a168:0614 Dino-Lite Digital Microscope (SN9C201 + MT9M111) +sn9c20x a168:0615 Dino-Lite Digital Microscope (SN9C201 + MT9M111) +sn9c20x a168:0617 Dino-Lite Digital Microscope (SN9C201 + MT9M111) +sn9c20x a168:0618 Dino-Lite Digital Microscope (SN9C201 + HV7131R) +spca561 abcd:cdee Petcam +========= ========= =================================================================== diff --git a/Documentation/media/v4l-drivers/index.rst b/Documentation/media/v4l-drivers/index.rst index aac566f88833..a606d1cdac13 100644 --- a/Documentation/media/v4l-drivers/index.rst +++ b/Documentation/media/v4l-drivers/index.rst @@ -2,6 +2,8 @@ .. include:: +.. _v4l-drivers: + ################################################ Video4Linux (V4L) driver-specific documentation ################################################ @@ -46,6 +48,7 @@ For more details see the file COPYING in the source distribution of Linux. pvrusb2 pxa_camera radiotrack + rcar-fdp1 saa7134 sh_mobile_ceu_camera si470x diff --git a/Documentation/media/v4l-drivers/ivtv-cardlist.rst b/Documentation/media/v4l-drivers/ivtv-cardlist.rst index cd7e79d2963e..754ffa820b4c 100644 --- a/Documentation/media/v4l-drivers/ivtv-cardlist.rst +++ b/Documentation/media/v4l-drivers/ivtv-cardlist.rst @@ -1,29 +1,38 @@ IVTV cards list =============== -.. code-block:: none - - 1 -> Hauppauge WinTV PVR-250 - 2 -> Hauppauge WinTV PVR-350 - 3 -> Hauppauge WinTV PVR-150 or PVR-500 - 4 -> AVerMedia M179 [1461:a3ce,1461:a3cf] - 5 -> Yuan MPG600/Kuroutoshikou iTVC16-STVLP [12ab:fff3,12ab:ffff] - 6 -> Yuan MPG160/Kuroutoshikou iTVC15-STVLP [12ab:0000,10fc:40a0] - 7 -> Yuan PG600/DiamondMM PVR-550 [ff92:0070,ffab:0600] - 8 -> Adaptec AVC-2410 [9005:0093] - 9 -> Adaptec AVC-2010 [9005:0092] - 10 -> NAGASE TRANSGEAR 5000TV [1461:bfff] - 11 -> AOpen VA2000MAX-STN6 [0000:ff5f] - 12 -> YUAN MPG600GR/Kuroutoshikou CX23416GYC-STVLP [12ab:0600,fbab:0600,1154:0523] - 13 -> I/O Data GV-MVP/RX [10fc:d01e,10fc:d038,10fc:d039] - 14 -> I/O Data GV-MVP/RX2E [10fc:d025] - 15 -> GOTVIEW PCI DVD (partial support only) [12ab:0600] - 16 -> GOTVIEW PCI DVD2 Deluxe [ffac:0600] - 17 -> Yuan MPC622 [ff01:d998] - 18 -> Digital Cowboy DCT-MTVP1 [1461:bfff] - 19 -> Yuan PG600V2/GotView PCI DVD Lite [ffab:0600,ffad:0600] - 20 -> Club3D ZAP-TV1x01 [ffab:0600] - 21 -> AverTV MCE 116 Plus [1461:c439] - 22 -> ASUS Falcon2 [1043:4b66,1043:462e,1043:4b2e] - 23 -> AverMedia PVR-150 Plus [1461:c035] - 24 -> AverMedia EZMaker PCI Deluxe [1461:c03f] +=========== ============================================================= ==================================================== +Card number Card name PCI IDs +=========== ============================================================= ==================================================== +0 Hauppauge WinTV PVR-250 IVTV16 104d:813d +1 Hauppauge WinTV PVR-350 IVTV16 104d:813d +2 Hauppauge WinTV PVR-150 IVTV16 104d:813d +3 AVerMedia M179 IVTV15 1461:a3cf, IVTV15 1461:a3ce +4 Yuan MPG600, Kuroutoshikou ITVC16-STVLP IVTV16 12ab:fff3, IVTV16 12ab:ffff +5 YUAN MPG160, Kuroutoshikou ITVC15-STVLP, I/O Data GV-M2TV/PCI IVTV15 10fc:40a0 +6 Yuan PG600, Diamond PVR-550 IVTV16 ff92:0070, IVTV16 ffab:0600 +7 Adaptec VideOh! AVC-2410 IVTV16 9005:0093 +8 Adaptec VideOh! AVC-2010 IVTV16 9005:0092 +9 Nagase Transgear 5000TV IVTV16 1461:bfff +10 AOpen VA2000MAX-SNT6 IVTV16 0000:ff5f +11 Yuan MPG600GR, Kuroutoshikou CX23416GYC-STVLP IVTV16 12ab:0600, IVTV16 fbab:0600, IVTV16 1154:0523 +12 I/O Data GV-MVP/RX, GV-MVP/RX2W (dual tuner) IVTV16 10fc:d01e, IVTV16 10fc:d038, IVTV16 10fc:d039 +13 I/O Data GV-MVP/RX2E IVTV16 10fc:d025 +14 GotView PCI DVD IVTV16 12ab:0600 +15 GotView PCI DVD2 Deluxe IVTV16 ffac:0600 +16 Yuan MPC622 IVTV16 ff01:d998 +17 Digital Cowboy DCT-MTVP1 IVTV16 1461:bfff +18 Yuan PG600-2, GotView PCI DVD Lite IVTV16 ffab:0600, IVTV16 ffad:0600 +19 Club3D ZAP-TV1x01 IVTV16 ffab:0600 +20 AVerTV MCE 116 Plus IVTV16 1461:c439 +21 ASUS Falcon2 IVTV16 1043:4b66, IVTV16 1043:462e, IVTV16 1043:4b2e +22 AVerMedia PVR-150 Plus / AVerTV M113 Partsnic (Daewoo) Tuner IVTV16 1461:c034, IVTV16 1461:c035 +23 AVerMedia EZMaker PCI Deluxe IVTV16 1461:c03f +24 AVerMedia M104 IVTV16 1461:c136 +25 Buffalo PC-MV5L/PCI IVTV16 1154:052b +26 AVerMedia UltraTV 1500 MCE / AVerTV M113 Philips Tuner IVTV16 1461:c019, IVTV16 1461:c01b +27 Sony VAIO Giga Pocket (ENX Kikyou) IVTV16 104d:813d +28 Hauppauge WinTV PVR-350 (V1) IVTV16 104d:813d +29 Yuan MPG600GR, Kuroutoshikou CX23416GYC-STVLP (no GR) IVTV16 104d:813d +30 Yuan MPG600GR, Kuroutoshikou CX23416GYC-STVLP (no GR/YCS) IVTV16 104d:813d +=========== ============================================================= ==================================================== diff --git a/Documentation/media/v4l-drivers/rcar-fdp1.rst b/Documentation/media/v4l-drivers/rcar-fdp1.rst new file mode 100644 index 000000000000..a59b1e8e3e9c --- /dev/null +++ b/Documentation/media/v4l-drivers/rcar-fdp1.rst @@ -0,0 +1,37 @@ +Renesas R-Car Fine Display Processor (FDP1) Driver +================================================== + +The R-Car FDP1 driver implements driver-specific controls as follows. + +``V4L2_CID_DEINTERLACING_MODE (menu)`` + The video deinterlacing mode (such as Bob, Weave, ...). The R-Car FDP1 + driver implements the following modes. + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + :widths: 1 4 + + * - ``"Progressive" (0)`` + - The input image video stream is progressive (not interlaced). No + deinterlacing is performed. Apart from (optional) format and encoding + conversion output frames are identical to the input frames. + * - ``"Adaptive 2D/3D" (1)`` + - Motion adaptive version of 2D and 3D deinterlacing. Use 3D deinterlacing + in the presence of fast motion and 2D deinterlacing with diagonal + interpolation otherwise. + * - ``"Fixed 2D" (2)`` + - The current field is scaled vertically by averaging adjacent lines to + recover missing lines. This method is also known as blending or Line + Averaging (LAV). + * - ``"Fixed 3D" (3)`` + - The previous and next fields are averaged to recover lines missing from + the current field. This method is also known as Field Averaging (FAV). + * - ``"Previous field" (4)`` + - The current field is weaved with the previous field, i.e. the previous + field is used to fill missing lines from the current field. This method + is also known as weave deinterlacing. + * - ``"Next field" (5)`` + - The current field is weaved with the next field, i.e. the next field is + used to fill missing lines from the current field. This method is also + known as weave deinterlacing. diff --git a/Documentation/media/v4l-drivers/saa7134-cardlist.rst b/Documentation/media/v4l-drivers/saa7134-cardlist.rst index 22c1510d9fa6..a5efa8f4b8e4 100644 --- a/Documentation/media/v4l-drivers/saa7134-cardlist.rst +++ b/Documentation/media/v4l-drivers/saa7134-cardlist.rst @@ -1,202 +1,204 @@ SAA7134 cards list ================== -.. code-block:: none - - 0 -> UNKNOWN/GENERIC - 1 -> Proteus Pro [philips reference design] [1131:2001,1131:2001] - 2 -> LifeView FlyVIDEO3000 [5168:0138,4e42:0138] - 3 -> LifeView/Typhoon FlyVIDEO2000 [5168:0138,4e42:0138] - 4 -> EMPRESS [1131:6752] - 5 -> SKNet Monster TV [1131:4e85] - 6 -> Tevion MD 9717 - 7 -> KNC One TV-Station RDS / Typhoon TV Tuner RDS [1131:fe01,1894:fe01] - 8 -> Terratec Cinergy 400 TV [153b:1142] - 9 -> Medion 5044 - 10 -> Kworld/KuroutoShikou SAA7130-TVPCI - 11 -> Terratec Cinergy 600 TV [153b:1143] - 12 -> Medion 7134 [16be:0003,16be:5000] - 13 -> Typhoon TV+Radio 90031 - 14 -> ELSA EX-VISION 300TV [1048:226b] - 15 -> ELSA EX-VISION 500TV [1048:226a] - 16 -> ASUS TV-FM 7134 [1043:4842,1043:4830,1043:4840] - 17 -> AOPEN VA1000 POWER [1131:7133] - 18 -> BMK MPEX No Tuner - 19 -> Compro VideoMate TV [185b:c100] - 20 -> Matrox CronosPlus [102B:48d0] - 21 -> 10MOONS PCI TV CAPTURE CARD [1131:2001] - 22 -> AverMedia M156 / Medion 2819 [1461:a70b] - 23 -> BMK MPEX Tuner - 24 -> KNC One TV-Station DVR [1894:a006] - 25 -> ASUS TV-FM 7133 [1043:4843] - 26 -> Pinnacle PCTV Stereo (saa7134) [11bd:002b] - 27 -> Manli MuchTV M-TV002 - 28 -> Manli MuchTV M-TV001 - 29 -> Nagase Sangyo TransGear 3000TV [1461:050c] - 30 -> Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM) [1019:4cb4] - 31 -> Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM) [1019:4cb5] - 32 -> AVACS SmartTV - 33 -> AVerMedia DVD EZMaker [1461:10ff] - 34 -> Noval Prime TV 7133 - 35 -> AverMedia AverTV Studio 305 [1461:2115] - 36 -> UPMOST PURPLE TV [12ab:0800] - 37 -> Items MuchTV Plus / IT-005 - 38 -> Terratec Cinergy 200 TV [153b:1152] - 39 -> LifeView FlyTV Platinum Mini [5168:0212,4e42:0212,5169:1502] - 40 -> Compro VideoMate TV PVR/FM [185b:c100] - 41 -> Compro VideoMate TV Gold+ [185b:c100] - 42 -> Sabrent SBT-TVFM (saa7130) - 43 -> :Zolid Xpert TV7134 - 44 -> Empire PCI TV-Radio LE - 45 -> Avermedia AVerTV Studio 307 [1461:9715] - 46 -> AVerMedia Cardbus TV/Radio (E500) [1461:d6ee] - 47 -> Terratec Cinergy 400 mobile [153b:1162] - 48 -> Terratec Cinergy 600 TV MK3 [153b:1158] - 49 -> Compro VideoMate Gold+ Pal [185b:c200] - 50 -> Pinnacle PCTV 300i DVB-T + PAL [11bd:002d] - 51 -> ProVideo PV952 [1540:9524] - 52 -> AverMedia AverTV/305 [1461:2108] - 53 -> ASUS TV-FM 7135 [1043:4845] - 54 -> LifeView FlyTV Platinum FM / Gold [5168:0214,5168:5214,1489:0214,5168:0304] - 55 -> LifeView FlyDVB-T DUO / MSI TV@nywhere Duo [5168:0306,4E42:0306] - 56 -> Avermedia AVerTV 307 [1461:a70a] - 57 -> Avermedia AVerTV GO 007 FM [1461:f31f] - 58 -> ADS Tech Instant TV (saa7135) [1421:0350,1421:0351,1421:0370,1421:1370] - 59 -> Kworld/Tevion V-Stream Xpert TV PVR7134 - 60 -> LifeView/Typhoon/Genius FlyDVB-T Duo Cardbus [5168:0502,4e42:0502,1489:0502] - 61 -> Philips TOUGH DVB-T reference design [1131:2004] - 62 -> Compro VideoMate TV Gold+II - 63 -> Kworld Xpert TV PVR7134 - 64 -> FlyTV mini Asus Digimatrix [1043:0210] - 65 -> V-Stream Studio TV Terminator - 66 -> Yuan TUN-900 (saa7135) - 67 -> Beholder BeholdTV 409 FM [0000:4091] - 68 -> GoTView 7135 PCI [5456:7135] - 69 -> Philips EUROPA V3 reference design [1131:2004] - 70 -> Compro Videomate DVB-T300 [185b:c900] - 71 -> Compro Videomate DVB-T200 [185b:c901] - 72 -> RTD Embedded Technologies VFG7350 [1435:7350] - 73 -> RTD Embedded Technologies VFG7330 [1435:7330] - 74 -> LifeView FlyTV Platinum Mini2 [14c0:1212] - 75 -> AVerMedia AVerTVHD MCE A180 [1461:1044] - 76 -> SKNet MonsterTV Mobile [1131:4ee9] - 77 -> Pinnacle PCTV 40i/50i/110i (saa7133) [11bd:002e] - 78 -> ASUSTeK P7131 Dual [1043:4862] - 79 -> Sedna/MuchTV PC TV Cardbus TV/Radio (ITO25 Rev:2B) - 80 -> ASUS Digimatrix TV [1043:0210] - 81 -> Philips Tiger reference design [1131:2018] - 82 -> MSI TV@Anywhere plus [1462:6231,1462:8624] - 83 -> Terratec Cinergy 250 PCI TV [153b:1160] - 84 -> LifeView FlyDVB Trio [5168:0319] - 85 -> AverTV DVB-T 777 [1461:2c05,1461:2c05] - 86 -> LifeView FlyDVB-T / Genius VideoWonder DVB-T [5168:0301,1489:0301] - 87 -> ADS Instant TV Duo Cardbus PTV331 [0331:1421] - 88 -> Tevion/KWorld DVB-T 220RF [17de:7201] - 89 -> ELSA EX-VISION 700TV [1048:226c] - 90 -> Kworld ATSC110/115 [17de:7350,17de:7352] - 91 -> AVerMedia A169 B [1461:7360] - 92 -> AVerMedia A169 B1 [1461:6360] - 93 -> Medion 7134 Bridge #2 [16be:0005] - 94 -> LifeView FlyDVB-T Hybrid Cardbus/MSI TV @nywhere A/D NB [5168:3306,5168:3502,5168:3307,4e42:3502] - 95 -> LifeView FlyVIDEO3000 (NTSC) [5169:0138] - 96 -> Medion Md8800 Quadro [16be:0007,16be:0008,16be:000d] - 97 -> LifeView FlyDVB-S /Acorp TV134DS [5168:0300,4e42:0300] - 98 -> Proteus Pro 2309 [0919:2003] - 99 -> AVerMedia TV Hybrid A16AR [1461:2c00] - 100 -> Asus Europa2 OEM [1043:4860] - 101 -> Pinnacle PCTV 310i [11bd:002f] - 102 -> Avermedia AVerTV Studio 507 [1461:9715] - 103 -> Compro Videomate DVB-T200A - 104 -> Hauppauge WinTV-HVR1110 DVB-T/Hybrid [0070:6700,0070:6701,0070:6702,0070:6703,0070:6704,0070:6705] - 105 -> Terratec Cinergy HT PCMCIA [153b:1172] - 106 -> Encore ENLTV [1131:2342,1131:2341,3016:2344] - 107 -> Encore ENLTV-FM [1131:230f] - 108 -> Terratec Cinergy HT PCI [153b:1175] - 109 -> Philips Tiger - S Reference design - 110 -> Avermedia M102 [1461:f31e] - 111 -> ASUS P7131 4871 [1043:4871] - 112 -> ASUSTeK P7131 Hybrid [1043:4876] - 113 -> Elitegroup ECS TVP3XP FM1246 Tuner Card (PAL,FM) [1019:4cb6] - 114 -> KWorld DVB-T 210 [17de:7250] - 115 -> Sabrent PCMCIA TV-PCB05 [0919:2003] - 116 -> 10MOONS TM300 TV Card [1131:2304] - 117 -> Avermedia Super 007 [1461:f01d] - 118 -> Beholder BeholdTV 401 [0000:4016] - 119 -> Beholder BeholdTV 403 [0000:4036] - 120 -> Beholder BeholdTV 403 FM [0000:4037] - 121 -> Beholder BeholdTV 405 [0000:4050] - 122 -> Beholder BeholdTV 405 FM [0000:4051] - 123 -> Beholder BeholdTV 407 [0000:4070] - 124 -> Beholder BeholdTV 407 FM [0000:4071] - 125 -> Beholder BeholdTV 409 [0000:4090] - 126 -> Beholder BeholdTV 505 FM [5ace:5050] - 127 -> Beholder BeholdTV 507 FM / BeholdTV 509 FM [5ace:5070,5ace:5090] - 128 -> Beholder BeholdTV Columbus TV/FM [0000:5201] - 129 -> Beholder BeholdTV 607 FM [5ace:6070] - 130 -> Beholder BeholdTV M6 [5ace:6190] - 131 -> Twinhan Hybrid DTV-DVB 3056 PCI [1822:0022] - 132 -> Genius TVGO AM11MCE - 133 -> NXP Snake DVB-S reference design - 134 -> Medion/Creatix CTX953 Hybrid [16be:0010] - 135 -> MSI TV@nywhere A/D v1.1 [1462:8625] - 136 -> AVerMedia Cardbus TV/Radio (E506R) [1461:f436] - 137 -> AVerMedia Hybrid TV/Radio (A16D) [1461:f936] - 138 -> Avermedia M115 [1461:a836] - 139 -> Compro VideoMate T750 [185b:c900] - 140 -> Avermedia DVB-S Pro A700 [1461:a7a1] - 141 -> Avermedia DVB-S Hybrid+FM A700 [1461:a7a2] - 142 -> Beholder BeholdTV H6 [5ace:6290] - 143 -> Beholder BeholdTV M63 [5ace:6191] - 144 -> Beholder BeholdTV M6 Extra [5ace:6193] - 145 -> AVerMedia MiniPCI DVB-T Hybrid M103 [1461:f636,1461:f736] - 146 -> ASUSTeK P7131 Analog - 147 -> Asus Tiger 3in1 [1043:4878] - 148 -> Encore ENLTV-FM v5.3 [1a7f:2008] - 149 -> Avermedia PCI pure analog (M135A) [1461:f11d] - 150 -> Zogis Real Angel 220 - 151 -> ADS Tech Instant HDTV [1421:0380] - 152 -> Asus Tiger Rev:1.00 [1043:4857] - 153 -> Kworld Plus TV Analog Lite PCI [17de:7128] - 154 -> Avermedia AVerTV GO 007 FM Plus [1461:f31d] - 155 -> Hauppauge WinTV-HVR1150 ATSC/QAM-Hybrid [0070:6706,0070:6708] - 156 -> Hauppauge WinTV-HVR1120 DVB-T/Hybrid [0070:6707,0070:6709,0070:670a] - 157 -> Avermedia AVerTV Studio 507UA [1461:a11b] - 158 -> AVerMedia Cardbus TV/Radio (E501R) [1461:b7e9] - 159 -> Beholder BeholdTV 505 RDS [0000:505B] - 160 -> Beholder BeholdTV 507 RDS [0000:5071] - 161 -> Beholder BeholdTV 507 RDS [0000:507B] - 162 -> Beholder BeholdTV 607 FM [5ace:6071] - 163 -> Beholder BeholdTV 609 FM [5ace:6090] - 164 -> Beholder BeholdTV 609 FM [5ace:6091] - 165 -> Beholder BeholdTV 607 RDS [5ace:6072] - 166 -> Beholder BeholdTV 607 RDS [5ace:6073] - 167 -> Beholder BeholdTV 609 RDS [5ace:6092] - 168 -> Beholder BeholdTV 609 RDS [5ace:6093] - 169 -> Compro VideoMate S350/S300 [185b:c900] - 170 -> AverMedia AverTV Studio 505 [1461:a115] - 171 -> Beholder BeholdTV X7 [5ace:7595] - 172 -> RoverMedia TV Link Pro FM [19d1:0138] - 173 -> Zolid Hybrid TV Tuner PCI [1131:2004] - 174 -> Asus Europa Hybrid OEM [1043:4847] - 175 -> Leadtek Winfast DTV1000S [107d:6655] - 176 -> Beholder BeholdTV 505 RDS [0000:5051] - 177 -> Hawell HW-404M7 - 178 -> Beholder BeholdTV H7 [5ace:7190] - 179 -> Beholder BeholdTV A7 [5ace:7090] - 180 -> Avermedia PCI M733A [1461:4155,1461:4255] - 181 -> TechoTrend TT-budget T-3000 [13c2:2804] - 182 -> Kworld PCI SBTVD/ISDB-T Full-Seg Hybrid [17de:b136] - 183 -> Compro VideoMate Vista M1F [185b:c900] - 184 -> Encore ENLTV-FM 3 [1a7f:2108] - 185 -> MagicPro ProHDTV Pro2 DMB-TH/Hybrid [17de:d136] - 186 -> Beholder BeholdTV 501 [5ace:5010] - 187 -> Beholder BeholdTV 503 FM [5ace:5030] - 188 -> Sensoray 811/911 [6000:0811,6000:0911] - 189 -> Kworld PC150-U [17de:a134] - 190 -> Asus My Cinema PS3-100 [1043:48cd] - 191 -> Hawell HW-9004V1 - 192 -> AverMedia AverTV Satellite Hybrid+FM A706 [1461:2055] - 193 -> WIS Voyager or compatible [1905:7007] - 194 -> AverMedia AverTV/505 [1461:a10a] - 195 -> Leadtek Winfast TV2100 FM [107d:6f3a] - 196 -> SnaZio* TVPVR PRO [1779:13cf] +=========== ======================================================= ================================================================ +Card number Card name PCI IDs +=========== ======================================================= ================================================================ +0 UNKNOWN/GENERIC +1 Proteus Pro [philips reference design] 1131:2001, 1131:2001 +2 LifeView FlyVIDEO3000 5168:0138, 4e42:0138 +3 LifeView/Typhoon FlyVIDEO2000 5168:0138, 4e42:0138 +4 EMPRESS 1131:6752 +5 SKNet Monster TV 1131:4e85 +6 Tevion MD 9717 +7 KNC One TV-Station RDS / Typhoon TV Tuner RDS 1131:fe01, 1894:fe01 +8 Terratec Cinergy 400 TV 153b:1142 +9 Medion 5044 +10 Kworld/KuroutoShikou SAA7130-TVPCI +11 Terratec Cinergy 600 TV 153b:1143 +12 Medion 7134 16be:0003, 16be:5000 +13 Typhoon TV+Radio 90031 +14 ELSA EX-VISION 300TV 1048:226b +15 ELSA EX-VISION 500TV 1048:226a +16 ASUS TV-FM 7134 1043:4842, 1043:4830, 1043:4840 +17 AOPEN VA1000 POWER 1131:7133 +18 BMK MPEX No Tuner +19 Compro VideoMate TV 185b:c100 +20 Matrox CronosPlus 102B:48d0 +21 10MOONS PCI TV CAPTURE CARD 1131:2001 +22 AverMedia M156 / Medion 2819 1461:a70b +23 BMK MPEX Tuner +24 KNC One TV-Station DVR 1894:a006 +25 ASUS TV-FM 7133 1043:4843 +26 Pinnacle PCTV Stereo (saa7134) 11bd:002b +27 Manli MuchTV M-TV002 +28 Manli MuchTV M-TV001 +29 Nagase Sangyo TransGear 3000TV 1461:050c +30 Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM) 1019:4cb4 +31 Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM) 1019:4cb5 +32 AVACS SmartTV +33 AVerMedia DVD EZMaker 1461:10ff +34 Noval Prime TV 7133 +35 AverMedia AverTV Studio 305 1461:2115 +36 UPMOST PURPLE TV 12ab:0800 +37 Items MuchTV Plus / IT-005 +38 Terratec Cinergy 200 TV 153b:1152 +39 LifeView FlyTV Platinum Mini 5168:0212, 4e42:0212, 5169:1502 +40 Compro VideoMate TV PVR/FM 185b:c100 +41 Compro VideoMate TV Gold+ 185b:c100 +42 Sabrent SBT-TVFM (saa7130) +43 :Zolid Xpert TV7134 +44 Empire PCI TV-Radio LE +45 Avermedia AVerTV Studio 307 1461:9715 +46 AVerMedia Cardbus TV/Radio (E500) 1461:d6ee +47 Terratec Cinergy 400 mobile 153b:1162 +48 Terratec Cinergy 600 TV MK3 153b:1158 +49 Compro VideoMate Gold+ Pal 185b:c200 +50 Pinnacle PCTV 300i DVB-T + PAL 11bd:002d +51 ProVideo PV952 1540:9524 +52 AverMedia AverTV/305 1461:2108 +53 ASUS TV-FM 7135 1043:4845 +54 LifeView FlyTV Platinum FM / Gold 5168:0214, 5168:5214, 1489:0214, 5168:0304 +55 LifeView FlyDVB-T DUO / MSI TV@nywhere Duo 5168:0306, 4E42:0306 +56 Avermedia AVerTV 307 1461:a70a +57 Avermedia AVerTV GO 007 FM 1461:f31f +58 ADS Tech Instant TV (saa7135) 1421:0350, 1421:0351, 1421:0370, 1421:1370 +59 Kworld/Tevion V-Stream Xpert TV PVR7134 +60 LifeView/Typhoon/Genius FlyDVB-T Duo Cardbus 5168:0502, 4e42:0502, 1489:0502 +61 Philips TOUGH DVB-T reference design 1131:2004 +62 Compro VideoMate TV Gold+II +63 Kworld Xpert TV PVR7134 +64 FlyTV mini Asus Digimatrix 1043:0210 +65 V-Stream Studio TV Terminator +66 Yuan TUN-900 (saa7135) +67 Beholder BeholdTV 409 FM 0000:4091 +68 GoTView 7135 PCI 5456:7135 +69 Philips EUROPA V3 reference design 1131:2004 +70 Compro Videomate DVB-T300 185b:c900 +71 Compro Videomate DVB-T200 185b:c901 +72 RTD Embedded Technologies VFG7350 1435:7350 +73 RTD Embedded Technologies VFG7330 1435:7330 +74 LifeView FlyTV Platinum Mini2 14c0:1212 +75 AVerMedia AVerTVHD MCE A180 1461:1044 +76 SKNet MonsterTV Mobile 1131:4ee9 +77 Pinnacle PCTV 40i/50i/110i (saa7133) 11bd:002e +78 ASUSTeK P7131 Dual 1043:4862 +79 Sedna/MuchTV PC TV Cardbus TV/Radio (ITO25 Rev:2B) +80 ASUS Digimatrix TV 1043:0210 +81 Philips Tiger reference design 1131:2018 +82 MSI TV@Anywhere plus 1462:6231, 1462:8624 +83 Terratec Cinergy 250 PCI TV 153b:1160 +84 LifeView FlyDVB Trio 5168:0319 +85 AverTV DVB-T 777 1461:2c05, 1461:2c05 +86 LifeView FlyDVB-T / Genius VideoWonder DVB-T 5168:0301, 1489:0301 +87 ADS Instant TV Duo Cardbus PTV331 0331:1421 +88 Tevion/KWorld DVB-T 220RF 17de:7201 +89 ELSA EX-VISION 700TV 1048:226c +90 Kworld ATSC110/115 17de:7350, 17de:7352 +91 AVerMedia A169 B 1461:7360 +92 AVerMedia A169 B1 1461:6360 +93 Medion 7134 Bridge #2 16be:0005 +94 LifeView FlyDVB-T Hybrid Cardbus/MSI TV @nywhere A/D NB 5168:3306, 5168:3502, 5168:3307, 4e42:3502 +95 LifeView FlyVIDEO3000 (NTSC) 5169:0138 +96 Medion Md8800 Quadro 16be:0007, 16be:0008, 16be:000d +97 LifeView FlyDVB-S /Acorp TV134DS 5168:0300, 4e42:0300 +98 Proteus Pro 2309 0919:2003 +99 AVerMedia TV Hybrid A16AR 1461:2c00 +100 Asus Europa2 OEM 1043:4860 +101 Pinnacle PCTV 310i 11bd:002f +102 Avermedia AVerTV Studio 507 1461:9715 +103 Compro Videomate DVB-T200A +104 Hauppauge WinTV-HVR1110 DVB-T/Hybrid 0070:6700, 0070:6701, 0070:6702, 0070:6703, 0070:6704, 0070:6705 +105 Terratec Cinergy HT PCMCIA 153b:1172 +106 Encore ENLTV 1131:2342, 1131:2341, 3016:2344 +107 Encore ENLTV-FM 1131:230f +108 Terratec Cinergy HT PCI 153b:1175 +109 Philips Tiger - S Reference design +110 Avermedia M102 1461:f31e +111 ASUS P7131 4871 1043:4871 +112 ASUSTeK P7131 Hybrid 1043:4876 +113 Elitegroup ECS TVP3XP FM1246 Tuner Card (PAL,FM) 1019:4cb6 +114 KWorld DVB-T 210 17de:7250 +115 Sabrent PCMCIA TV-PCB05 0919:2003 +116 10MOONS TM300 TV Card 1131:2304 +117 Avermedia Super 007 1461:f01d +118 Beholder BeholdTV 401 0000:4016 +119 Beholder BeholdTV 403 0000:4036 +120 Beholder BeholdTV 403 FM 0000:4037 +121 Beholder BeholdTV 405 0000:4050 +122 Beholder BeholdTV 405 FM 0000:4051 +123 Beholder BeholdTV 407 0000:4070 +124 Beholder BeholdTV 407 FM 0000:4071 +125 Beholder BeholdTV 409 0000:4090 +126 Beholder BeholdTV 505 FM 5ace:5050 +127 Beholder BeholdTV 507 FM / BeholdTV 509 FM 5ace:5070, 5ace:5090 +128 Beholder BeholdTV Columbus TV/FM 0000:5201 +129 Beholder BeholdTV 607 FM 5ace:6070 +130 Beholder BeholdTV M6 5ace:6190 +131 Twinhan Hybrid DTV-DVB 3056 PCI 1822:0022 +132 Genius TVGO AM11MCE +133 NXP Snake DVB-S reference design +134 Medion/Creatix CTX953 Hybrid 16be:0010 +135 MSI TV@nywhere A/D v1.1 1462:8625 +136 AVerMedia Cardbus TV/Radio (E506R) 1461:f436 +137 AVerMedia Hybrid TV/Radio (A16D) 1461:f936 +138 Avermedia M115 1461:a836 +139 Compro VideoMate T750 185b:c900 +140 Avermedia DVB-S Pro A700 1461:a7a1 +141 Avermedia DVB-S Hybrid+FM A700 1461:a7a2 +142 Beholder BeholdTV H6 5ace:6290 +143 Beholder BeholdTV M63 5ace:6191 +144 Beholder BeholdTV M6 Extra 5ace:6193 +145 AVerMedia MiniPCI DVB-T Hybrid M103 1461:f636, 1461:f736 +146 ASUSTeK P7131 Analog +147 Asus Tiger 3in1 1043:4878 +148 Encore ENLTV-FM v5.3 1a7f:2008 +149 Avermedia PCI pure analog (M135A) 1461:f11d +150 Zogis Real Angel 220 +151 ADS Tech Instant HDTV 1421:0380 +152 Asus Tiger Rev:1.00 1043:4857 +153 Kworld Plus TV Analog Lite PCI 17de:7128 +154 Avermedia AVerTV GO 007 FM Plus 1461:f31d +155 Hauppauge WinTV-HVR1150 ATSC/QAM-Hybrid 0070:6706, 0070:6708 +156 Hauppauge WinTV-HVR1120 DVB-T/Hybrid 0070:6707, 0070:6709, 0070:670a +157 Avermedia AVerTV Studio 507UA 1461:a11b +158 AVerMedia Cardbus TV/Radio (E501R) 1461:b7e9 +159 Beholder BeholdTV 505 RDS 0000:505B +160 Beholder BeholdTV 507 RDS 0000:5071 +161 Beholder BeholdTV 507 RDS 0000:507B +162 Beholder BeholdTV 607 FM 5ace:6071 +163 Beholder BeholdTV 609 FM 5ace:6090 +164 Beholder BeholdTV 609 FM 5ace:6091 +165 Beholder BeholdTV 607 RDS 5ace:6072 +166 Beholder BeholdTV 607 RDS 5ace:6073 +167 Beholder BeholdTV 609 RDS 5ace:6092 +168 Beholder BeholdTV 609 RDS 5ace:6093 +169 Compro VideoMate S350/S300 185b:c900 +170 AverMedia AverTV Studio 505 1461:a115 +171 Beholder BeholdTV X7 5ace:7595 +172 RoverMedia TV Link Pro FM 19d1:0138 +173 Zolid Hybrid TV Tuner PCI 1131:2004 +174 Asus Europa Hybrid OEM 1043:4847 +175 Leadtek Winfast DTV1000S 107d:6655 +176 Beholder BeholdTV 505 RDS 0000:5051 +177 Hawell HW-404M7 +178 Beholder BeholdTV H7 5ace:7190 +179 Beholder BeholdTV A7 5ace:7090 +180 Avermedia PCI M733A 1461:4155, 1461:4255 +181 TechoTrend TT-budget T-3000 13c2:2804 +182 Kworld PCI SBTVD/ISDB-T Full-Seg Hybrid 17de:b136 +183 Compro VideoMate Vista M1F 185b:c900 +184 Encore ENLTV-FM 3 1a7f:2108 +185 MagicPro ProHDTV Pro2 DMB-TH/Hybrid 17de:d136 +186 Beholder BeholdTV 501 5ace:5010 +187 Beholder BeholdTV 503 FM 5ace:5030 +188 Sensoray 811/911 6000:0811, 6000:0911 +189 Kworld PC150-U 17de:a134 +190 Asus My Cinema PS3-100 1043:48cd +191 Hawell HW-9004V1 +192 AverMedia AverTV Satellite Hybrid+FM A706 1461:2055 +193 WIS Voyager or compatible 1905:7007 +194 AverMedia AverTV/505 1461:a10a +195 Leadtek Winfast TV2100 FM 107d:6f3a +196 SnaZio* TVPVR PRO 1779:13cf +=========== ======================================================= ================================================================ diff --git a/Documentation/media/v4l-drivers/saa7164-cardlist.rst b/Documentation/media/v4l-drivers/saa7164-cardlist.rst index b937836cd54c..7d17d38df3bc 100644 --- a/Documentation/media/v4l-drivers/saa7164-cardlist.rst +++ b/Documentation/media/v4l-drivers/saa7164-cardlist.rst @@ -1,19 +1,21 @@ -SAA7134 cards list +SAA7164 cards list ================== -.. code-block:: none - - 0 -> Unknown - 1 -> Generic Rev2 - 2 -> Generic Rev3 - 3 -> Hauppauge WinTV-HVR2250 [0070:8880,0070:8810] - 4 -> Hauppauge WinTV-HVR2200 [0070:8980] - 5 -> Hauppauge WinTV-HVR2200 [0070:8900] - 6 -> Hauppauge WinTV-HVR2200 [0070:8901] - 7 -> Hauppauge WinTV-HVR2250 [0070:8891,0070:8851] - 8 -> Hauppauge WinTV-HVR2250 [0070:88A1] - 9 -> Hauppauge WinTV-HVR2200 [0070:8940] - 10 -> Hauppauge WinTV-HVR2200 [0070:8953] - 11 -> Hauppauge WinTV-HVR2255(proto) - 12 -> Hauppauge WinTV-HVR2255 [0070:f111] - 13 -> Hauppauge WinTV-HVR2205 [0070:f123,0070:f120] +=========== ==================================== ==================== +Card number Card name PCI IDs +=========== ==================================== ==================== +0 Unknown +1 Generic Rev2 +2 Generic Rev3 +3 Hauppauge WinTV-HVR2250 0070:8880, 0070:8810 +4 Hauppauge WinTV-HVR2200 0070:8980 +5 Hauppauge WinTV-HVR2200 0070:8900 +6 Hauppauge WinTV-HVR2200 0070:8901 +7 Hauppauge WinTV-HVR2250 0070:8891, 0070:8851 +8 Hauppauge WinTV-HVR2250 0070:88A1 +9 Hauppauge WinTV-HVR2200 0070:8940 +10 Hauppauge WinTV-HVR2200 0070:8953 +11 Hauppauge WinTV-HVR2255(proto) 0070:f111 +12 Hauppauge WinTV-HVR2255 0070:f111 +13 Hauppauge WinTV-HVR2205 0070:f123, 0070:f120 +=========== ==================================== ==================== diff --git a/Documentation/media/v4l-drivers/tm6000-cardlist.rst b/Documentation/media/v4l-drivers/tm6000-cardlist.rst index 2fbd3886b5f0..ae2952683ccf 100644 --- a/Documentation/media/v4l-drivers/tm6000-cardlist.rst +++ b/Documentation/media/v4l-drivers/tm6000-cardlist.rst @@ -1,21 +1,24 @@ TM6000 cards list ================= -.. code-block:: none - - 1 -> Generic tm5600 board (tm5600) [6000:0001] - 2 -> Generic tm6000 board (tm6000) [6000:0001] - 3 -> Generic tm6010 board (tm6010) [6000:0002] - 4 -> 10Moons UT821 (tm5600) [6000:0001] - 5 -> 10Moons UT330 (tm5600) - 6 -> ADSTech Dual TV (tm6000) [06e1:f332] - 7 -> FreeCom and similar (tm6000) [14aa:0620] - 8 -> ADSTech Mini Dual TV (tm6000) [06e1:b339] - 9 -> Hauppauge WinTV HVR-900H/USB2 Stick (tm6010) [2040:6600,2040:6601,2040:6610,2040:6611] - 10 -> Beholder Wander (tm6010) [6000:dec0] - 11 -> Beholder Voyager (tm6010) [6000:dec1] - 12 -> TerraTec Cinergy Hybrid XE/Cinergy Hybrid Stick (tm6010) [0ccd:0086,0ccd:00a5] - 13 -> TwinHan TU501 (tm6010) [13d3:3240,13d3:3241,13d3:3243,13d3:3264] - 14 -> Beholder Wander Lite (tm6010) [6000:dec2] - 15 -> Beholder Voyager Lite (tm6010) [6000:dec3] - +=========== ================================================= ========================================== +Card number Card name USB IDs +=========== ================================================= ========================================== +0 Unknown tm6000 video grabber +1 Generic tm5600 board 6000:0001 +2 Generic tm6000 board +3 Generic tm6010 board 6000:0002 +4 10Moons UT 821 +5 10Moons UT 330 +6 ADSTECH Dual TV USB 06e1:f332 +7 Freecom Hybrid Stick / Moka DVB-T Receiver Dual 14aa:0620 +8 ADSTECH Mini Dual TV USB 06e1:b339 +9 Hauppauge WinTV HVR-900H / WinTV USB2-Stick 2040:6600, 2040:6601, 2040:6610, 2040:6611 +10 Beholder Wander DVB-T/TV/FM USB2.0 6000:dec0 +11 Beholder Voyager TV/FM USB2.0 6000:dec1 +12 Terratec Cinergy Hybrid XE / Cinergy Hybrid-Stick 0ccd:0086, 0ccd:00A5 +13 Twinhan TU501(704D1) 13d3:3240, 13d3:3241, 13d3:3243, 13d3:3264 +14 Beholder Wander Lite DVB-T/TV/FM USB2.0 6000:dec2 +15 Beholder Voyager Lite TV/FM USB2.0 6000:dec3 +16 Terratec Grabster AV 150/250 MX 0ccd:0079 +=========== ================================================= ========================================== diff --git a/Documentation/media/v4l-drivers/tuner-cardlist.rst b/Documentation/media/v4l-drivers/tuner-cardlist.rst index 2f1e1029c04e..276dd90e0c59 100644 --- a/Documentation/media/v4l-drivers/tuner-cardlist.rst +++ b/Documentation/media/v4l-drivers/tuner-cardlist.rst @@ -1,96 +1,98 @@ Tuner cards list ================ -.. code-block:: none - - tuner=0 - Temic PAL (4002 FH5) - tuner=1 - Philips PAL_I (FI1246 and compatibles) - tuner=2 - Philips NTSC (FI1236,FM1236 and compatibles) - tuner=3 - Philips (SECAM+PAL_BG) (FI1216MF, FM1216MF, FR1216MF) - tuner=4 - NoTuner - tuner=5 - Philips PAL_BG (FI1216 and compatibles) - tuner=6 - Temic NTSC (4032 FY5) - tuner=7 - Temic PAL_I (4062 FY5) - tuner=8 - Temic NTSC (4036 FY5) - tuner=9 - Alps HSBH1 - tuner=10 - Alps TSBE1 - tuner=11 - Alps TSBB5 - tuner=12 - Alps TSBE5 - tuner=13 - Alps TSBC5 - tuner=14 - Temic PAL_BG (4006FH5) - tuner=15 - Alps TSCH6 - tuner=16 - Temic PAL_DK (4016 FY5) - tuner=17 - Philips NTSC_M (MK2) - tuner=18 - Temic PAL_I (4066 FY5) - tuner=19 - Temic PAL* auto (4006 FN5) - tuner=20 - Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5) - tuner=21 - Temic NTSC (4039 FR5) - tuner=22 - Temic PAL/SECAM multi (4046 FM5) - tuner=23 - Philips PAL_DK (FI1256 and compatibles) - tuner=24 - Philips PAL/SECAM multi (FQ1216ME) - tuner=25 - LG PAL_I+FM (TAPC-I001D) - tuner=26 - LG PAL_I (TAPC-I701D) - tuner=27 - LG NTSC+FM (TPI8NSR01F) - tuner=28 - LG PAL_BG+FM (TPI8PSB01D) - tuner=29 - LG PAL_BG (TPI8PSB11D) - tuner=30 - Temic PAL* auto + FM (4009 FN5) - tuner=31 - SHARP NTSC_JP (2U5JF5540) - tuner=32 - Samsung PAL TCPM9091PD27 - tuner=33 - MT20xx universal - tuner=34 - Temic PAL_BG (4106 FH5) - tuner=35 - Temic PAL_DK/SECAM_L (4012 FY5) - tuner=36 - Temic NTSC (4136 FY5) - tuner=37 - LG PAL (newer TAPC series) - tuner=38 - Philips PAL/SECAM multi (FM1216ME MK3) - tuner=39 - LG NTSC (newer TAPC series) - tuner=40 - HITACHI V7-J180AT - tuner=41 - Philips PAL_MK (FI1216 MK) - tuner=42 - Philips FCV1236D ATSC/NTSC dual in - tuner=43 - Philips NTSC MK3 (FM1236MK3 or FM1236/F) - tuner=44 - Philips 4 in 1 (ATI TV Wonder Pro/Conexant) - tuner=45 - Microtune 4049 FM5 - tuner=46 - Panasonic VP27s/ENGE4324D - tuner=47 - LG NTSC (TAPE series) - tuner=48 - Tenna TNF 8831 BGFF) - tuner=49 - Microtune 4042 FI5 ATSC/NTSC dual in - tuner=50 - TCL 2002N - tuner=51 - Philips PAL/SECAM_D (FM 1256 I-H3) - tuner=52 - Thomson DTT 7610 (ATSC/NTSC) - tuner=53 - Philips FQ1286 - tuner=54 - Philips/NXP TDA 8290/8295 + 8275/8275A/18271 - tuner=55 - TCL 2002MB - tuner=56 - Philips PAL/SECAM multi (FQ1216AME MK4) - tuner=57 - Philips FQ1236A MK4 - tuner=58 - Ymec TVision TVF-8531MF/8831MF/8731MF - tuner=59 - Ymec TVision TVF-5533MF - tuner=60 - Thomson DTT 761X (ATSC/NTSC) - tuner=61 - Tena TNF9533-D/IF/TNF9533-B/DF - tuner=62 - Philips TEA5767HN FM Radio - tuner=63 - Philips FMD1216ME MK3 Hybrid Tuner - tuner=64 - LG TDVS-H06xF - tuner=65 - Ymec TVF66T5-B/DFF - tuner=66 - LG TALN series - tuner=67 - Philips TD1316 Hybrid Tuner - tuner=68 - Philips TUV1236D ATSC/NTSC dual in - tuner=69 - Tena TNF 5335 and similar models - tuner=70 - Samsung TCPN 2121P30A - tuner=71 - Xceive xc2028/xc3028 tuner - tuner=72 - Thomson FE6600 - tuner=73 - Samsung TCPG 6121P30A - tuner=75 - Philips TEA5761 FM Radio - tuner=76 - Xceive 5000 tuner - tuner=77 - TCL tuner MF02GIP-5N-E - tuner=78 - Philips FMD1216MEX MK3 Hybrid Tuner - tuner=79 - Philips PAL/SECAM multi (FM1216 MK5) - tuner=80 - Philips FQ1216LME MK3 PAL/SECAM w/active loopthrough - tuner=81 - Partsnic (Daewoo) PTI-5NF05 - tuner=82 - Philips CU1216L - tuner=83 - NXP TDA18271 - tuner=84 - Sony BTF-Pxn01Z - tuner=85 - Philips FQ1236 MK5 - tuner=86 - Tena TNF5337 MFD - tuner=87 - Xceive 4000 tuner - tuner=88 - Xceive 5000C tuner - tuner=89 - Sony BTF-PG472Z PAL/SECAM - tuner=90 - Sony BTF-PK467Z NTSC-M-JP - tuner=91 - Sony BTF-PB463Z NTSC-M +============ ===================================================== +Tuner number Card name +============ ===================================================== +0 Temic PAL (4002 FH5) +1 Philips PAL_I (FI1246 and compatibles) +2 Philips NTSC (FI1236,FM1236 and compatibles) +3 Philips (SECAM+PAL_BG) (FI1216MF, FM1216MF, FR1216MF) +4 NoTuner +5 Philips PAL_BG (FI1216 and compatibles) +6 Temic NTSC (4032 FY5) +7 Temic PAL_I (4062 FY5) +8 Temic NTSC (4036 FY5) +9 Alps HSBH1 +10 Alps TSBE1 +11 Alps TSBB5 +12 Alps TSBE5 +13 Alps TSBC5 +14 Temic PAL_BG (4006FH5) +15 Alps TSCH6 +16 Temic PAL_DK (4016 FY5) +17 Philips NTSC_M (MK2) +18 Temic PAL_I (4066 FY5) +19 Temic PAL* auto (4006 FN5) +20 Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5) +21 Temic NTSC (4039 FR5) +22 Temic PAL/SECAM multi (4046 FM5) +23 Philips PAL_DK (FI1256 and compatibles) +24 Philips PAL/SECAM multi (FQ1216ME) +25 LG PAL_I+FM (TAPC-I001D) +26 LG PAL_I (TAPC-I701D) +27 LG NTSC+FM (TPI8NSR01F) +28 LG PAL_BG+FM (TPI8PSB01D) +29 LG PAL_BG (TPI8PSB11D) +30 Temic PAL* auto + FM (4009 FN5) +31 SHARP NTSC_JP (2U5JF5540) +32 Samsung PAL TCPM9091PD27 +33 MT20xx universal +34 Temic PAL_BG (4106 FH5) +35 Temic PAL_DK/SECAM_L (4012 FY5) +36 Temic NTSC (4136 FY5) +37 LG PAL (newer TAPC series) +38 Philips PAL/SECAM multi (FM1216ME MK3) +39 LG NTSC (newer TAPC series) +40 HITACHI V7-J180AT +41 Philips PAL_MK (FI1216 MK) +42 Philips FCV1236D ATSC/NTSC dual in +43 Philips NTSC MK3 (FM1236MK3 or FM1236/F) +44 Philips 4 in 1 (ATI TV Wonder Pro/Conexant) +45 Microtune 4049 FM5 +46 Panasonic VP27s/ENGE4324D +47 LG NTSC (TAPE series) +48 Tenna TNF 8831 BGFF) +49 Microtune 4042 FI5 ATSC/NTSC dual in +50 TCL 2002N +51 Philips PAL/SECAM_D (FM 1256 I-H3) +52 Thomson DTT 7610 (ATSC/NTSC) +53 Philips FQ1286 +54 Philips/NXP TDA 8290/8295 + 8275/8275A/18271 +55 TCL 2002MB +56 Philips PAL/SECAM multi (FQ1216AME MK4) +57 Philips FQ1236A MK4 +58 Ymec TVision TVF-8531MF/8831MF/8731MF +59 Ymec TVision TVF-5533MF +60 Thomson DTT 761X (ATSC/NTSC) +61 Tena TNF9533-D/IF/TNF9533-B/DF +62 Philips TEA5767HN FM Radio +63 Philips FMD1216ME MK3 Hybrid Tuner +64 LG TDVS-H06xF +65 Ymec TVF66T5-B/DFF +66 LG TALN series +67 Philips TD1316 Hybrid Tuner +68 Philips TUV1236D ATSC/NTSC dual in +69 Tena TNF 5335 and similar models +70 Samsung TCPN 2121P30A +71 Xceive xc2028/xc3028 tuner +72 Thomson FE6600 +73 Samsung TCPG 6121P30A +75 Philips TEA5761 FM Radio +76 Xceive 5000 tuner +77 TCL tuner MF02GIP-5N-E +78 Philips FMD1216MEX MK3 Hybrid Tuner +79 Philips PAL/SECAM multi (FM1216 MK5) +80 Philips FQ1216LME MK3 PAL/SECAM w/active loopthrough +81 Partsnic (Daewoo) PTI-5NF05 +82 Philips CU1216L +83 NXP TDA18271 +84 Sony BTF-Pxn01Z +85 Philips FQ1236 MK5 +86 Tena TNF5337 MFD +87 Xceive 4000 tuner +88 Xceive 5000C tuner +89 Sony BTF-PG472Z PAL/SECAM +90 Sony BTF-PK467Z NTSC-M-JP +91 Sony BTF-PB463Z NTSC-M +============ ===================================================== diff --git a/Documentation/media/v4l-drivers/usbvision-cardlist.rst b/Documentation/media/v4l-drivers/usbvision-cardlist.rst index 3d8be9cb1b5a..44d53dff0984 100644 --- a/Documentation/media/v4l-drivers/usbvision-cardlist.rst +++ b/Documentation/media/v4l-drivers/usbvision-cardlist.rst @@ -1,72 +1,74 @@ -Usbvision cards list +USBvision cards list ==================== -.. code-block:: none - - 0 -> Xanboo [0a6f:0400] - 1 -> Belkin USB VideoBus II Adapter [050d:0106] - 2 -> Belkin Components USB VideoBus [050d:0207] - 3 -> Belkin USB VideoBus II [050d:0208] - 4 -> echoFX InterView Lite [0571:0002] - 5 -> USBGear USBG-V1 resp. HAMA USB [0573:0003] - 6 -> D-Link V100 [0573:0400] - 7 -> X10 USB Camera [0573:2000] - 8 -> Hauppauge WinTV USB Live (PAL B/G) [0573:2d00] - 9 -> Hauppauge WinTV USB Live Pro (NTSC M/N) [0573:2d01] - 10 -> Zoran Co. PMD (Nogatech) AV-grabber Manhattan [0573:2101] - 11 -> Nogatech USB-TV (NTSC) FM [0573:4100] - 12 -> PNY USB-TV (NTSC) FM [0573:4110] - 13 -> PixelView PlayTv-USB PRO (PAL) FM [0573:4450] - 14 -> ZTV ZT-721 2.4GHz USB A/V Receiver [0573:4550] - 15 -> Hauppauge WinTV USB (NTSC M/N) [0573:4d00] - 16 -> Hauppauge WinTV USB (PAL B/G) [0573:4d01] - 17 -> Hauppauge WinTV USB (PAL I) [0573:4d02] - 18 -> Hauppauge WinTV USB (PAL/SECAM L) [0573:4d03] - 19 -> Hauppauge WinTV USB (PAL D/K) [0573:4d04] - 20 -> Hauppauge WinTV USB (NTSC FM) [0573:4d10] - 21 -> Hauppauge WinTV USB (PAL B/G FM) [0573:4d11] - 22 -> Hauppauge WinTV USB (PAL I FM) [0573:4d12] - 23 -> Hauppauge WinTV USB (PAL D/K FM) [0573:4d14] - 24 -> Hauppauge WinTV USB Pro (NTSC M/N) [0573:4d2a] - 25 -> Hauppauge WinTV USB Pro (NTSC M/N) V2 [0573:4d2b] - 26 -> Hauppauge WinTV USB Pro (PAL/SECAM B/G/I/D/K/L) [0573:4d2c] - 27 -> Hauppauge WinTV USB Pro (NTSC M/N) V3 [0573:4d20] - 28 -> Hauppauge WinTV USB Pro (PAL B/G) [0573:4d21] - 29 -> Hauppauge WinTV USB Pro (PAL I) [0573:4d22] - 30 -> Hauppauge WinTV USB Pro (PAL/SECAM L) [0573:4d23] - 31 -> Hauppauge WinTV USB Pro (PAL D/K) [0573:4d24] - 32 -> Hauppauge WinTV USB Pro (PAL/SECAM BGDK/I/L) [0573:4d25] - 33 -> Hauppauge WinTV USB Pro (PAL/SECAM BGDK/I/L) V2 [0573:4d26] - 34 -> Hauppauge WinTV USB Pro (PAL B/G) V2 [0573:4d27] - 35 -> Hauppauge WinTV USB Pro (PAL B/G,D/K) [0573:4d28] - 36 -> Hauppauge WinTV USB Pro (PAL I,D/K) [0573:4d29] - 37 -> Hauppauge WinTV USB Pro (NTSC M/N FM) [0573:4d30] - 38 -> Hauppauge WinTV USB Pro (PAL B/G FM) [0573:4d31] - 39 -> Hauppauge WinTV USB Pro (PAL I FM) [0573:4d32] - 40 -> Hauppauge WinTV USB Pro (PAL D/K FM) [0573:4d34] - 41 -> Hauppauge WinTV USB Pro (Temic PAL/SECAM B/G/I/D/K/L FM) [0573:4d35] - 42 -> Hauppauge WinTV USB Pro (Temic PAL B/G FM) [0573:4d36] - 43 -> Hauppauge WinTV USB Pro (PAL/SECAM B/G/I/D/K/L FM) [0573:4d37] - 44 -> Hauppauge WinTV USB Pro (NTSC M/N FM) V2 [0573:4d38] - 45 -> Camtel Technology USB TV Genie Pro FM Model TVB330 [0768:0006] - 46 -> Digital Video Creator I [07d0:0001] - 47 -> Global Village GV-007 (NTSC) [07d0:0002] - 48 -> Dazzle Fusion Model DVC-50 Rev 1 (NTSC) [07d0:0003] - 49 -> Dazzle Fusion Model DVC-80 Rev 1 (PAL) [07d0:0004] - 50 -> Dazzle Fusion Model DVC-90 Rev 1 (SECAM) [07d0:0005] - 51 -> Eskape Labs MyTV2Go [07f8:9104] - 52 -> Pinnacle Studio PCTV USB (PAL) [2304:010d] - 53 -> Pinnacle Studio PCTV USB (SECAM) [2304:0109] - 54 -> Pinnacle Studio PCTV USB (PAL) FM [2304:0110] - 55 -> Miro PCTV USB [2304:0111] - 56 -> Pinnacle Studio PCTV USB (NTSC) FM [2304:0112] - 57 -> Pinnacle Studio PCTV USB (PAL) FM V2 [2304:0210] - 58 -> Pinnacle Studio PCTV USB (NTSC) FM V2 [2304:0212] - 59 -> Pinnacle Studio PCTV USB (PAL) FM V3 [2304:0214] - 60 -> Pinnacle Studio Linx Video input cable (NTSC) [2304:0300] - 61 -> Pinnacle Studio Linx Video input cable (PAL) [2304:0301] - 62 -> Pinnacle PCTV Bungee USB (PAL) FM [2304:0419] - 63 -> Hauppauge WinTv-USB [2400:4200] - 64 -> Pinnacle Studio PCTV USB (NTSC) FM V3 [2304:0113] - 65 -> Nogatech USB MicroCam NTSC (NV3000N) [0573:3000] - 66 -> Nogatech USB MicroCam PAL (NV3001P) [0573:3001] +=========== ======================================================== ========= +Card number Card name USB IDs +=========== ======================================================== ========= +0 Xanboo 0a6f:0400 +1 Belkin USB VideoBus II Adapter 050d:0106 +2 Belkin Components USB VideoBus 050d:0207 +3 Belkin USB VideoBus II 050d:0208 +4 echoFX InterView Lite 0571:0002 +5 USBGear USBG-V1 resp. HAMA USB 0573:0003 +6 D-Link V100 0573:0400 +7 X10 USB Camera 0573:2000 +8 Hauppauge WinTV USB Live (PAL B/G) 0573:2d00 +9 Hauppauge WinTV USB Live Pro (NTSC M/N) 0573:2d01 +10 Zoran Co. PMD (Nogatech) AV-grabber Manhattan 0573:2101 +11 Nogatech USB-TV (NTSC) FM 0573:4100 +12 PNY USB-TV (NTSC) FM 0573:4110 +13 PixelView PlayTv-USB PRO (PAL) FM 0573:4450 +14 ZTV ZT-721 2.4GHz USB A/V Receiver 0573:4550 +15 Hauppauge WinTV USB (NTSC M/N) 0573:4d00 +16 Hauppauge WinTV USB (PAL B/G) 0573:4d01 +17 Hauppauge WinTV USB (PAL I) 0573:4d02 +18 Hauppauge WinTV USB (PAL/SECAM L) 0573:4d03 +19 Hauppauge WinTV USB (PAL D/K) 0573:4d04 +20 Hauppauge WinTV USB (NTSC FM) 0573:4d10 +21 Hauppauge WinTV USB (PAL B/G FM) 0573:4d11 +22 Hauppauge WinTV USB (PAL I FM) 0573:4d12 +23 Hauppauge WinTV USB (PAL D/K FM) 0573:4d14 +24 Hauppauge WinTV USB Pro (NTSC M/N) 0573:4d2a +25 Hauppauge WinTV USB Pro (NTSC M/N) V2 0573:4d2b +26 Hauppauge WinTV USB Pro (PAL/SECAM B/G/I/D/K/L) 0573:4d2c +27 Hauppauge WinTV USB Pro (NTSC M/N) V3 0573:4d20 +28 Hauppauge WinTV USB Pro (PAL B/G) 0573:4d21 +29 Hauppauge WinTV USB Pro (PAL I) 0573:4d22 +30 Hauppauge WinTV USB Pro (PAL/SECAM L) 0573:4d23 +31 Hauppauge WinTV USB Pro (PAL D/K) 0573:4d24 +32 Hauppauge WinTV USB Pro (PAL/SECAM BGDK/I/L) 0573:4d25 +33 Hauppauge WinTV USB Pro (PAL/SECAM BGDK/I/L) V2 0573:4d26 +34 Hauppauge WinTV USB Pro (PAL B/G) V2 0573:4d27 +35 Hauppauge WinTV USB Pro (PAL B/G,D/K) 0573:4d28 +36 Hauppauge WinTV USB Pro (PAL I,D/K) 0573:4d29 +37 Hauppauge WinTV USB Pro (NTSC M/N FM) 0573:4d30 +38 Hauppauge WinTV USB Pro (PAL B/G FM) 0573:4d31 +39 Hauppauge WinTV USB Pro (PAL I FM) 0573:4d32 +40 Hauppauge WinTV USB Pro (PAL D/K FM) 0573:4d34 +41 Hauppauge WinTV USB Pro (Temic PAL/SECAM B/G/I/D/K/L FM) 0573:4d35 +42 Hauppauge WinTV USB Pro (Temic PAL B/G FM) 0573:4d36 +43 Hauppauge WinTV USB Pro (PAL/SECAM B/G/I/D/K/L FM) 0573:4d37 +44 Hauppauge WinTV USB Pro (NTSC M/N FM) V2 0573:4d38 +45 Camtel Technology USB TV Genie Pro FM Model TVB330 0768:0006 +46 Digital Video Creator I 07d0:0001 +47 Global Village GV-007 (NTSC) 07d0:0002 +48 Dazzle Fusion Model DVC-50 Rev 1 (NTSC) 07d0:0003 +49 Dazzle Fusion Model DVC-80 Rev 1 (PAL) 07d0:0004 +50 Dazzle Fusion Model DVC-90 Rev 1 (SECAM) 07d0:0005 +51 Eskape Labs MyTV2Go 07f8:9104 +52 Pinnacle Studio PCTV USB (PAL) 2304:010d +53 Pinnacle Studio PCTV USB (SECAM) 2304:0109 +54 Pinnacle Studio PCTV USB (PAL) FM 2304:0110 +55 Miro PCTV USB 2304:0111 +56 Pinnacle Studio PCTV USB (NTSC) FM 2304:0112 +57 Pinnacle Studio PCTV USB (PAL) FM V2 2304:0210 +58 Pinnacle Studio PCTV USB (NTSC) FM V2 2304:0212 +59 Pinnacle Studio PCTV USB (PAL) FM V3 2304:0214 +60 Pinnacle Studio Linx Video input cable (NTSC) 2304:0300 +61 Pinnacle Studio Linx Video input cable (PAL) 2304:0301 +62 Pinnacle PCTV Bungee USB (PAL) FM 2304:0419 +63 Hauppauge WinTv-USB 2400:4200 +64 Pinnacle Studio PCTV USB (NTSC) FM V3 2304:0113 +65 Nogatech USB MicroCam NTSC (NV3000N) 0573:3000 +66 Nogatech USB MicroCam PAL (NV3001P) 0573:3001 +=========== ======================================================== ========= diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions index 1d3f27d922b2..e11a0d0a8931 100644 --- a/Documentation/media/videodev2.h.rst.exceptions +++ b/Documentation/media/videodev2.h.rst.exceptions @@ -87,6 +87,10 @@ replace symbol V4L2_YCBCR_ENC_XV601 :c:type:`v4l2_ycbcr_encoding` replace symbol V4L2_YCBCR_ENC_XV709 :c:type:`v4l2_ycbcr_encoding` replace symbol V4L2_YCBCR_ENC_SMPTE240M :c:type:`v4l2_ycbcr_encoding` +# Documented enum v4l2_hsv_encoding +replace symbol V4L2_HSV_ENC_180 :c:type:`v4l2_hsv_encoding` +replace symbol V4L2_HSV_ENC_256 :c:type:`v4l2_hsv_encoding` + # Documented enum v4l2_quantization replace symbol V4L2_QUANTIZATION_DEFAULT :c:type:`v4l2_quantization` replace symbol V4L2_QUANTIZATION_FULL_RANGE :c:type:`v4l2_quantization` @@ -276,6 +280,9 @@ replace define V4L2_DV_FL_REDUCED_FPS dv-bt-standards replace define V4L2_DV_FL_HALF_LINE dv-bt-standards replace define V4L2_DV_FL_IS_CE_VIDEO dv-bt-standards replace define V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE dv-bt-standards +replace define V4L2_DV_FL_HAS_PICTURE_ASPECT dv-bt-standards +replace define V4L2_DV_FL_HAS_CEA861_VIC dv-bt-standards +replace define V4L2_DV_FL_HAS_HDMI_VIC dv-bt-standards replace define V4L2_DV_BT_656_1120 dv-timing-types diff --git a/Documentation/networking/mpls-sysctl.txt b/Documentation/networking/mpls-sysctl.txt index 9ed15f86c17c..15d8d16934fd 100644 --- a/Documentation/networking/mpls-sysctl.txt +++ b/Documentation/networking/mpls-sysctl.txt @@ -5,8 +5,8 @@ platform_labels - INTEGER possible to configure forwarding for label values equal to or greater than the number of platform labels. - A dense utliziation of the entries in the platform label table - is possible and expected aas the platform labels are locally + A dense utilization of the entries in the platform label table + is possible and expected as the platform labels are locally allocated. If the number of platform label table entries is set to 0 no diff --git a/Documentation/scsi/g_NCR5380.txt b/Documentation/scsi/g_NCR5380.txt index e2c187947e58..37b1967a00a9 100644 --- a/Documentation/scsi/g_NCR5380.txt +++ b/Documentation/scsi/g_NCR5380.txt @@ -6,17 +6,15 @@ NCR53c400 extensions (c) 1994,1995,1996 Kevin Lentin This file documents the NCR53c400 extensions by Kevin Lentin and some enhancements to the NCR5380 core. -This driver supports both NCR5380 and NCR53c400 cards in port or memory -mapped modes. Currently this driver can only support one of those mapping -modes at a time but it does support both of these chips at the same time. -The next release of this driver will support port & memory mapped cards at -the same time. It should be able to handle multiple different cards in the -same machine. +This driver supports NCR5380 and NCR53c400 and compatible cards in port or +memory mapped modes. -The drivers/scsi/Makefile has an override in it for the most common -NCR53c400 card, the Trantor T130B in its default configuration: - Port: 0x350 - IRQ : 5 +Use of an interrupt is recommended, if supported by the board, as this will +allow targets to disconnect and thereby improve SCSI bus utilization. + +If the irq parameter is 254 or is omitted entirely, the driver will probe +for the correct IRQ line automatically. If the irq parameter is 0 or 255 +then no IRQ will be used. The NCR53c400 does not support DMA but it does have Pseudo-DMA which is supported by the driver. @@ -47,22 +45,24 @@ These old-style parameters can support only one card: dtc_3181e=1 to set up for a Domex Technology Corp 3181E board hp_c2502=1 to set up for a Hewlett Packard C2502 board -e.g. -OLD: modprobe g_NCR5380 ncr_irq=5 ncr_addr=0x350 ncr_5380=1 -NEW: modprobe g_NCR5380 irq=5 base=0x350 card=0 - for a port mapped NCR5380 board or +E.g. Trantor T130B in its default configuration: +modprobe g_NCR5380 irq=5 base=0x350 card=1 +or alternatively, using the old syntax, +modprobe g_NCR5380 ncr_irq=5 ncr_addr=0x350 ncr_53c400=1 -OLD: modprobe g_NCR5380 ncr_irq=255 ncr_addr=0xc8000 ncr_53c400=1 -NEW: modprobe g_NCR5380 irq=255 base=0xc8000 card=1 - for a memory mapped NCR53C400 board with interrupts disabled or +E.g. a port mapped NCR5380 board, driver to probe for IRQ: +modprobe g_NCR5380 base=0x350 card=0 +or alternatively, +modprobe g_NCR5380 ncr_addr=0x350 ncr_5380=1 -NEW: modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4 - for two cards: DTC3181 (in non-PnP mode) at 0x240 with no IRQ - and HP C2502 at 0x300 with IRQ 7 - -(255 should be specified for no or DMA interrupt, 254 to autoprobe for an - IRQ line if overridden on the command line.) +E.g. a memory mapped NCR53C400 board with no IRQ: +modprobe g_NCR5380 irq=255 base=0xc8000 card=1 +or alternatively, +modprobe g_NCR5380 ncr_irq=255 ncr_addr=0xc8000 ncr_53c400=1 +E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ +and HP C2502 at 0x300 with IRQ 7: +modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4 Kevin Lentin K.Lentin@cs.monash.edu.au diff --git a/Documentation/security/keys-trusted-encrypted.txt b/Documentation/security/keys-trusted-encrypted.txt index 324ddf5223b3..b20a993a32af 100644 --- a/Documentation/security/keys-trusted-encrypted.txt +++ b/Documentation/security/keys-trusted-encrypted.txt @@ -32,8 +32,6 @@ Usage: (40 ascii zeros) blobauth= ascii hex auth for sealed data default 0x00... (40 ascii zeros) - blobauth= ascii hex auth for sealed data default 0x00... - (40 ascii zeros) pcrinfo= ascii hex of PCR_INFO or PCR_INFO_LONG (no default) pcrlock= pcr number to be extended to "lock" blob migratable= 0|1 indicating permission to reseal to new PCR values, diff --git a/Documentation/sphinx/rstFlatTable.py b/Documentation/sphinx/rstFlatTable.py index 55f275793028..25feb0d35e7a 100755 --- a/Documentation/sphinx/rstFlatTable.py +++ b/Documentation/sphinx/rstFlatTable.py @@ -157,6 +157,11 @@ class ListTableBuilder(object): def buildTableNode(self): colwidths = self.directive.get_column_widths(self.max_cols) + if isinstance(colwidths, tuple): + # Since docutils 0.13, get_column_widths returns a (widths, + # colwidths) tuple, where widths is a string (i.e. 'auto'). + # See https://sourceforge.net/p/docutils/patches/120/. + colwidths = colwidths[1] stub_columns = self.directive.options.get('stub-columns', 0) header_rows = self.directive.options.get('header-rows', 0) diff --git a/Documentation/trace/events.txt b/Documentation/trace/events.txt index 08d74d75150d..2cc08d4a326e 100644 --- a/Documentation/trace/events.txt +++ b/Documentation/trace/events.txt @@ -189,16 +189,13 @@ And for string fields they are: ==, !=, ~ -The glob (~) only accepts a wild card character (*) at the start and or -end of the string. For example: +The glob (~) accepts a wild card character (*,?) and character classes +([). For example: prev_comm ~ "*sh" prev_comm ~ "sh*" prev_comm ~ "*sh*" - -But does not allow for it to be within the string: - - prev_comm ~ "ba*sh" <-- is invalid + prev_comm ~ "ba*sh" 5.2 Setting filters ------------------- diff --git a/Documentation/trace/ftrace.txt b/Documentation/trace/ftrace.txt index 5596e2d71d6d..006f47c7d913 100644 --- a/Documentation/trace/ftrace.txt +++ b/Documentation/trace/ftrace.txt @@ -416,6 +416,12 @@ of ftrace. Here is a list of some of the key files: trace_fd = open("trace_marker", WR_ONLY); + trace_marker_raw: + + This is similar to trace_marker above, but is meant for for binary data + to be written to it, where a tool can be used to parse the data + from trace_pipe_raw. + uprobe_events: Add dynamic tracepoints in programs. @@ -2238,16 +2244,13 @@ hrtimer_interrupt sys_nanosleep -Perhaps this is not enough. The filters also allow simple wild -cards. Only the following are currently available +Perhaps this is not enough. The filters also allow glob(7) matching. * - will match functions that begin with * - will match functions that end with ** - will match functions that have in it - -These are the only wild cards which are supported. - - * will not work. + * - will match functions that begin with + and end with Note: It is better to use quotes to enclose the wild cards, otherwise the shell may expand the parameters into names diff --git a/Documentation/translations/zh_CN/sparse.txt b/Documentation/translations/zh_CN/sparse.txt index cc144e581515..e41dc940e162 100644 --- a/Documentation/translations/zh_CN/sparse.txt +++ b/Documentation/translations/zh_CN/sparse.txt @@ -92,9 +92,4 @@ DaveJ 把每小时自动生成的 git 源码树 tar 包放在以下地址： 如果你已经编译了内核，用后一种方式可以很快地检查整个源码树。 make 的可选变量 CHECKFLAGS 可以用来向 sparse 工具传递参数。编译系统会自 -动向 sparse 工具传递 -Wbitwise 参数。你可以定义 __CHECK_ENDIAN__ 来进行 -大小尾检查。 - - make C=2 CHECKFLAGS="-D__CHECK_ENDIAN__" - -这些检查默认都是被关闭的，因为他们通常会产生大量的警告。 +动向 sparse 工具传递 -Wbitwise 参数。 diff --git a/Documentation/unaligned-memory-access.txt b/Documentation/unaligned-memory-access.txt index a445da098bc6..3f76c0c37920 100644 --- a/Documentation/unaligned-memory-access.txt +++ b/Documentation/unaligned-memory-access.txt @@ -151,7 +151,7 @@ bool ether_addr_equal(const u8 *addr1, const u8 *addr2) #else const u16 *a = (const u16 *)addr1; const u16 *b = (const u16 *)addr2; - return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0; + return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0; #endif } diff --git a/Documentation/vfio-mediated-device.txt b/Documentation/vfio-mediated-device.txt index b38afec35edc..d226c7a5ba8b 100644 --- a/Documentation/vfio-mediated-device.txt +++ b/Documentation/vfio-mediated-device.txt @@ -127,22 +127,22 @@ the VFIO when devices are unbound from the driver. Physical Device Driver Interface -------------------------------- -The physical device driver interface provides the parent_ops[3] structure to -define the APIs to manage work in the mediated core driver that is related to -the physical device. +The physical device driver interface provides the mdev_parent_ops[3] structure +to define the APIs to manage work in the mediated core driver that is related +to the physical device. -The structures in the parent_ops structure are as follows: +The structures in the mdev_parent_ops structure are as follows: * dev_attr_groups: attributes of the parent device * mdev_attr_groups: attributes of the mediated device * supported_config: attributes to define supported configurations -The functions in the parent_ops structure are as follows: +The functions in the mdev_parent_ops structure are as follows: * create: allocate basic resources in a driver for a mediated device * remove: free resources in a driver when a mediated device is destroyed -The callbacks in the parent_ops structure are as follows: +The callbacks in the mdev_parent_ops structure are as follows: * open: open callback of mediated device * close: close callback of mediated device @@ -151,14 +151,14 @@ The callbacks in the parent_ops structure are as follows: * write: write emulation callback * mmap: mmap emulation callback -A driver should use the parent_ops structure in the function call to register -itself with the mdev core driver: +A driver should use the mdev_parent_ops structure in the function call to +register itself with the mdev core driver: extern int mdev_register_device(struct device *dev, - const struct parent_ops *ops); + const struct mdev_parent_ops *ops); -However, the parent_ops structure is not required in the function call that a -driver should use to unregister itself with the mdev core driver: +However, the mdev_parent_ops structure is not required in the function call +that a driver should use to unregister itself with the mdev core driver: extern void mdev_unregister_device(struct device *dev); @@ -223,6 +223,9 @@ Directories and files under the sysfs for Each Physical Device sprintf(buf, "%s-%s", dev_driver_string(parent->dev), group->name); + (or using mdev_parent_dev(mdev) to arrive at the parent device outside + of the core mdev code) + * device_api This attribute should show which device API is being created, for example, @@ -394,5 +397,5 @@ References [1] See Documentation/vfio.txt for more information on VFIO. [2] struct mdev_driver in include/linux/mdev.h -[3] struct parent_ops in include/linux/mdev.h +[3] struct mdev_parent_ops in include/linux/mdev.h [4] struct vfio_iommu_driver_ops in include/linux/vfio.h diff --git a/Documentation/virtual/kvm/locking.txt b/Documentation/virtual/kvm/locking.txt index e5dd9f4d6100..fd013bf4115b 100644 --- a/Documentation/virtual/kvm/locking.txt +++ b/Documentation/virtual/kvm/locking.txt @@ -13,8 +13,12 @@ The acquisition orders for mutexes are as follows: - kvm->slots_lock is taken outside kvm->irq_lock, though acquiring them together is quite rare. -For spinlocks, kvm_lock is taken outside kvm->mmu_lock. Everything -else is a leaf: no other lock is taken inside the critical sections. +On x86, vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock. + +For spinlocks, kvm_lock is taken outside kvm->mmu_lock. + +Everything else is a leaf: no other lock is taken inside the critical +sections. 2: Exception ------------ diff --git a/Documentation/vm/page_frags b/Documentation/vm/page_frags new file mode 100644 index 000000000000..a6714565dbf9 --- /dev/null +++ b/Documentation/vm/page_frags @@ -0,0 +1,42 @@ +Page fragments +-------------- + +A page fragment is an arbitrary-length arbitrary-offset area of memory +which resides within a 0 or higher order compound page. Multiple +fragments within that page are individually refcounted, in the page's +reference counter. + +The page_frag functions, page_frag_alloc and page_frag_free, provide a +simple allocation framework for page fragments. This is used by the +network stack and network device drivers to provide a backing region of +memory for use as either an sk_buff->head, or to be used in the "frags" +portion of skb_shared_info. + +In order to make use of the page fragment APIs a backing page fragment +cache is needed. This provides a central point for the fragment allocation +and tracks allows multiple calls to make use of a cached page. The +advantage to doing this is that multiple calls to get_page can be avoided +which can be expensive at allocation time. However due to the nature of +this caching it is required that any calls to the cache be protected by +either a per-cpu limitation, or a per-cpu limitation and forcing interrupts +to be disabled when executing the fragment allocation. + +The network stack uses two separate caches per CPU to handle fragment +allocation. The netdev_alloc_cache is used by callers making use of the +__netdev_alloc_frag and __netdev_alloc_skb calls. The napi_alloc_cache is +used by callers of the __napi_alloc_frag and __napi_alloc_skb calls. The +main difference between these two calls is the context in which they may be +called. The "netdev" prefixed functions are usable in any context as these +functions will disable interrupts, while the "napi" prefixed functions are +only usable within the softirq context. + +Many network device drivers use a similar methodology for allocating page +fragments, but the page fragments are cached at the ring or descriptor +level. In order to enable these cases it is necessary to provide a generic +way of tearing down a page cache. For this reason __page_frag_cache_drain +was implemented. It allows for freeing multiple references from a single +page via a single call. The advantage to doing this is that it allows for +cleaning up the multiple references that were added to a page in order to +avoid calling get_page per allocation. + +Alexander Duyck, Nov 29, 2016. diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt new file mode 100644 index 000000000000..d918d268cd72 --- /dev/null +++ b/Documentation/x86/intel_rdt_ui.txt @@ -0,0 +1,214 @@ +User Interface for Resource Allocation in Intel Resource Director Technology + +Copyright (C) 2016 Intel Corporation + +Fenghua Yu +Tony Luck + +This feature is enabled by the CONFIG_INTEL_RDT_A Kconfig and the +X86 /proc/cpuinfo flag bits "rdt", "cat_l3" and "cdp_l3". + +To use the feature mount the file system: + + # mount -t resctrl resctrl [-o cdp] /sys/fs/resctrl + +mount options are: + +"cdp": Enable code/data prioritization in L3 cache allocations. + + +Info directory +-------------- + +The 'info' directory contains information about the enabled +resources. Each resource has its own subdirectory. The subdirectory +names reflect the resource names. Each subdirectory contains the +following files: + +"num_closids": The number of CLOSIDs which are valid for this + resource. The kernel uses the smallest number of + CLOSIDs of all enabled resources as limit. + +"cbm_mask": The bitmask which is valid for this resource. This + mask is equivalent to 100%. + +"min_cbm_bits": The minimum number of consecutive bits which must be + set when writing a mask. + + +Resource groups +--------------- +Resource groups are represented as directories in the resctrl file +system. The default group is the root directory. Other groups may be +created as desired by the system administrator using the "mkdir(1)" +command, and removed using "rmdir(1)". + +There are three files associated with each group: + +"tasks": A list of tasks that belongs to this group. Tasks can be + added to a group by writing the task ID to the "tasks" file + (which will automatically remove them from the previous + group to which they belonged). New tasks created by fork(2) + and clone(2) are added to the same group as their parent. + If a pid is not in any sub partition, it is in root partition + (i.e. default partition). + +"cpus": A bitmask of logical CPUs assigned to this group. Writing + a new mask can add/remove CPUs from this group. Added CPUs + are removed from their previous group. Removed ones are + given to the default (root) group. You cannot remove CPUs + from the default group. + +"schemata": A list of all the resources available to this group. + Each resource has its own line and format - see below for + details. + +When a task is running the following rules define which resources +are available to it: + +1) If the task is a member of a non-default group, then the schemata +for that group is used. + +2) Else if the task belongs to the default group, but is running on a +CPU that is assigned to some specific group, then the schemata for +the CPU's group is used. + +3) Otherwise the schemata for the default group is used. + + +Schemata files - general concepts +--------------------------------- +Each line in the file describes one resource. The line starts with +the name of the resource, followed by specific values to be applied +in each of the instances of that resource on the system. + +Cache IDs +--------- +On current generation systems there is one L3 cache per socket and L2 +caches are generally just shared by the hyperthreads on a core, but this +isn't an architectural requirement. We could have multiple separate L3 +caches on a socket, multiple cores could share an L2 cache. So instead +of using "socket" or "core" to define the set of logical cpus sharing +a resource we use a "Cache ID". At a given cache level this will be a +unique number across the whole system (but it isn't guaranteed to be a +contiguous sequence, there may be gaps). To find the ID for each logical +CPU look in /sys/devices/system/cpu/cpu*/cache/index*/id + +Cache Bit Masks (CBM) +--------------------- +For cache resources we describe the portion of the cache that is available +for allocation using a bitmask. The maximum value of the mask is defined +by each cpu model (and may be different for different cache levels). It +is found using CPUID, but is also provided in the "info" directory of +the resctrl file system in "info/{resource}/cbm_mask". X86 hardware +requires that these masks have all the '1' bits in a contiguous block. So +0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 +and 0xA are not. On a system with a 20-bit mask each bit represents 5% +of the capacity of the cache. You could partition the cache into four +equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. + + +L3 details (code and data prioritization disabled) +-------------------------------------------------- +With CDP disabled the L3 schemata format is: + + L3:=;=;... + +L3 details (CDP enabled via mount option to resctrl) +---------------------------------------------------- +When CDP is enabled L3 control is split into two separate resources +so you can specify independent masks for code and data like this: + + L3data:=;=;... + L3code:=;=;... + +L2 details +---------- +L2 cache does not support code and data prioritization, so the +schemata format is always: + + L2:=;=;... + +Example 1 +--------- +On a two socket machine (one L3 cache per socket) with just four bits +for cache bit masks + +# mount -t resctrl resctrl /sys/fs/resctrl +# cd /sys/fs/resctrl +# mkdir p0 p1 +# echo "L3:0=3;1=c" > /sys/fs/resctrl/p0/schemata +# echo "L3:0=3;1=3" > /sys/fs/resctrl/p1/schemata + +The default resource group is unmodified, so we have access to all parts +of all caches (its schemata file reads "L3:0=f;1=f"). + +Tasks that are under the control of group "p0" may only allocate from the +"lower" 50% on cache ID 0, and the "upper" 50% of cache ID 1. +Tasks in group "p1" use the "lower" 50% of cache on both sockets. + +Example 2 +--------- +Again two sockets, but this time with a more realistic 20-bit mask. + +Two real time tasks pid=1234 running on processor 0 and pid=5678 running on +processor 1 on socket 0 on a 2-socket and dual core machine. To avoid noisy +neighbors, each of the two real-time tasks exclusively occupies one quarter +of L3 cache on socket 0. + +# mount -t resctrl resctrl /sys/fs/resctrl +# cd /sys/fs/resctrl + +First we reset the schemata for the default group so that the "upper" +50% of the L3 cache on socket 0 cannot be used by ordinary tasks: + +# echo "L3:0=3ff;1=fffff" > schemata + +Next we make a resource group for our first real time task and give +it access to the "top" 25% of the cache on socket 0. + +# mkdir p0 +# echo "L3:0=f8000;1=fffff" > p0/schemata + +Finally we move our first real time task into this resource group. We +also use taskset(1) to ensure the task always runs on a dedicated CPU +on socket 0. Most uses of resource groups will also constrain which +processors tasks run on. + +# echo 1234 > p0/tasks +# taskset -cp 1 1234 + +Ditto for the second real time task (with the remaining 25% of cache): + +# mkdir p1 +# echo "L3:0=7c00;1=fffff" > p1/schemata +# echo 5678 > p1/tasks +# taskset -cp 2 5678 + +Example 3 +--------- + +A single socket system which has real-time tasks running on core 4-7 and +non real-time workload assigned to core 0-3. The real-time tasks share text +and data, so a per task association is not required and due to interaction +with the kernel it's desired that the kernel on these cores shares L3 with +the tasks. + +# mount -t resctrl resctrl /sys/fs/resctrl +# cd /sys/fs/resctrl + +First we reset the schemata for the default group so that the "upper" +50% of the L3 cache on socket 0 cannot be used by ordinary tasks: + +# echo "L3:0=3ff" > schemata + +Next we make a resource group for our real time cores and give +it access to the "top" 50% of the cache on socket 0. + +# mkdir p0 +# echo "L3:0=ffc00;" > p0/schemata + +Finally we move core 4-7 over to the new group and make sure that the +kernel and the tasks running there get 50% of the cache. + +# echo C0 > p0/cpus diff --git a/Documentation/x86/topology.txt b/Documentation/x86/topology.txt index 06afac252f5b..f3e9d7e9ed6c 100644 --- a/Documentation/x86/topology.txt +++ b/Documentation/x86/topology.txt @@ -63,6 +63,15 @@ The topology of a system is described in the units of: The maximum possible number of packages in the system. Helpful for per package facilities to preallocate per package information. + - cpu_llc_id: + + A per-CPU variable containing: + - On Intel, the first APIC ID of the list of CPUs sharing the Last Level + Cache + + - On AMD, the Node ID or Core Complex ID containing the Last Level + Cache. In general, it is a number identifying an LLC uniquely on the + system. * Cores: diff --git a/MAINTAINERS b/MAINTAINERS index 680625c2d8f6..4432e23d56fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -81,7 +81,6 @@ Descriptions of section entries: Q: Patchwork web based patch tracking system site T: SCM tree type and location. Type is one of: git, hg, quilt, stgit, topgit - B: Bug tracking system location. S: Status, one of the following: Supported: Someone is actually paid to look after this. Maintained: Someone actually looks after it. @@ -143,7 +142,7 @@ S: Maintained F: drivers/net/ethernet/3com/typhoon* 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) -M: Adam Radford +M: Adam Radford L: linux-scsi@vger.kernel.org W: http://www.lsi.com S: Supported @@ -540,6 +539,7 @@ S: Supported F: fs/afs/ F: include/net/af_rxrpc.h F: net/rxrpc/af_rxrpc.c +W: https://www.infradead.org/~dhowells/kafs/ AGPGART DRIVER M: David Airlie @@ -976,6 +976,7 @@ M: Russell King L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) W: http://www.armlinux.org.uk/ S: Maintained +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git F: arch/arm/ ARM SUB-ARCHITECTURES @@ -1041,6 +1042,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained N: sun[x456789]i F: arch/arm/boot/dts/ntc-gr8* +F: arch/arm64/boot/dts/allwinner/ ARM/Allwinner SoC Clock Support M: Emilio López @@ -1152,6 +1154,7 @@ ARM/CLKDEV SUPPORT M: Russell King L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev F: arch/arm/include/asm/clkdev.h F: drivers/clk/clkdev.c @@ -1502,8 +1505,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-oxnas/ -F: arch/arm/boot/dts/oxnas* +F: arch/arm/boot/dts/ox8*.dtsi F: arch/arm/boot/dts/wd-mbwe.dts +F: arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts N: oxnas ARM/Mediatek RTC DRIVER @@ -1624,6 +1628,7 @@ F: arch/arm/mach-qcom/ F: arch/arm64/boot/dts/qcom/* F: drivers/i2c/busses/i2c-qup.c F: drivers/clk/qcom/ +F: drivers/pinctrl/qcom/ F: drivers/soc/qcom/ F: drivers/spi/spi-qup.c F: drivers/tty/serial/msm_serial.h @@ -1743,7 +1748,7 @@ F: drivers/staging/media/platform/s5p-cec/ ARM/SAMSUNG S5P SERIES JPEG CODEC SUPPORT M: Andrzej Pietrasiewicz -M: Jacek Anaszewski +M: Jacek Anaszewski L: linux-arm-kernel@lists.infradead.org L: linux-media@vger.kernel.org S: Maintained @@ -1804,9 +1809,7 @@ F: drivers/media/rc/st_rc.c F: drivers/media/platform/sti/c8sectpfe/ F: drivers/mmc/host/sdhci-st.c F: drivers/phy/phy-miphy28lp.c -F: drivers/phy/phy-miphy365x.c F: drivers/phy/phy-stih407-usb.c -F: drivers/phy/phy-stih41x-usb.c F: drivers/pinctrl/pinctrl-st.c F: drivers/remoteproc/st_remoteproc.c F: drivers/remoteproc/st_slim_rproc.c @@ -2192,14 +2195,6 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers) S: Supported F: sound/soc/atmel -ATMEL DMA DRIVER -M: Nicolas Ferre -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Supported -F: drivers/dma/at_hdmac.c -F: drivers/dma/at_hdmac_regs.h -F: include/linux/platform_data/dma-atmel.h - ATMEL XDMA DRIVER M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org @@ -2344,6 +2339,13 @@ F: include/uapi/linux/ax25.h F: include/net/ax25.h F: net/ax25/ +AXENTIA ASOC DRIVERS +M: Peter Rosin +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/sound/axentia,* +F: sound/soc/atmel/tse850-pcm5142.c + AZ6007 DVB DRIVER M: Mauro Carvalho Chehab M: Mauro Carvalho Chehab @@ -2793,7 +2795,7 @@ S: Supported F: drivers/net/ethernet/broadcom/bcmsysport.* BROADCOM VULCAN ARM64 SOC -M: Jayachandran C. +M: Jayachandran C. M: bcm-kernel-feedback-list@broadcom.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -3001,15 +3003,15 @@ L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git W: http://linuxtv.org S: Supported -F: Documentation/cec.txt +F: Documentation/media/kapi/cec-core.rst F: Documentation/media/uapi/cec -F: drivers/staging/media/cec/ +F: drivers/media/cec/ F: drivers/media/cec-edid.c F: drivers/media/rc/keymaps/rc-cec.c F: include/media/cec.h F: include/media/cec-edid.h -F: include/linux/cec.h -F: include/linux/cec-funcs.h +F: include/uapi/linux/cec.h +F: include/uapi/linux/cec-funcs.h CELL BROADBAND ENGINE ARCHITECTURE M: Arnd Bergmann @@ -3463,6 +3465,7 @@ F: arch/*/crypto/ F: crypto/ F: drivers/crypto/ F: include/crypto/ +F: include/linux/crypto* CRYPTOGRAPHIC RANDOM NUMBER GENERATOR M: Neil Horman @@ -3790,6 +3793,7 @@ F: include/linux/devcoredump.h DEVICE FREQUENCY (DEVFREQ) M: MyungJoo Ham M: Kyungmin Park +R: Chanwoo Choi L: linux-pm@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git S: Maintained @@ -4106,7 +4110,7 @@ F: drivers/gpu/drm/cirrus/ RADEON and AMDGPU DRM DRIVERS M: Alex Deucher M: Christian König -L: dri-devel@lists.freedesktop.org +L: amd-gfx@lists.freedesktop.org T: git git://people.freedesktop.org/~agd5f/linux S: Supported F: drivers/gpu/drm/radeon/ @@ -4578,7 +4582,8 @@ L: linux-edac@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git for-next T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac.git linux_next S: Supported -F: Documentation/edac.txt +F: Documentation/admin-guide/ras.rst +F: Documentation/driver-api/edac.rst F: drivers/edac/ F: include/linux/edac.h @@ -5069,9 +5074,11 @@ F: drivers/net/wan/dlci.c F: drivers/net/wan/sdla.c FRAMEBUFFER LAYER +M: Bartlomiej Zolnierkiewicz L: linux-fbdev@vger.kernel.org +T: git git://github.com/bzolnier/linux.git Q: http://patchwork.kernel.org/project/linux-fbdev/list/ -S: Orphan +S: Maintained F: Documentation/fb/ F: drivers/video/ F: include/video/ @@ -5079,6 +5086,14 @@ F: include/linux/fb.h F: include/uapi/video/ F: include/uapi/linux/fb.h +FREESCALE CAAM (Cryptographic Acceleration and Assurance Module) DRIVER +M: Horia Geantă +M: Dan Douglass +L: linux-crypto@vger.kernel.org +S: Maintained +F: drivers/crypto/caam/ +F: Documentation/devicetree/bindings/crypto/fsl-sec4.txt + FREESCALE DIU FRAMEBUFFER DRIVER M: Timur Tabi L: linux-fbdev@vger.kernel.org @@ -5144,6 +5159,12 @@ S: Maintained F: drivers/net/ethernet/freescale/fman F: Documentation/devicetree/bindings/powerpc/fsl/fman.txt +FREESCALE QORIQ DPAA ETHERNET DRIVER +M: Madalin Bucur +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/freescale/dpaa + FREESCALE SOC DRIVERS M: Scott Wood L: linuxppc-dev@lists.ozlabs.org @@ -5479,6 +5500,7 @@ M: Alex Elder M: Greg Kroah-Hartman S: Maintained F: drivers/staging/greybus/ +L: greybus-dev@lists.linaro.org GREYBUS AUDIO PROTOCOLS DRIVERS M: Vaibhav Agarwal @@ -5710,7 +5732,7 @@ S: Maintained F: drivers/media/dvb-frontends/hd29l2* HEWLETT PACKARD ENTERPRISE ILO NMI WATCHDOG DRIVER -M: Brian Boylston +M: Jimmy Vance S: Supported F: Documentation/watchdog/hpwdt.txt F: drivers/watchdog/hpwdt.c @@ -5936,6 +5958,7 @@ F: drivers/media/platform/sti/hva Hyper-V CORE AND DRIVERS M: "K. Y. Srinivasan" M: Haiyang Zhang +M: Stephen Hemminger L: devel@linuxdriverproject.org S: Maintained F: arch/x86/include/asm/mshyperv.h @@ -6498,10 +6521,7 @@ F: drivers/net/ethernet/intel/*/ INTEL RDMA RNIC DRIVER M: Faisal Latif -R: Chien Tin Tung -R: Mustafa Ismail -R: Shiraz Saleem -R: Tatyana Nikolova +M: Shiraz Saleem L: linux-rdma@vger.kernel.org S: Supported F: drivers/infiniband/hw/i40iw/ @@ -7207,7 +7227,7 @@ F: drivers/scsi/53c700* LED SUBSYSTEM M: Richard Purdie -M: Jacek Anaszewski +M: Jacek Anaszewski M: Pavel Machek L: linux-leds@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds.git @@ -7548,14 +7568,6 @@ S: Maintained F: Documentation/ldm.txt F: block/partitions/ldm.* -LogFS -M: Joern Engel -M: Prasad Joshi -L: logfs@logfs.org -W: logfs.org -S: Maintained -F: fs/logfs/ - LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Chaitra P B @@ -7687,8 +7699,10 @@ F: drivers/net/dsa/mv88e6xxx/ F: Documentation/devicetree/bindings/net/dsa/marvell.txt MARVELL ARMADA DRM SUPPORT -M: Russell King +M: Russell King S: Maintained +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes F: drivers/gpu/drm/armada/ F: include/uapi/drm/armada_drm.h F: Documentation/devicetree/bindings/display/armada/ @@ -7853,6 +7867,15 @@ F: Documentation/devicetree/bindings/media/renesas,fcp.txt F: drivers/media/platform/rcar-fcp.c F: include/media/rcar-fcp.h +MEDIA DRIVERS FOR RENESAS - FDP1 +M: Kieran Bingham +L: linux-media@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +S: Supported +F: Documentation/devicetree/bindings/media/renesas,fdp1.txt +F: drivers/media/platform/rcar_fdp1.c + MEDIA DRIVERS FOR RENESAS - VIN M: Niklas Söderlund L: linux-media@vger.kernel.org @@ -7959,6 +7982,24 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/mediatek/ +MEDIATEK MEDIA DRIVER +M: Tiffany Lin +M: Andrew-CT Chen +S: Supported +F: drivers/media/platform/mtk-vcodec/ +F: drivers/media/platform/mtk-vpu/ +F: Documentation/devicetree/bindings/media/mediatek-vcodec.txt +F: Documentation/devicetree/bindings/media/mediatek-vpu.txt + +MEDIATEK MDP DRIVER +M: Minghsiu Tsai +M: Houlong Wei +M: Andrew-CT Chen +S: Supported +F: drivers/media/platform/mtk-mdp/ +F: drivers/media/platform/mtk-vpu/ +F: Documentation/devicetree/bindings/media/mediatek-mdp.txt + MEDIATEK MT7601U WIRELESS LAN DRIVER M: Jakub Kicinski L: linux-wireless@vger.kernel.org @@ -8009,6 +8050,15 @@ W: http://www.mellanox.com Q: http://patchwork.ozlabs.org/project/netdev/list/ F: drivers/net/ethernet/mellanox/mlxsw/ +MELLANOX MLXCPLD I2C AND MUX DRIVER +M: Vadim Pasternak +M: Michael Shych +L: linux-i2c@vger.kernel.org +S: Supported +F: drivers/i2c/busses/i2c-mlxcpld.c +F: drivers/i2c/muxes/i2c-mux-mlxcpld.c +F: Documentation/i2c/busses/i2c-mlxcpld + MELLANOX MLXCPLD LED DRIVER M: Vadim Pasternak L: linux-leds@vger.kernel.org @@ -8020,7 +8070,14 @@ MELLANOX PLATFORM DRIVER M: Vadim Pasternak L: platform-driver-x86@vger.kernel.org S: Supported -F: arch/x86/platform/mellanox/mlx-platform.c +F: drivers/platform/x86/mlx-platform.c + +MELLANOX MLX CPLD HOTPLUG DRIVER +M: Vadim Pasternak +L: platform-driver-x86@vger.kernel.org +S: Supported +F: drivers/platform/x86/mlxcpld-hotplug.c +F: include/linux/platform_data/mlxcpld-hotplug.h SOFT-ROCE DRIVER (rxe) M: Moni Shoua @@ -8117,6 +8174,15 @@ S: Maintained F: drivers/tty/serial/atmel_serial.c F: include/linux/atmel_serial.h +MICROCHIP / ATMEL DMA DRIVER +M: Ludovic Desroches +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: dmaengine@vger.kernel.org +S: Supported +F: drivers/dma/at_hdmac.c +F: drivers/dma/at_hdmac_regs.h +F: include/linux/platform_data/dma-atmel.h + MICROCHIP / ATMEL ISC DRIVER M: Songjun Wu L: linux-media@vger.kernel.org @@ -8771,7 +8837,7 @@ T: git git://github.com/jonmason/ntb.git F: drivers/ntb/hw/intel/ NTB AMD DRIVER -M: Xiangliang Yu +M: Shyam Sundar S K L: linux-ntb@googlegroups.com S: Supported F: drivers/ntb/hw/amd/ @@ -8795,17 +8861,22 @@ F: drivers/video/fbdev/nvidia/ NVM EXPRESS DRIVER M: Keith Busch M: Jens Axboe +M: Christoph Hellwig +M: Sagi Grimberg L: linux-nvme@lists.infradead.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git -W: https://kernel.googlesource.com/pub/scm/linux/kernel/git/axboe/linux-block/ +T: git://git.infradead.org/nvme.git +W: http://git.infradead.org/nvme.git S: Supported F: drivers/nvme/host/ F: include/linux/nvme.h +F: include/uapi/linux/nvme_ioctl.h NVM EXPRESS TARGET DRIVER M: Christoph Hellwig M: Sagi Grimberg L: linux-nvme@lists.infradead.org +T: git://git.infradead.org/nvme.git +W: http://git.infradead.org/nvme.git S: Supported F: drivers/nvme/target/ @@ -8836,8 +8907,10 @@ S: Supported F: drivers/nfc/nxp-nci NXP TDA998X DRM DRIVER -M: Russell King +M: Russell King S: Supported +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-devel +T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-fixes F: drivers/gpu/drm/i2c/tda998x_drv.c F: include/drm/i2c/tda998x.h @@ -9785,7 +9858,7 @@ M: Mark Rutland M: Lorenzo Pieralisi L: linux-arm-kernel@lists.infradead.org S: Maintained -F: drivers/firmware/psci.c +F: drivers/firmware/psci*.c F: include/linux/psci.h F: include/uapi/linux/psci.h @@ -9924,7 +9997,7 @@ M: Hans Verkuil L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git S: Maintained -F: drivers/staging/media/pulse8-cec +F: drivers/media/usb/pulse8-cec/* PVRUSB2 VIDEO4LINUX DRIVER M: Mike Isely @@ -10079,6 +10152,12 @@ F: drivers/net/ethernet/qlogic/qed/ F: include/linux/qed/ F: drivers/net/ethernet/qlogic/qede/ +QLOGIC QL41xxx ISCSI DRIVER +M: QLogic-Storage-Upstream@cavium.com +L: linux-scsi@vger.kernel.org +S: Supported +F: drivers/scsi/qedi/ + QNX4 FILESYSTEM M: Anders Larsen W: http://www.alarsen.net/linux/qnx4fs/ @@ -10270,6 +10349,14 @@ L: linux-rdma@vger.kernel.org S: Supported F: drivers/infiniband/sw/rdmavt +RDT - RESOURCE ALLOCATION +M: Fenghua Yu +L: linux-kernel@vger.kernel.org +S: Supported +F: arch/x86/kernel/cpu/intel_rdt* +F: arch/x86/include/asm/intel_rdt* +F: Documentation/x86/intel_rdt* + READ-COPY UPDATE (RCU) M: "Paul E. McKenney" M: Josh Triplett @@ -10750,6 +10837,12 @@ S: Maintained F: Documentation/devicetree/bindings/serial/ F: drivers/tty/serial/ +SERIAL IR RECEIVER +M: Sean Young +L: linux-media@vger.kernel.org +S: Maintained +F: drivers/media/rc/serial_ir.c + STI CEC DRIVER M: Benjamin Gaignard L: kernel@stlinux.com @@ -11061,7 +11154,6 @@ F: drivers/net/ethernet/emulex/benet/ EMULEX ONECONNECT ROCE DRIVER M: Selvin Xavier M: Devesh Sharma -M: Mitesh Ahuja L: linux-rdma@vger.kernel.org W: http://www.emulex.com S: Supported @@ -11798,6 +11890,7 @@ S: Supported F: arch/arc/ F: Documentation/devicetree/bindings/arc/* F: Documentation/devicetree/bindings/interrupt-controller/snps,arc* +F: drivers/clocksource/arc_timer.c F: drivers/tty/serial/arc_uart.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git @@ -12058,6 +12151,16 @@ S: Maintained F: arch/xtensa/ F: drivers/irqchip/irq-xtensa-* +Texas Instruments' System Control Interface (TISCI) Protocol Driver +M: Nishanth Menon +M: Tero Kristo +M: Santosh Shilimkar +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt +F: drivers/firmware/ti_sci* +F: include/linux/soc/ti/ti_sci_protocol.h + THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org @@ -12972,6 +13075,7 @@ F: drivers/net/virtio_net.c F: drivers/block/virtio_blk.c F: include/linux/virtio_*.h F: include/uapi/linux/virtio_*.h +F: drivers/crypto/virtio/ VIRTIO DRIVERS FOR S390 M: Christian Borntraeger @@ -13008,6 +13112,14 @@ S: Maintained F: drivers/virtio/virtio_input.c F: include/uapi/linux/virtio_input.h +VIRTIO CRYPTO DRIVER +M: Gonglei +L: virtualization@lists.linux-foundation.org +L: linux-crypto@vger.kernel.org +S: Maintained +F: drivers/crypto/virtio/ +F: include/uapi/linux/virtio_crypto.h + VIA RHINE NETWORK DRIVER S: Orphan F: drivers/net/ethernet/via/via-rhine.c @@ -13112,6 +13224,13 @@ S: Maintained F: drivers/scsi/vmw_pvscsi.c F: drivers/scsi/vmw_pvscsi.h +VMWARE PVRDMA DRIVER +M: Adit Ranadive +M: VMware PV-Drivers +L: linux-rdma@vger.kernel.org +S: Maintained +F: drivers/infiniband/hw/vmw_pvrdma/ + VOLTAGE AND CURRENT REGULATOR FRAMEWORK M: Liam Girdwood M: Mark Brown @@ -13424,11 +13543,11 @@ F: arch/x86/xen/*swiotlb* F: drivers/xen/*swiotlb* XFS FILESYSTEM -M: Dave Chinner +M: Darrick J. Wong M: linux-xfs@vger.kernel.org L: linux-xfs@vger.kernel.org W: http://xfs.org/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/dgc/linux-xfs.git +T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git S: Supported F: Documentation/filesystems/xfs.txt F: fs/xfs/ diff --git a/Makefile b/Makefile index b1037774e8e8..96e2352d10a8 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ VERSION = 4 -PATCHLEVEL = 9 +PATCHLEVEL = 10 SUBLEVEL = 0 -EXTRAVERSION = +EXTRAVERSION = -rc4 NAME = Roaring Lionus # *DOCUMENTATION* diff --git a/arch/Kconfig b/arch/Kconfig index 19483aea4bbc..99839c23d453 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -5,6 +5,9 @@ config KEXEC_CORE bool +config HAVE_IMA_KEXEC + bool + config OPROFILE tristate "OProfile system profiling" depends on PROFILING diff --git a/arch/alpha/boot/misc.c b/arch/alpha/boot/misc.c index 3ff9a957a25c..1b568ed74f95 100644 --- a/arch/alpha/boot/misc.c +++ b/arch/alpha/boot/misc.c @@ -21,7 +21,7 @@ #include #include -#include +#include #define memzero(s,n) memset ((s),0,(n)) #define puts srm_printk diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index 2d6efcff3bf3..2f26ae74b61a 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -26,7 +26,7 @@ #include #include -#include +#include volatile unsigned long irq_err_count; DEFINE_PER_CPU(unsigned long, irq_pmi_count); diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index 56e427c7aa3c..54d8616644e2 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c index b483156698d5..bca963a4aa48 100644 --- a/arch/alpha/kernel/process.c +++ b/arch/alpha/kernel/process.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/alpha/kernel/ptrace.c b/arch/alpha/kernel/ptrace.c index 940dfb406591..bc4d2cdcf21d 100644 --- a/arch/alpha/kernel/ptrace.c +++ b/arch/alpha/kernel/ptrace.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include @@ -283,7 +283,7 @@ long arch_ptrace(struct task_struct *child, long request, /* When I and D space are separate, these will need to be fixed. */ case PTRACE_PEEKTEXT: /* read word at location addr. */ case PTRACE_PEEKDATA: - copied = access_process_vm(child, addr, &tmp, sizeof(tmp), + copied = ptrace_access_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE); ret = -EIO; if (copied != sizeof(tmp)) diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 4811e54069fc..491e6a604e82 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -53,7 +53,7 @@ static struct notifier_block alpha_panic_block = { INT_MAX /* try to do it first */ }; -#include +#include #include #include #include diff --git a/arch/alpha/kernel/signal.c b/arch/alpha/kernel/signal.c index 8dbfb15f1745..17308f925306 100644 --- a/arch/alpha/kernel/signal.c +++ b/arch/alpha/kernel/signal.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include #include diff --git a/arch/alpha/kernel/srm_env.c b/arch/alpha/kernel/srm_env.c index ffe996a54fad..705ae12acd15 100644 --- a/arch/alpha/kernel/srm_env.c +++ b/arch/alpha/kernel/srm_env.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #define BASE_DIR "srm_environment" /* Subdir in /proc/ */ diff --git a/arch/alpha/kernel/srmcons.c b/arch/alpha/kernel/srmcons.c index 72b59511e59a..e9c45b65a905 100644 --- a/arch/alpha/kernel/srmcons.c +++ b/arch/alpha/kernel/srmcons.c @@ -18,7 +18,7 @@ #include #include -#include +#include static DEFINE_SPINLOCK(srmcons_callback_lock); diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index 5b6202a825ff..3bfe058d75d9 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -34,7 +34,7 @@ #include #include -#include +#include #include #include @@ -133,7 +133,7 @@ init_rtc_clockevent(void) * The QEMU clock as a clocksource primitive. */ -static cycle_t +static u64 qemu_cs_read(struct clocksource *cs) { return qemu_get_vmtime(); @@ -260,7 +260,7 @@ common_init_rtc(void) * use this method when WTINT is in use. */ -static cycle_t read_rpcc(struct clocksource *cs) +static u64 read_rpcc(struct clocksource *cs) { return rpcc(); } diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 74aceead06e9..3328af7c2776 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/alpha/lib/csum_partial_copy.c b/arch/alpha/lib/csum_partial_copy.c index b4ff3b683bcd..5dfb7975895f 100644 --- a/arch/alpha/lib/csum_partial_copy.c +++ b/arch/alpha/lib/csum_partial_copy.c @@ -11,7 +11,7 @@ #include #include -#include +#include #define ldq_u(x,y) \ diff --git a/arch/alpha/math-emu/math.c b/arch/alpha/math-emu/math.c index 58c2669a1dd4..fa5ae0ad8983 100644 --- a/arch/alpha/math-emu/math.c +++ b/arch/alpha/math-emu/math.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include "sfp-util.h" #include diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c index a1bea91df56a..0542e973c73d 100644 --- a/arch/alpha/mm/init.c +++ b/arch/alpha/mm/init.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index bd204bfa29ed..c75d29077e4a 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -8,9 +8,10 @@ config ARC def_bool y + select ARC_TIMERS + select ARCH_HAS_SG_CHAIN select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC select BUILDTIME_EXTABLE_SORT - select CLKSRC_OF select CLONE_BACKWARDS select COMMON_CLK select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) @@ -115,6 +116,7 @@ config ISA_ARCOMPACT config ISA_ARCV2 bool "ARC ISA v2" + select ARC_TIMERS_64BIT help ISA for the Next Generation ARC-HS cores @@ -410,16 +412,6 @@ config ARC_HAS_DIV_REM bool "Insn: div, divu, rem, remu" default y -config ARC_HAS_RTC - bool "Local 64-bit r/o cycle counter" - default n - depends on !SMP - -config ARC_HAS_GFRC - bool "SMP synchronized 64-bit cycle counter" - default y - depends on SMP - config ARC_NUMBER_OF_INTERRUPTS int "Number of interrupts" range 8 240 diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi index de53f5c3251c..3121536b25a3 100644 --- a/arch/arc/boot/dts/abilis_tb10x.dtsi +++ b/arch/arc/boot/dts/abilis_tb10x.dtsi @@ -129,6 +129,7 @@ data-width = <4>; clocks = <&ahb_clk>; clock-names = "hclk"; + multi-block = <1 1 1 1 1 1>; }; i2c0: i2c@FF120000 { diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts index d9b9b9dcfc4c..70aec7d6ca60 100644 --- a/arch/arc/boot/dts/axs101.dts +++ b/arch/arc/boot/dts/axs101.dts @@ -17,6 +17,6 @@ compatible = "snps,axs101", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60"; }; }; diff --git a/arch/arc/boot/dts/axs103_idu.dts b/arch/arc/boot/dts/axs103_idu.dts index 070c29782216..5c843d9b4ac8 100644 --- a/arch/arc/boot/dts/axs103_idu.dts +++ b/arch/arc/boot/dts/axs103_idu.dts @@ -20,6 +20,6 @@ compatible = "snps,axs103", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0 video=1280x720@60"; }; }; diff --git a/arch/arc/boot/dts/zebu_hs.dts b/arch/arc/boot/dts/haps_hs.dts similarity index 100% rename from arch/arc/boot/dts/zebu_hs.dts rename to arch/arc/boot/dts/haps_hs.dts diff --git a/arch/arc/boot/dts/zebu_hs_idu.dts b/arch/arc/boot/dts/haps_hs_idu.dts similarity index 100% rename from arch/arc/boot/dts/zebu_hs_idu.dts rename to arch/arc/boot/dts/haps_hs_idu.dts diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig index 0a0eaf09aac7..6980b966a364 100644 --- a/arch/arc/configs/axs101_defconfig +++ b/arch/arc/configs/axs101_defconfig @@ -75,9 +75,11 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_HWMON is not set +CONFIG_DRM=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_ARCPGU=m CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig index 110874705085..30a3d4cf53d2 100644 --- a/arch/arc/configs/axs103_smp_defconfig +++ b/arch/arc/configs/axs103_smp_defconfig @@ -77,9 +77,11 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_HWMON is not set +CONFIG_DRM=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_ARCPGU=m CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set diff --git a/arch/arc/configs/zebu_hs_defconfig b/arch/arc/configs/haps_hs_defconfig similarity index 98% rename from arch/arc/configs/zebu_hs_defconfig rename to arch/arc/configs/haps_hs_defconfig index 9f6166be7145..57b3e599322f 100644 --- a/arch/arc/configs/zebu_hs_defconfig +++ b/arch/arc/configs/haps_hs_defconfig @@ -23,7 +23,7 @@ CONFIG_MODULES=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARC_PLAT_SIM=y CONFIG_ISA_ARCV2=y -CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs" +CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs" CONFIG_PREEMPT=y # CONFIG_COMPACTION is not set CONFIG_NET=y diff --git a/arch/arc/configs/zebu_hs_smp_defconfig b/arch/arc/configs/haps_hs_smp_defconfig similarity index 98% rename from arch/arc/configs/zebu_hs_smp_defconfig rename to arch/arc/configs/haps_hs_smp_defconfig index 44e9693f4257..f85985adebb2 100644 --- a/arch/arc/configs/zebu_hs_smp_defconfig +++ b/arch/arc/configs/haps_hs_smp_defconfig @@ -26,7 +26,7 @@ CONFIG_MODULES=y CONFIG_ARC_PLAT_SIM=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y -CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs_idu" +CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu" CONFIG_PREEMPT=y # CONFIG_COMPACTION is not set CONFIG_NET=y diff --git a/arch/arc/configs/nsimosci_hs_smp_defconfig b/arch/arc/configs/nsimosci_hs_smp_defconfig index 6da71ba253a9..155add7761ed 100644 --- a/arch/arc/configs/nsimosci_hs_smp_defconfig +++ b/arch/arc/configs/nsimosci_hs_smp_defconfig @@ -21,7 +21,7 @@ CONFIG_MODULES=y CONFIG_ARC_PLAT_SIM=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y -# CONFIG_ARC_HAS_GFRC is not set +# CONFIG_ARC_TIMERS_64BIT is not set CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs_idu" CONFIG_PREEMPT=y # CONFIG_COMPACTION is not set diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig index 969b206d6c67..573028f19de7 100644 --- a/arch/arc/configs/vdk_hs38_smp_defconfig +++ b/arch/arc/configs/vdk_hs38_smp_defconfig @@ -15,7 +15,7 @@ CONFIG_ARC_PLAT_AXS10X=y CONFIG_AXS103=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y -# CONFIG_ARC_HAS_GFRC is not set +# CONFIG_ARC_TIMERS_64BIT is not set CONFIG_ARC_UBOOT_SUPPORT=y CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp" CONFIG_PREEMPT=y diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 1bd24ec3e350..f659942744de 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -20,7 +20,6 @@ #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ #define ARC_REG_SLC_BCR 0xce #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ -#define ARC_REG_TIMERS_BCR 0x75 #define ARC_REG_AP_BCR 0x76 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ #define ARC_REG_XY_MEM_BCR 0x79 @@ -112,90 +111,7 @@ #ifndef __ASSEMBLY__ -/* - ****************************************************************** - * Inline ASM macros to read/write AUX Regs - * Essentially invocation of lr/sr insns from "C" - */ - -#if 1 - -#define read_aux_reg(reg) __builtin_arc_lr(reg) - -/* gcc builtin sr needs reg param to be long immediate */ -#define write_aux_reg(reg_immed, val) \ - __builtin_arc_sr((unsigned int)(val), reg_immed) - -#else - -#define read_aux_reg(reg) \ -({ \ - unsigned int __ret; \ - __asm__ __volatile__( \ - " lr %0, [%1]" \ - : "=r"(__ret) \ - : "i"(reg)); \ - __ret; \ -}) - -/* - * Aux Reg address is specified as long immediate by caller - * e.g. - * write_aux_reg(0x69, some_val); - * This generates tightest code. - */ -#define write_aux_reg(reg_imm, val) \ -({ \ - __asm__ __volatile__( \ - " sr %0, [%1] \n" \ - : \ - : "ir"(val), "i"(reg_imm)); \ -}) - -/* - * Aux Reg address is specified in a variable - * * e.g. - * reg_num = 0x69 - * write_aux_reg2(reg_num, some_val); - * This has to generate glue code to load the reg num from - * memory to a reg hence not recommended. - */ -#define write_aux_reg2(reg_in_var, val) \ -({ \ - unsigned int tmp; \ - \ - __asm__ __volatile__( \ - " ld %0, [%2] \n\t" \ - " sr %1, [%0] \n\t" \ - : "=&r"(tmp) \ - : "r"(val), "memory"(®_in_var)); \ -}) - -#endif - -#define READ_BCR(reg, into) \ -{ \ - unsigned int tmp; \ - tmp = read_aux_reg(reg); \ - if (sizeof(tmp) == sizeof(into)) { \ - into = *((typeof(into) *)&tmp); \ - } else { \ - extern void bogus_undefined(void); \ - bogus_undefined(); \ - } \ -} - -#define WRITE_AUX(reg, into) \ -{ \ - unsigned int tmp; \ - if (sizeof(tmp) == sizeof(into)) { \ - tmp = (*(unsigned int *)&(into)); \ - write_aux_reg(reg, tmp); \ - } else { \ - extern void bogus_undefined(void); \ - bogus_undefined(); \ - } \ -} +#include /* Helpers */ #define TO_KB(bytes) ((bytes) >> 10) @@ -291,13 +207,7 @@ struct bcr_fp_arcv2 { #endif }; -struct bcr_timer { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; -#else - unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; -#endif -}; +#include struct bcr_bpu_arcompact { #ifdef CONFIG_CPU_BIG_ENDIAN @@ -334,7 +244,7 @@ struct cpuinfo_arc_mmu { }; struct cpuinfo_arc_cache { - unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; + unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; }; struct cpuinfo_arc_bpu { diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index a093adbdb017..fc662f49c55a 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma, */ #define PG_dc_clean PG_arch_1 +#define CACHE_COLORS_NUM 4 +#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1) +#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK) + /* * Simple wrapper over config option * Bootup code ensures that hardware matches kernel configuration @@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void) return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); } -#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1) - /* * checks if two addresses (after page aligning) index into same cache set */ diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h index e880dfa3fcd3..a64c447b0337 100644 --- a/arch/arc/include/asm/irqflags-arcv2.h +++ b/arch/arc/include/asm/irqflags-arcv2.h @@ -38,10 +38,10 @@ #define AUX_IRQ_ACT_BIT_U 31 /* - * User space should be interruptable even by lowest prio interrupt - * Safe even if actual interrupt priorities is fewer or even one + * Hardware supports 16 priorities (0 highest, 15 lowest) + * Linux by default runs at 1, priority 0 reserved for NMI style interrupts */ -#define ARCV2_IRQ_DEF_PRIO 15 +#define ARCV2_IRQ_DEF_PRIO 1 /* seed value for status register */ #define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \ diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile index cfcdedf52ff8..8942c5c3b4c5 100644 --- a/arch/arc/kernel/Makefile +++ b/arch/arc/kernel/Makefile @@ -8,7 +8,7 @@ # Pass UTS_MACHINE for user_regset definition CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' -obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o +obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S index 7a1c124ff021..0b6388a5f0b8 100644 --- a/arch/arc/kernel/entry-arcv2.S +++ b/arch/arc/kernel/entry-arcv2.S @@ -67,12 +67,23 @@ ENTRY(handle_interrupt) INTERRUPT_PROLOGUE irq - clri ; To make status32.IE agree with CPU internal state + # irq control APIs local_irq_save/restore/disable/enable fiddle with + # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) + # However a taken interrupt doesn't clear these bits. Thus irqs_disabled() + # query in hard ISR path would return false (since .IE is set) which would + # trips genirq interrupt handling asserts. + # + # So do a "soft" disable of interrutps here. + # + # Note this disable is only for consistent book-keeping as further interrupts + # will be disabled anyways even w/o this. Hardware tracks active interrupts + # seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts + # unless this one returns (or higher prio becomes pending in 2-prio scheme) -#ifdef CONFIG_TRACE_IRQFLAGS - TRACE_ASM_IRQ_DISABLE -#endif + IRQ_DISABLE + ; icause is banked: one per priority level + ; so a higher prio interrupt taken here won't clobber prev prio icause lr r0, [ICAUSE] mov blink, ret_from_exception @@ -171,6 +182,7 @@ END(EV_TLBProtV) ; All 2 entry points to here already disable interrupts .Lrestore_regs: +restore_regs: # Interrpts are actually disabled from this point on, but will get # reenabled after we return from interrupt/exception. diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index 98812c1248df..9211707634dc 100644 --- a/arch/arc/kernel/entry-compact.S +++ b/arch/arc/kernel/entry-compact.S @@ -259,7 +259,7 @@ ENTRY(EV_TLBProtV) EXCEPTION_PROLOGUE - lr r2, [ecr] + mov r2, r9 ; ECR set into r9 already lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above) ; Exception auto-disables further Intr/exceptions. diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c index 62b59409a5d9..994dca7014db 100644 --- a/arch/arc/kernel/intc-arcv2.c +++ b/arch/arc/kernel/intc-arcv2.c @@ -14,8 +14,6 @@ #include #include -static int irq_prio; - /* * Early Hardware specific Interrupt setup * -Called very early (start_kernel -> setup_arch -> setup_processor) @@ -24,7 +22,7 @@ static int irq_prio; */ void arc_init_IRQ(void) { - unsigned int tmp; + unsigned int tmp, irq_prio; struct irq_build { #ifdef CONFIG_CPU_BIG_ENDIAN @@ -67,12 +65,12 @@ void arc_init_IRQ(void) irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ pr_info("archs-intc\t: %d priority levels (default %d)%s\n", - irq_prio + 1, irq_prio, + irq_prio + 1, ARCV2_IRQ_DEF_PRIO, irq_bcr.firq ? " FIRQ (not used)":""); /* setup status32, don't enable intr yet as kernel doesn't want */ tmp = read_aux_reg(0xa); - tmp |= STATUS_AD_MASK | (irq_prio << 1); + tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1); tmp &= ~STATUS_IE_MASK; asm volatile("kflag %0 \n"::"r"(tmp)); } @@ -93,7 +91,7 @@ void arcv2_irq_enable(struct irq_data *data) { /* set default priority */ write_aux_reg(AUX_IRQ_SELECT, data->irq); - write_aux_reg(AUX_IRQ_PRIORITY, irq_prio); + write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); /* * hw auto enables (linux unmask) all by default diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c index f39142acc89e..560c4afc2af4 100644 --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c @@ -11,8 +11,8 @@ #include #include #include +#include #include -#include #include static DEFINE_RAW_SPINLOCK(mcip_lock); diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 0385df77a697..3093fa898a23 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -234,11 +236,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) is_isa_arcompact() ? "ARCompact" : "ARCv2", IS_AVAIL1(cpu->isa.be, "[Big-Endian]")); - n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", + n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", IS_AVAIL1(cpu->extn.timer0, "Timer0 "), IS_AVAIL1(cpu->extn.timer1, "Timer1 "), - IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", - CONFIG_ARC_HAS_RTC)); + IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), + IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), @@ -449,6 +451,15 @@ void __init setup_arch(char **cmdline_p) arc_unwind_init(); } +/* + * Called from start_kernel() - boot CPU only + */ +void __init time_init(void) +{ + of_clk_init(NULL); + clocksource_probe(); +} + static int __init customize_machine(void) { if (machine_desc->init_machine) diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 50d71695cd4e..ec86ac0e3321 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -40,7 +40,7 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) struct cpuinfo_arc_cache *p; #define PR_CACHE(p, cfg, str) \ - if (!(p)->ver) \ + if (!(p)->line_len) \ n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ else \ n += scnprintf(buf + n, len - n, \ @@ -54,7 +54,7 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); p = &cpuinfo_arc700[c].slc; - if (p->ver) + if (p->line_len) n += scnprintf(buf + n, len - n, "SLC\t\t: %uK, %uB Line%s\n", p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); @@ -104,7 +104,6 @@ static void read_decode_cache_bcr_arcv2(int cpu) READ_BCR(ARC_REG_SLC_BCR, sbcr); if (sbcr.ver) { READ_BCR(ARC_REG_SLC_CFG, slc_cfg); - p_slc->ver = sbcr.ver; p_slc->sz_k = 128 << slc_cfg.sz; l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; } @@ -152,7 +151,6 @@ void read_decode_cache_bcr(void) p_ic->line_len = 8 << ibcr.line_len; p_ic->sz_k = 1 << (ibcr.sz - 1); - p_ic->ver = ibcr.ver; p_ic->vipt = 1; p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; @@ -176,7 +174,6 @@ dc_chk: p_dc->line_len = 16 << dbcr.line_len; p_dc->sz_k = 1 << (dbcr.sz - 1); - p_dc->ver = dbcr.ver; slc_chk: if (is_isa_arcv2()) @@ -945,17 +942,13 @@ void arc_cache_init(void) if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; - if (!ic->ver) + if (!ic->line_len) panic("cache support enabled but non-existent cache\n"); if (ic->line_len != L1_CACHE_BYTES) panic("ICache line [%d] != kernel Config [%d]", ic->line_len, L1_CACHE_BYTES); - if (ic->ver != CONFIG_ARC_MMU_VER) - panic("Cache ver [%d] doesn't match MMU ver [%d]\n", - ic->ver, CONFIG_ARC_MMU_VER); - /* * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 @@ -969,7 +962,7 @@ void arc_cache_init(void) if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; - if (!dc->ver) + if (!dc->line_len) panic("cache support enabled but non-existent cache\n"); if (dc->line_len != L1_CACHE_BYTES) @@ -979,11 +972,16 @@ void arc_cache_init(void) /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ if (is_isa_arcompact()) { int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); + int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE); - if (dc->alias && !handled) - panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); - else if (!dc->alias && handled) + if (dc->alias) { + if (!handled) + panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); + if (CACHE_COLORS_NUM != num_colors) + panic("CACHE_COLORS_NUM not optimized for config\n"); + } else if (!dc->alias && handled) { panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); + } } } diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c index cd8aad8226dd..08450a1a5b5f 100644 --- a/arch/arc/mm/dma.c +++ b/arch/arc/mm/dma.c @@ -158,7 +158,10 @@ static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, unsigned long attrs) { phys_addr_t paddr = page_to_phys(page) + offset; - _dma_cache_sync(paddr, size, dir); + + if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) + _dma_cache_sync(paddr, size, dir); + return plat_phys_to_dma(dev, paddr); } diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 86548701023c..38ff349d7f2a 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #define AXS_MB_CGU 0xE0010000 #define AXS_MB_CREG 0xE0011000 diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 9d6718c1a199..ee2e32df5e90 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -46,9 +46,7 @@ #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) /* EZchip core instructions */ -#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF -#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 #define CTOP_INST_SCHD_RW 0x3E6F7004 #define CTOP_INST_SCHD_RD 0x3E6F7084 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index caef68429b08..186c4c214e0a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,6 +888,11 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config MACH_STM32F746 + bool "STMicrolectronics STM32F746" + depends on ARCH_STM32 + default y + config ARCH_MPS2 bool "ARM MPS2 platform" depends on ARM_SINGLE_ARMV7M @@ -1497,8 +1502,7 @@ source kernel/Kconfig.preempt config HZ_FIXED int - default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ - ARCH_S5PV210 || ARCH_EXYNOS4 + default 200 if ARCH_EBSA110 default 128 if SOC_AT91RM9200 default 0 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6be9ee148b78..ab30cc634d02 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NSPIRE) += nspire +machine-$(CONFIG_ARCH_OXNAS) += oxnas machine-$(CONFIG_ARCH_OMAP1) += omap1 machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x @@ -311,8 +312,11 @@ all: $(KBUILD_IMAGE) $(KBUILD_DTBS) boot := arch/arm/boot +archheaders: + $(Q)$(MAKE) $(build)=arch/arm/tools uapi + archprepare: - $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h + $(Q)$(MAKE) $(build)=arch/arm/tools kapi # Convert bzImage to zImage bzImage: zImage diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c558ba75cbcc..7327250f0bb6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-luxul-xap-1510.dtb \ bcm4708-luxul-xwc-1000.dtb \ bcm4708-netgear-r6250.dtb \ bcm4708-netgear-r6300-v2.dtb \ @@ -86,11 +87,16 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-buffalo-wxr-1900dhp.dtb \ bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-dlink-dir-885l.dtb \ + bcm47094-luxul-xwr-3100.dtb \ + bcm47094-netgear-r8500.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ bcm953012k.dtb +dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-tenda-ac9.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ @@ -136,6 +142,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ + exynos4412-itop-elite.dtb \ exynos4412-odroidu3.dtb \ exynos4412-odroidx.dtb \ exynos4412-odroidx2.dtb \ @@ -330,6 +337,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ @@ -340,6 +348,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw552x.dtb \ imx6dl-gw553x.dtb \ imx6dl-hummingboard.dtb \ + imx6dl-icore.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ @@ -381,10 +390,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw553x.dtb \ imx6q-h100.dtb \ imx6q-hummingboard.dtb \ + imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ imx6q-marsboard.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_som2.dtb \ imx6q-novena.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ @@ -416,14 +427,19 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb + imx6sx-sdb.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ imx6ul-geam-kit.dtb \ + imx6ul-liteboard.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \ @@ -485,6 +501,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ logicpd-torpedo-37xx-devkit.dtb \ + logicpd-som-lv-37xx-devkit.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ omap3-beagle-xm.dtb \ @@ -561,6 +578,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-sl50.dtb \ am335x-wega-rdk.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ + omap4-droid4-xt894.dtb \ omap4-duovero-parlor.dtb \ omap4-kc1.dtb \ omap4-panda.dtb \ @@ -588,15 +606,18 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ + am571x-idk.dtb \ dra7-evm.dtb \ dra72-evm.dtb \ - dra72-evm-revc.dtb + dra72-evm-revc.dtb \ + dra71-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ orion5x-linkstation-lsgl.dtb \ orion5x-linkstation-lswtgl.dtb \ + orion5x-lschl.dtb \ orion5x-lswsgl.dtb \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-netgear-wnr854t.dtb \ @@ -604,7 +625,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ - wd-mbwe.dtb + wd-mbwe.dtb \ + cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-arrow-sd-600eval.dtb \ @@ -620,7 +642,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-honami.dtb + qcom-msm8974-sony-xperia-honami.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ @@ -635,11 +658,14 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pba8.dtb \ arm-realview-pbx-a9.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ + rk3066a-mk808.dtb \ rk3066a-rayeager.dtb \ + rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ rk3229-evb.dtb \ @@ -677,6 +703,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ + r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ @@ -690,12 +718,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += \ @@ -712,16 +742,12 @@ dtb-$(CONFIG_ARCH_STI) += \ stih407-b2120.dtb \ stih410-b2120.dtb \ stih410-b2260.dtb \ - stih415-b2000.dtb \ - stih415-b2020.dtb \ - stih416-b2000.dtb \ - stih416-b2020.dtb \ - stih416-b2020e.dtb \ stih418-b2199.dtb dtb-$(CONFIG_ARCH_STM32)+= \ stm32f429-disco.dtb \ stm32f469-disco.dtb \ - stm32429i-eval.dtb + stm32429i-eval.dtb \ + stm32746g-eval.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ @@ -760,6 +786,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-q8-tablet.dtb \ sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ sun5i-gr8-evb.dtb \ sun5i-r8-chip.dtb dtb-$(CONFIG_MACH_SUN6I) += \ @@ -897,6 +924,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8750-apc8750.dtb \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ zynq-zc706.dtb \ @@ -920,6 +948,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-db-ap.dtb \ armada-385-linksys-caiman.dtb \ armada-385-linksys-cobra.dtb \ + armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ armada-388-db.dtb \ armada-388-gp.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index a9a97307d66c..501c7527121b 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -54,16 +54,22 @@ dr_mode = "host"; }; +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + &cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; phy-mode = "rmii"; dual_emac_res_vlan = <1>; + phy-handle = <&phy0>; }; &cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; phy-mode = "rgmii-txid"; dual_emac_res_vlan = <2>; + phy-handle = <&phy1>; }; &phy_sel { diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index fe002a17c04b..19f53b8569e1 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -109,9 +109,9 @@ }; &cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; phy-mode = "rgmii-txid"; dual_emac_res_vlan = <2>; + phy-handle = <&phy1>; }; &phy_sel { diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index d0faa7b8c5da..2b9d7f4db23f 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -114,7 +114,7 @@ &usb1 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &cpsw_emac0 { @@ -127,9 +127,9 @@ }; &cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; phy-mode = "rgmii-txid"; dual_emac_res_vlan = <2>; + phy-handle = <&phy1>; }; &phy_sel { diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index dd45d172a892..efb5eae290a8 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -364,11 +364,14 @@ }; &davinci_mdio { + status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; + phy1: ethernet-phy@1 { + reg = <7>; + }; }; &mmc1 { @@ -406,3 +409,7 @@ &gpio0 { ti,no-reset-on-init; }; + +&gpio3 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 007b5e5a51a9..3e32dd18fd25 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -310,8 +310,23 @@ * by the hardware problems. (Tip: double-check by performing a current * measurement after shutdown: it should be less than 1 mA.) */ + + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + ti,pmic-shutdown-controller; + charger { + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + status = "okay"; + }; + + pwrbutton { + interrupts = <2>; + status = "okay"; + }; + regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; @@ -393,3 +408,8 @@ &sham { status = "okay"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 6bbb1fee0868..db00d8ef7b19 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -79,6 +79,14 @@ &lcdc { status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + */ + blue-and-red-wiring = "straight"; + port { lcdc_0: endpoint@0 { remote-endpoint = <&hdmi_0>; @@ -95,6 +103,9 @@ pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + #sound-dai-cells = <0>; audio-ports = < TDA998x_I2S 0x03>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e82432c79f85..c2186ec2834b 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -783,3 +783,8 @@ pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 975c36e332a2..e2548d1ce753 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -715,3 +715,8 @@ blue-and-red-wiring = "crossed"; }; + +&rtc { + clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 85e04c205542..1463df3b5b19 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -43,52 +43,52 @@ enable-active-high; }; - leds0 { + leds-iio { + status = "disabled"; compatible = "gpio-leds"; - - led0 { + led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led1 { + led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led2 { + led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led3 { + led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led4 { + led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led5 { + led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led6 { + led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led7 { + led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -187,6 +187,8 @@ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ >; }; @@ -224,6 +226,31 @@ }; }; +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <1 2 3 4 5 6 7>; + }; +}; + #include "tps65910.dtsi" &tps { diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 194d884c9de1..18d72a245e88 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -16,6 +16,7 @@ interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c0; @@ -130,6 +131,7 @@ reg = <0x210000 0x2000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x210000 0x2000>; am33xx_pinmux: pinmux@800 { @@ -137,6 +139,7 @@ reg = <0x800 0x238>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; }; @@ -505,6 +508,8 @@ interrupts = <75 76>; ti,hwmods = "rtc"; + clocks = <&clkdiv32k_ick>; + clock-names = "int-clk"; }; spi0: spi@48030000 { @@ -855,6 +860,8 @@ interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 0db19d39d24c..9fe545dbfa89 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -66,6 +66,7 @@ reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index a275fa956813..2df9e6050c2f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -16,6 +16,7 @@ interrupt-parent = <&wakeupgen>; #address-cells = <1>; #size-cells = <1>; + chosen { }; memory@0 { device_type = "memory"; @@ -189,6 +190,7 @@ reg = <0x800 0x31c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; @@ -871,6 +873,8 @@ clocks = <&adc_tsc_fck>; clock-names = "fck"; status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 25ce611c6568..b76a7c0264a5 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -117,6 +117,58 @@ compatible = "fixed-clock"; clock-frequency = <32768>; }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; }; &am43xx_pinmux { @@ -178,6 +230,24 @@ >; }; + spi1_pins_default: spi1_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ + AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ + AM4372_IOPAD(0x944, PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ + AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ + >; + }; + + spi1_pins_sleep: spi1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ @@ -290,6 +360,33 @@ pinctrl-0 = <&i2c2_pins_default>; pinctrl-1 = <&i2c2_pins_sleep>; clock-frequency = <100000>; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; }; &epwmss0 { @@ -310,6 +407,10 @@ status = "okay"; }; +&gpio3 { + status = "okay"; +}; + &gpio4 { status = "okay"; }; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts new file mode 100644 index 000000000000..ad68d1eb3bc3 --- /dev/null +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include +#include +#include "am57xx-idk-common.dtsi" + +/ { + model = "TI AM5718 IDK"; + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + usr1-led { + label = "status1:red:usr"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + usr2-led { + label = "status1:green:usr"; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&extcon_usb2 { + id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 87bbc66f0f21..8350b4b34b08 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -23,11 +23,6 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - }; - status-leds { compatible = "gpio-leds"; cpu0-led { @@ -76,6 +71,11 @@ extcon = <&extcon_usb2>; }; +&extcon_usb2 { + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +}; + &mmc1 { status = "okay"; vmmc-supply = <&v3_3d>; @@ -83,3 +83,11 @@ bus-width = <4>; cd-gpios = <&gpio6 27 0>; /* gpio 219 */ }; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 6df7829a2c15..78bee26361f1 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -204,6 +204,7 @@ interrupt-controller; ti,system-power-controller; + ti,palmas-override-powerhold; tps659038_pmic { compatible = "ti,tps659038-pmic"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 03cec62260e1..814a720d5c3d 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -43,6 +43,58 @@ regulator-always-on; regulator-boot-on; }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; }; &i2c1 { @@ -57,6 +109,7 @@ #interrupt-cells = <2>; interrupt-controller; ti,system-power-controller; + ti,palmas-override-powerhold; tps659038_pmic { compatible = "ti,tps659038-pmic"; @@ -250,6 +303,35 @@ gpio-controller; #gpio-cells = <2>; }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + /* ID & VBUS GPIOs provided in board dts */ + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; }; }; @@ -294,7 +376,7 @@ }; &usb2 { - dr_mode = "otg"; + dr_mode = "peripheral"; }; &mmc2 { diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 033fa63544f7..a9419f8e17e8 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; @@ -86,18 +86,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -182,24 +170,6 @@ }; }; }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; sound { @@ -261,6 +231,37 @@ }; }; +&pciec { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + + &spi0 { pinctrl-0 = <&spi0_pins2>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts index e2a363b1dd8a..aeedc463daa6 100644 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts @@ -62,7 +62,7 @@ stdout-path = &uart0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MiB */ }; @@ -72,20 +72,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { sata@a0000 { nr-ports = <2>; @@ -262,6 +248,20 @@ }; }; +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + &pinctrl { sata_l_white_pin: sata-l-white-pin { marvell,pins = "mpp57"; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index d5e19cd4d256..a1425409e570 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -54,7 +54,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -64,22 +64,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -113,17 +97,6 @@ }; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -197,6 +170,34 @@ }; }; +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &pinctrl { pwr_led_pin: pwr-led-pin { marvell,pins = "mpp63"; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 39181b3fa90d..6bd9265f1062 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -66,22 +66,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -99,14 +83,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - }; - ethernet@74000 { pinctrl-0 = <&ge1_rgmii_pins>; pinctrl-names = "default"; @@ -120,8 +96,11 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; isl12057: isl12057@68 { @@ -257,6 +236,30 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; +}; + &pinctrl { power_led_pin: power-led-pin { marvell,pins = "mpp57"; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 11565752b9f6..c84ab5bf1e18 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -66,22 +66,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -93,18 +77,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -126,8 +98,11 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <100000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; isl12057: isl12057@68 { @@ -279,6 +254,34 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to Marvell 88SE9215 SATA controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + &pinctrl { poweroff: poweroff { marvell,pins = "mpp60"; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index fbef730e8d37..c3fd6e49212f 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -77,22 +77,6 @@ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -102,14 +86,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -146,7 +122,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - button@1 { + button { label = "Software Button"; linux,code = ; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; @@ -196,7 +172,7 @@ }; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -235,7 +211,32 @@ }; }; }; - }; +}; + +&pciec { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { fan_pins: fan-pins { diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts index ae2e1fe50ef6..eb6af53b4954 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts +++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts @@ -28,20 +28,7 @@ compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; soc { - pcie-controller { - /* SATA AHCI controller 88SE9170 */ - pcie@1,0 { - status = "okay"; - }; - }; - internal-regs { - mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@74000 { status = "okay"; pinctrl-0 = <&ge1_rgmii_pins>; @@ -131,3 +118,17 @@ 1300 0>; }; }; + +&pciec { + /* SATA AHCI controller 88SE9170 */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi index 3036e25c5992..e9a5b952afc0 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -32,15 +32,6 @@ ranges = ; - pcie-controller { - status = "okay"; - - /* USB 3.0 bridge ASM1042A */ - pcie@2,0 { - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -51,15 +42,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@70000 { status = "okay"; pinctrl-0 = <&ge0_rgmii_pins>; @@ -159,19 +141,19 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power button"; linux,code = ; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@2 { + backup { label = "Backup button"; linux,code = ; gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@3 { + reset { label = "Reset Button"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; @@ -208,6 +190,25 @@ }; }; +&pciec { + status = "okay"; + + /* USB 3.0 bridge ASM1042A */ + pcie@2,0 { + status = "okay"; + }; +}; + + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index 01cded310cbc..d079a89ee5a2 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -24,7 +24,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -33,15 +33,6 @@ ranges = ; - pcie-controller { - status = "okay"; - - /* USB 3.0 Bridge ASM1042A */ - pcie@1,0 { - status = "okay"; - }; - }; - internal-regs { coherency-fabric@20200 { broken-idle; @@ -51,15 +42,6 @@ status = "okay"; }; - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - ethernet@74000 { status = "okay"; pinctrl-0 = <&ge1_rgmii_pins>; @@ -107,19 +89,19 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power button"; linux,code = ; gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; debounce-interval = <100>; }; - button@2 { + reset { label = "Reset Button"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@3 { + button { label = "USB VBUS error"; linux,code = ; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; @@ -143,6 +125,24 @@ }; }; +&pciec { + status = "okay"; + + /* USB 3.0 Bridge ASM1042A */ + pcie@1,0 { + status = "okay"; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &pinctrl { pinctrl-0 = <&sata_led_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index a9cc42776874..99f9de229ea8 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -70,7 +70,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; @@ -127,12 +127,6 @@ status = "okay"; }; - mdio { - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy1>; @@ -192,7 +186,7 @@ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; pinctrl-names = "default"; - sata1_regulator: sata1-regulator { + sata1_regulator: sata1-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "SATA1 Power"; @@ -205,7 +199,7 @@ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; - sata2_regulator: sata2-regulator { + sata2_regulator: sata2-regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "SATA2 Power"; @@ -220,6 +214,12 @@ }; }; +&mdio { + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + &pinctrl { disk1_led_pin: disk1-led-pin { marvell,pins = "mpp31"; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 3ccedc9dffb2..b0520bdeea27 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -50,8 +50,6 @@ * 370 and Armada XP SoC. */ -/include/ "skeleton64.dtsi" - #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { @@ -86,7 +84,7 @@ pcie-mem-aperture = <0xf8000000 0x7e00000>; pcie-io-aperture = <0xffe00000 0x100000>; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -96,7 +94,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -106,7 +104,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -116,7 +114,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -126,7 +124,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -142,7 +140,7 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <50>; @@ -214,33 +212,38 @@ msi-controller; }; - coherency-fabric@20200 { + coherencyfab: coherency-fabric@20200 { compatible = "marvell,coherency-fabric"; reg = <0x20200 0xb0>, <0x21010 0x1c>; }; - timer@20300 { + timer: timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; - watchdog@20300 { + watchdog: watchdog@20300 { reg = <0x20300 0x34>, <0x20704 0x4>; }; - pmsu@22000 { + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + + pmsu: pmsu@22000 { compatible = "marvell,armada-370-pmsu"; reg = <0x22000 0x1000>; }; - usb@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; interrupts = <45>; status = "disabled"; }; - usb@51000 { + usb1: usb@51000 { compatible = "marvell,orion-ehci"; reg = <0x51000 0x500>; interrupts = <46>; @@ -254,7 +257,7 @@ status = "disabled"; }; - mdio: mdio { + mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; @@ -269,7 +272,7 @@ status = "disabled"; }; - sata@a0000 { + sata: sata@a0000 { compatible = "marvell,armada-370-sata"; reg = <0xa0000 0x5000>; interrupts = <55>; @@ -278,7 +281,7 @@ status = "disabled"; }; - nand@d0000 { + nand: nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; @@ -288,7 +291,7 @@ status = "disabled"; }; - mvsdio@d4000 { + sdio: mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; interrupts = <54>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index b4258105e91f..b704bcc597f7 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -50,9 +50,11 @@ */ #include "armada-370-xp.dtsi" -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; @@ -70,7 +72,7 @@ reg = ; }; - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -89,7 +91,7 @@ 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -106,7 +108,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -125,7 +127,7 @@ }; internal-regs { - L2: l2-cache { + L2: l2-cache@8000 { compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; @@ -134,14 +136,6 @@ wt-override; }; - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -175,22 +169,8 @@ interrupts = <91>; }; - /* - * Default UART pinctrl setting without RTS/CTS, can - * be overwritten on board level if a different - * configuration is used. - */ - uart0: serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - }; - uart1: serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; - - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x100>; }; @@ -208,37 +188,18 @@ #clock-cells = <1>; }; - thermal@18300 { + thermal: thermal@18300 { compatible = "marvell,armada370-thermal"; reg = <0x18300 0x4 0x18304 0x4>; status = "okay"; }; - sscg@18330 { + sscg: sscg@18330 { reg = <0x18330 0x4>; }; - interrupt-controller@20a00 { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; - }; - - watchdog@20300 { - compatible = "marvell,armada-370-wdt"; - clocks = <&coreclk 2>; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x8>; - }; - - cpu-config@21000 { + cpuconf: cpu-config@21000 { compatible = "marvell,armada-370-cpu-config"; reg = <0x21000 0x8>; }; @@ -253,15 +214,7 @@ status = "disabled"; }; - usb@50000 { - clocks = <&coreclk 0>; - }; - - usb@51000 { - clocks = <&coreclk 0>; - }; - - xor@60800 { + xor0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -280,7 +233,7 @@ }; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -299,15 +252,7 @@ }; }; - ethernet@70000 { - compatible = "marvell,armada-370-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-370-neta"; - }; - - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-370-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -342,6 +287,59 @@ }; }; +/* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. + */ + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + reg = <0x11000 0x20>; +}; + +&i2c1 { + reg = <0x11100 0x20>; +}; + +&mpic { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; +}; + +&timer { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; +}; + +&watchdog { + compatible = "marvell,armada-370-wdt"; + clocks = <&coreclk 2>; +}; + +&usb0 { + clocks = <&coreclk 0>; +}; + +&usb1 { + clocks = <&coreclk 0>; +}; + +ð0 { + compatible = "marvell,armada-370-neta"; +}; + +ð1 { + compatible = "marvell,armada-370-neta"; +}; + &pinctrl { compatible = "marvell,mv88f6710-pinctrl"; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index cded5f0a262d..ef45cbeb3e7d 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -58,7 +58,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; @@ -69,138 +69,141 @@ MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; - internal-regs { - spi@10600 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - /* - * SPI conflicts with NAND, so we disable it - * here, and select NAND as the enabled device - * by default. - */ - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - }; - - serial@12000 { - status = "okay"; - }; - - pinctrl { - sdio_st_pins: sdio-st-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "gpio"; - }; - }; - - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - - nand: nand@d0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - - usb@54000 { - status = "okay"; - }; - - usb3@58000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins &sdio_st_pins>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - - ethernet@f0000 { - status = "okay"; - - eth0@c4000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - eth1@c5000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "gmii"; - }; - }; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; }; +&pciec { + status = "okay"; +}; + +/* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ +&pcie0 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&pcie1 { + /* Port 1, Lane 0 */ + status = "okay"; +}; + + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + + /* + * SPI conflicts with NAND, so we disable it here, and + * select NAND as the enabled device by default. + */ + + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + sdio_st_pins: sdio-st-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&sdio { + pinctrl-0 = <&sdio_pins &sdio_st_pins>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +ðernet { + status = "okay"; +}; + + +ð0 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +ð1 { + status = "okay"; + phy = <&phy3>; + phy-mode = "gmii"; +}; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index cc952cf8ec30..f515591e8733 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -45,7 +45,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include #include @@ -53,6 +52,9 @@ #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 375 family SoC"; compatible = "marvell,armada375"; @@ -65,7 +67,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; @@ -84,12 +86,12 @@ #size-cells = <0>; enable-method = "marvell,armada-375-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -115,7 +117,7 @@ reg = ; }; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -125,7 +127,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -135,7 +137,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -145,7 +147,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -155,7 +157,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -182,12 +184,12 @@ prefetch-data = <1>; }; - scu@c000 { + scu: scu@c000 { compatible = "arm,cortex-a9-scu"; reg = <0xc000 0x58>; }; - timer@c600 { + timer0: timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; interrupts = ; @@ -203,7 +205,7 @@ <0xc100 0x100>; }; - mdio { + mdio: mdio@c0054 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; @@ -212,7 +214,7 @@ }; /* Network controller */ - ethernet@f0000 { + ethernet: ethernet@f0000 { compatible = "marvell,armada-375-pp2"; reg = <0xf0000 0xa000>, /* Packet Processor regs */ <0xc0000 0x3060>, /* LMS regs */ @@ -222,20 +224,20 @@ clock-names = "pp_clk", "gop_clk"; status = "disabled"; - eth0: eth0@c4000 { + eth0: eth0 { interrupts = ; port-id = <0>; status = "disabled"; }; - eth1: eth1@c5000 { + eth1: eth1 { interrupts = ; port-id = <1>; status = "disabled"; }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = ; @@ -307,7 +309,7 @@ status = "disabled"; }; - pinctrl { + pinctrl: pinctrl@18000 { compatible = "marvell,mv88f6720-pinctrl"; reg = <0x18000 0x24>; @@ -382,7 +384,7 @@ interrupts = ; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-375-system-controller"; reg = <0x18200 0x100>; }; @@ -415,7 +417,7 @@ interrupts = ; }; - timer@20300 { + timer1: timer@20300 { compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, @@ -428,24 +430,24 @@ clock-names = "nbclk", "fixed"; }; - watchdog@20300 { + watchdog: watchdog@20300 { compatible = "marvell,armada-375-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; clocks = <&coreclk 0>, <&refclk>; clock-names = "nbclk", "fixed"; }; - cpurst@20800 { + cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; - coherency-fabric@21010 { + coherencyfab: coherency-fabric@21010 { compatible = "marvell,armada-375-coherency-fabric"; reg = <0x21010 0x1c>; }; - usb@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; interrupts = ; @@ -455,7 +457,7 @@ status = "disabled"; }; - usb@54000 { + usb1: usb@54000 { compatible = "marvell,orion-ehci"; reg = <0x54000 0x500>; interrupts = ; @@ -463,7 +465,7 @@ status = "disabled"; }; - usb3@58000 { + usb2: usb3@58000 { compatible = "marvell,armada-375-xhci"; reg = <0x58000 0x20000>,<0x5b880 0x80>; interrupts = ; @@ -473,7 +475,7 @@ status = "disabled"; }; - xor@60800 { + xor0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -493,7 +495,7 @@ }; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -513,7 +515,7 @@ }; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-375-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -528,7 +530,7 @@ marvell,crypto-sram-size = <0x800>; }; - sata@a0000 { + sata: sata@a0000 { compatible = "marvell,armada-370-sata"; reg = <0xa0000 0x5000>; interrupts = ; @@ -537,7 +539,7 @@ status = "disabled"; }; - nand@d0000 { + nand: nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; @@ -547,7 +549,7 @@ status = "disabled"; }; - mvsdio@d4000 { + sdio: mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; interrupts = ; @@ -559,7 +561,7 @@ status = "disabled"; }; - thermal@e8078 { + thermal: thermal@e8078 { compatible = "marvell,armada375-thermal"; reg = <0xe8078 0x4>, <0xe807c 0x8>; status = "okay"; @@ -580,7 +582,7 @@ }; }; - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -599,7 +601,7 @@ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -616,7 +618,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie1: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts new file mode 100644 index 000000000000..ab49acb2d452 --- /dev/null +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -0,0 +1,340 @@ +/* + * Device Tree file for the Turris Omnia + * + * Copyright (C) 2016 Uwe Kleine-König + * Copyright (C) 2016 Tomas Hlavacek + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf + */ + +/dts-v1/; + +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Turris Omnia"; + compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + /* USB part of the PCIe2/USB 2.0 port */ + usb@58000 { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + }; +}; + +/* Connected to 88E6176 switch, port 6 */ +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&ge0_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* Connected to 88E6176 switch, port 5 */ +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* WAN port */ +ð2 { + status = "okay"; + phy-mode = "sgmii"; + phy = <&phy1>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + i2cmux@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + status = "okay"; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* STM32F0 command interface at address 0x2a */ + /* leds device (in STM32F0) at address 0x2b */ + + eeprom@54 { + compatible = "at,24c64"; + reg = <0x54>; + + /* The EEPROM contains data for bootloader. + * Contents: + * struct omnia_eeprom { + * u32 magic; (=0x0341a034 in LE) + * u32 ramsize; (in GiB) + * char regdomain[4]; + * u32 crc32; + * }; + */ + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* routed to PCIe0/mSATA connector (CN7A) */ + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* routed to PCIe1/USB2 connector (CN61A) */ + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + /* routed to PCIe2 connector (CN62A) */ + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + /* routed to SFP+ */ + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + /* ATSHA204A at address 0x64 */ + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + /* exposed on pin header */ + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + pcawan: gpio@71 { + /* + * GPIO expander for SFP+ signals and + * and phy irq + */ + compatible = "nxp,pca9538"; + reg = <0x71>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcawan_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + phy1: phy@1 { + status = "okay"; + compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + /* irq is connected to &pcawan pin 7 */ + }; + + /* Switch MV88E7176 at address 0x10 */ +}; + +&pinctrl { + pcawan_pins: pcawan-pins { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + spi0cs0_pins: spi0cs0-pins { + marvell,pins = "mpp25"; + marvell,function = "spi0"; + }; + + spi0cs1_pins: spi0cs1-pins { + marvell,pins = "mpp26"; + marvell,function = "spi0"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0cs0_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "spansion,s25fl164k", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x00100000>; + label = "U-Boot"; + }; + + partition@100000 { + reg = <0x00100000 0x00700000>; + label = "Rescue system"; + }; + }; + }; + + /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ +}; + +&uart0 { + /* Pin header CN10 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + /* Pin header CN11 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 2d7668848c5a..7450e9fea45d 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -661,7 +661,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 34cba87f9200..de171baffcf6 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -573,7 +573,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index ce152719bc28..1e1fc4fccbad 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -62,7 +62,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ }; @@ -73,28 +73,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* First mini-PCIe port */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Renesas uPD720202 USB 3.0 controller */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - internal-regs { /* UART0 */ serial@12000 { @@ -111,16 +89,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -145,7 +113,7 @@ pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - button@1 { + reset { label = "Factory Reset Button"; linux,code = ; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -153,6 +121,38 @@ }; }; +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&pciec { + status = "okay"; + + /* First mini-PCIe port */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Renesas uPD720202 USB 3.0 controller */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + &pinctrl { pinctrl-0 = <&phy_int_pin>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 075120bc3ec4..44a724d39dbe 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -67,7 +67,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ }; @@ -108,39 +108,6 @@ }; }; - pcie-controller { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -160,24 +127,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <25>; - }; - - phy3: ethernet-phy@3 { - reg = <27>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -266,6 +215,57 @@ }; }; +&pciec { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; +}; + &spi0 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 190e4eccb180..72cb8fa377e3 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -68,7 +68,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; /* * 8 GB of plug-in RAM modules by default.The amount @@ -127,27 +127,6 @@ }; }; - pcie-controller { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; @@ -175,24 +154,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -251,6 +212,45 @@ }; }; +&pciec { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; +}; + &spi0 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 8af463f26ea1..d848ae9007db 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -57,7 +57,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x20000000>; /* 512MB */ }; @@ -68,37 +68,11 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Quad port sata: Marvell 88SX7042 */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* USB 3.0 xHCI controller: NEC D720200F1 */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; @@ -295,6 +269,31 @@ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; +&pciec { + status = "okay"; + + /* Quad port sata: Marvell 88SX7042 */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* USB 3.0 xHCI controller: NEC D720200F1 */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; &pinctrl { poweroff_pin: poweroff-pin { diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 076f27f22c3b..83ac884c0f8a 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -62,7 +62,7 @@ stdout-path = &uart0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ }; @@ -73,28 +73,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Etron EJ168 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* First mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - internal-regs { rtc@10300 { @@ -289,13 +267,13 @@ pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - button@1 { + wps { label = "WPS"; linux,code = ; gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Factory Reset Button"; linux,code = ; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -323,7 +301,7 @@ 4500 1>; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -369,6 +347,28 @@ }; }; +&pciec { + status = "okay"; + + /* Etron EJ168 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* First mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; +}; + &pinctrl { keys_pin: keys-pin { diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index 6522b04f4a8e..16277380e714 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -55,7 +55,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; /* * This board has 4 GB of RAM, but the last 256 MB of @@ -99,18 +99,18 @@ }; }; - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - usb@50000 { status = "okay"; }; }; }; }; + +&pciec { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 6e6d0f04bf2b..05c164b5786d 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -86,7 +86,7 @@ * configured as x4 or quad x1 lanes. One unit is * x1 only. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -114,7 +114,7 @@ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -131,7 +131,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -148,7 +148,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -165,7 +165,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -182,7 +182,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index c5fdc99f0dbe..07894b0d3e59 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -87,7 +87,7 @@ * configured as x4 or quad x1 lanes. One unit is * x4 only. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -129,7 +129,7 @@ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -146,7 +146,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -163,7 +163,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -180,7 +180,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -197,7 +197,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; @@ -214,7 +214,7 @@ status = "disabled"; }; - pcie@6,0 { + pcie6: pcie@6,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; @@ -231,7 +231,7 @@ status = "disabled"; }; - pcie@7,0 { + pcie7: pcie@7,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; @@ -248,7 +248,7 @@ status = "disabled"; }; - pcie@8,0 { + pcie8: pcie@8,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; @@ -265,7 +265,7 @@ status = "disabled"; }; - pcie@9,0 { + pcie9: pcie@9,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 0e24f1a38540..775bee53ce86 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -104,7 +104,7 @@ * configured as x4 or quad x1 lanes. Two units are * x4/x1. */ - pcie-controller { + pciec: pcie-controller@82000000 { compatible = "marvell,armada-xp-pcie"; status = "disabled"; device_type = "pci"; @@ -150,7 +150,7 @@ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -167,7 +167,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -184,7 +184,7 @@ status = "disabled"; }; - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -201,7 +201,7 @@ status = "disabled"; }; - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -218,7 +218,7 @@ status = "disabled"; }; - pcie@5,0 { + pcie5: pcie@5,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; @@ -235,7 +235,7 @@ status = "disabled"; }; - pcie@6,0 { + pcie6: pcie@6,0 { device_type = "pci"; assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; @@ -252,7 +252,7 @@ status = "disabled"; }; - pcie@7,0 { + pcie7: pcie@7,0 { device_type = "pci"; assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; @@ -269,7 +269,7 @@ status = "disabled"; }; - pcie@8,0 { + pcie8: pcie@8,0 { device_type = "pci"; assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; @@ -286,7 +286,7 @@ status = "disabled"; }; - pcie@9,0 { + pcie9: pcie@9,0 { device_type = "pci"; assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; @@ -303,7 +303,7 @@ status = "disabled"; }; - pcie@10,0 { + pcie10: pcie@10,0 { device_type = "pci"; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; reg = <0x5000 0 0 0 0>; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index d19f44c70925..a2f0e789465d 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -56,7 +56,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x80000000>; /* 2GB */ }; @@ -67,28 +67,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* Connected to first Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to second Marvell 88SE9170 SATA controller */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Connected to Fresco Logic FL1009 USB 3.0 controller */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Intersil ISL12057 I2C RTC chip */ @@ -97,7 +75,6 @@ }; i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; clock-frequency = <400000>; status = "okay"; @@ -154,23 +131,19 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -295,6 +268,39 @@ }; }; +&pciec { + status = "okay"; + + /* Connected to first Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to second Marvell 88SE9170 SATA controller */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Connected to Fresco Logic FL1009 USB 3.0 controller */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; +}; + + &pinctrl { poweroff: poweroff { marvell,pins = "mpp42"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index ed3b889d16ce..b577c9fb03a4 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -57,7 +57,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ }; @@ -98,15 +98,6 @@ }; }; - pcie-controller { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { rtc@10300 { /* No crystal connected to the internal RTC */ @@ -148,31 +139,13 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + init { label = "Init Button"; linux,code = ; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; }; }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -240,6 +213,33 @@ }; }; +&pciec { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + &pinctrl { led_pins: led-pins-0 { marvell,pins = "mpp49", "mpp51", "mpp53"; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index ae286736b90a..e803da03146a 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -70,7 +70,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x40000000>; /* 1GB */ }; @@ -81,28 +81,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Seiko S-35390A below */ @@ -150,16 +128,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - ethernet@70000 { status = "okay"; pinctrl-0 = <&ge0_rgmii_pins>; @@ -186,7 +154,7 @@ &sata3_pwr_pin &sata4_pwr_pin>; pinctrl-names = "default"; - sata1_regulator: sata1-regulator { + sata1_regulator: sata1-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "SATA1 Power"; @@ -199,7 +167,7 @@ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - sata2_regulator: sata2-regulator { + sata2_regulator: sata2-regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "SATA2 Power"; @@ -212,7 +180,7 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - sata3_regulator: sata3-regulator { + sata3_regulator: sata3-regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "SATA3 Power"; @@ -225,7 +193,7 @@ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - sata4_regulator: sata4-regulator { + sata4_regulator: sata4-regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "SATA4 Power"; @@ -240,6 +208,39 @@ }; }; +&pciec { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + &pinctrl { sata1_pwr_pin: sata1-pwr-pin { marvell,pins = "mpp42"; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 4a5f99e65b51..5274e4ff5d62 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -53,6 +53,9 @@ #include "armada-370-xp.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; + model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; @@ -75,7 +78,7 @@ reg = <0x1400 0x500>; }; - L2: l2-cache { + L2: l2-cache@8000 { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; @@ -84,16 +87,6 @@ wt-override; }; - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - uart2: serial@12200 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart2_pins>; @@ -118,7 +111,7 @@ status = "disabled"; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; }; @@ -136,7 +129,7 @@ #clock-cells = <1>; }; - thermal@182b0 { + thermal: thermal@182b0 { compatible = "marvell,armadaxp-thermal"; reg = <0x182b0 0x4 0x184d0 0x4>; @@ -150,27 +143,6 @@ clocks = <&coreclk 1>; }; - interrupt-controller@20a00 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x20>; - }; - cpu-config@21000 { compatible = "marvell,armada-xp-cpu-config"; reg = <0x21000 0x8>; @@ -184,15 +156,7 @@ status = "disabled"; }; - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { + usb2: usb@52000 { compatible = "marvell,orion-ehci"; reg = <0x52000 0x500>; interrupts = <47>; @@ -200,7 +164,7 @@ status = "disabled"; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -228,7 +192,7 @@ compatible = "marvell,armada-xp-neta"; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,armada-xp-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; @@ -248,7 +212,7 @@ status = "disabled"; }; - xor@f0900 { + xor0: xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 0xF0B00 0x100>; @@ -309,6 +273,44 @@ }; }; +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +}; + +&i2c1 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + &pinctrl { ge0_gmii_pins: ge0-gmii-pins { marvell,pins = diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts index f823ed382ac7..9dfe845694cf 100644 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ b/arch/arm/boot/dts/artpec6-devboard.dts @@ -46,6 +46,10 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + ðernet { status = "okay"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3489019cc0dc..767cbe8d8557 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -67,7 +67,7 @@ }; }; - syscon { + syscon: syscon@f8000000 { compatible = "axis,artpec6-syscon", "syscon"; reg = <0xf8000000 0x48>; }; @@ -154,6 +154,33 @@ interrupt-parent = <&intc>; }; + pcie: pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x2000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + amba@0 { compatible = "simple-bus"; #address-cells = <0x1>; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index a92c6e0ca854..b5a5a91bc2ef 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -12,8 +12,8 @@ #include "sama5d4.dtsi" / { - model = "DENX MA5D4"; - compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; + model = "Aries/DENX MA5D4"; + compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; memory { reg = <0x20000000 0x10000000>; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index eac4ea2744cc..84be29f38dae 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -13,8 +13,8 @@ #include "at91-sama5d4_ma5d4.dtsi" / { - model = "DENX MA5D4EVK"; - compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; + model = "Aries/DENX MA5D4EVK"; + compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; chosen { stdout-path = "serial3:115200n8"; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 4e913c2ccb79..f057e0b15a6f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -481,8 +481,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PA31 periph with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index a3e363d79122..9e035b21e1b6 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -412,8 +412,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PB15 periph with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 2c87f58448e7..b2578feceb08 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -174,14 +174,14 @@ label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; - gpio-key,wakeup; + wakeup-source; }; btn4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <0x104>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 32752d7883f1..3fe77c38bd0d 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -302,8 +302,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - , - ; + , + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index aeb1a36373f4..a1888f6d892b 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -412,8 +412,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PC31 periph with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index b3501ae2a3bd..e567d5fd3f9d 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -478,8 +478,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PB13 periph A */ + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 3b3eb3edcb47..f43d7695352d 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -500,8 +500,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PA10 periph with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 70adf940d98c..f4c129a98f17 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -438,8 +438,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - , - ; + , + ; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index ed4e4bd8a8f1..f66bae925705 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -460,8 +460,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PA10 periph A with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index fabc9f36c408..8833a4c3cd96 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -91,6 +91,13 @@ #address-cells = <1>; #size-cells = <1>; + otp: otp@0301c800 { + compatible = "brcm,ocotp"; + reg = <0x0301c800 0x2c>; + brcm,ocotp-size = <2048>; + status = "disabled"; + }; + pcie_phy: phy@0301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; @@ -108,12 +115,21 @@ }; }; - pinctrl: pinctrl@0x0301d0c8 { + pinctrl: pinctrl@0301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, <0x0301d24c 0x2c>; }; + mailbox: mailbox@03024024 { + compatible = "brcm,iproc-mailbox"; + reg = <0x03024024 0x40>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-controller; + #mbox-cells = <1>; + }; + gpio_crmu: gpio@03024800 { compatible = "brcm,cygnus-crmu-gpio"; reg = <0x03024800 0x50>, @@ -121,6 +137,9 @@ ngpios = <6>; #gpio-cells = <2>; gpio-controller; + interrupt-controller; + interrupt-parent = <&mailbox>; + interrupts = <0>; }; i2c0: i2c@18008000 { diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 7c9e0fae9bb9..b6142bda661e 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -160,7 +160,7 @@ axi { compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011ba08>; + ranges = <0x00000000 0x18000000 0x0011c40a>; #address-cells = <1>; #size-cells = <1>; @@ -241,6 +241,16 @@ brcm,nand-has-wp; }; + gpiob: gpio@30000 { + compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = ; + }; + pwm: pwm@31000 { compatible = "brcm,iproc-pwm"; reg = <0x31000 0x28>; @@ -254,6 +264,35 @@ reg = <0x33000 0x14>; }; + qspi: qspi@27200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + ccbtimer0: timer@34000 { compatible = "arm,sp804"; reg = <0x34000 0x1000>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index f7f9db355d98..d0704540db6b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -22,7 +22,72 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + /* + * This is based on the unreleased schematic for the Model A+. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "USB_LIMIT", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 8be102f5d826..46d078e29017 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -15,7 +15,74 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "CAM_GPIO0", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ i2s_alt2: i2s_alt2 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 35cde65c975e..432088ebb0a1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -23,7 +23,73 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + /* + * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf + * RPI-BPLUS sheet 1 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "LAN_RUN", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "USB_LIMIT", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "ETHCLK", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 84df85ea6296..4133bc2cd9be 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -16,7 +16,73 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; + /* + * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf + * RPI00022 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_CLK", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "CAM_GPIO", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ i2s_alt2: i2s_alt2 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 8e626a80fe24..4d56fe3006b0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -16,7 +16,74 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &alt3>; + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_GPIO1", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "CAM_GPIO0", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; }; &hdmi { diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 60e359fafc5b..cc8b832c4c78 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -26,7 +26,72 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "NC", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "NC", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index e9b47b2bbc33..6ddf7dfe3f72 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -39,22 +39,21 @@ }; alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; + brcm,pins = <4 5 7 8 9 10 11 14 15>; brcm,function = ; }; - - alt3: alt3 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_gpio0>; status = "okay"; clock-frequency = <100000>; }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_gpio2>; status = "okay"; clock-frequency = <100000>; }; @@ -64,11 +63,15 @@ }; &sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio48>; status = "okay"; bus-width = <4>; }; &pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index a78759e73710..0890d97e674d 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -23,3 +23,9 @@ }; }; }; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2835-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 39dccf62ac96..bf19e8cfb9e6 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -27,7 +27,7 @@ }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 9d0651d8f373..519a44f5d25a 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -76,3 +76,9 @@ interrupt-parent = <&local_intc>; interrupts = <8>; }; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2836-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 46d46d894a44..9a44da190897 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -104,7 +104,7 @@ reg = <0x7e104000 0x10>; }; - mailbox: mailbox@7e00b800 { + mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; interrupts = <0 1>; @@ -132,6 +132,209 @@ interrupt-controller; #interrupt-cells = <2>; + + /* Defines pin muxing groups according to + * BCM2835-ARM-Peripherals.pdf page 102. + * + * While each pin can have its mux selected + * for various functions individually, some + * groups only make sense to switch to a + * particular function together. + */ + dpi_gpio0: dpi_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio22: emmc_gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio34: emmc_gpio34 { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = ; + brcm,pull = ; + }; + emmc_gpio48: emmc_gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + gpclk0_gpio4: gpclk0_gpio4 { + brcm,pins = <4>; + brcm,function = ; + }; + gpclk1_gpio5: gpclk1_gpio5 { + brcm,pins = <5>; + brcm,function = ; + }; + gpclk1_gpio42: gpclk1_gpio42 { + brcm,pins = <42>; + brcm,function = ; + }; + gpclk1_gpio44: gpclk1_gpio44 { + brcm,pins = <44>; + brcm,function = ; + }; + gpclk2_gpio6: gpclk2_gpio6 { + brcm,pins = <6>; + brcm,function = ; + }; + gpclk2_gpio43: gpclk2_gpio43 { + brcm,pins = <43>; + brcm,function = ; + }; + + i2c0_gpio0: i2c0_gpio0 { + brcm,pins = <0 1>; + brcm,function = ; + }; + i2c0_gpio32: i2c0_gpio32 { + brcm,pins = <32 34>; + brcm,function = ; + }; + i2c0_gpio44: i2c0_gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + i2c1_gpio2: i2c1_gpio2 { + brcm,pins = <2 3>; + brcm,function = ; + }; + i2c1_gpio44: i2c1_gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + i2c_slave_gpio18: i2c_slave_gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + + jtag_gpio4: jtag_gpio4 { + brcm,pins = <4 5 6 12 13>; + brcm,function = ; + }; + jtag_gpio22: jtag_gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + + pcm_gpio18: pcm_gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + pcm_gpio28: pcm_gpio28 { + brcm,pins = <28 29 30 31>; + brcm,function = ; + }; + + pwm0_gpio12: pwm0_gpio12 { + brcm,pins = <12>; + brcm,function = ; + }; + pwm0_gpio18: pwm0_gpio18 { + brcm,pins = <18>; + brcm,function = ; + }; + pwm0_gpio40: pwm0_gpio40 { + brcm,pins = <40>; + brcm,function = ; + }; + pwm1_gpio13: pwm1_gpio13 { + brcm,pins = <13>; + brcm,function = ; + }; + pwm1_gpio19: pwm1_gpio19 { + brcm,pins = <19>; + brcm,function = ; + }; + pwm1_gpio41: pwm1_gpio41 { + brcm,pins = <41>; + brcm,function = ; + }; + pwm1_gpio45: pwm1_gpio45 { + brcm,pins = <45>; + brcm,function = ; + }; + + sdhost_gpio48: sdhost_gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + spi0_gpio7: spi0_gpio7 { + brcm,pins = <7 8 9 10 11>; + brcm,function = ; + }; + spi0_gpio35: spi0_gpio35 { + brcm,pins = <35 36 37 38 39>; + brcm,function = ; + }; + spi1_gpio16: spi1_gpio16 { + brcm,pins = <16 17 18 19 20 21>; + brcm,function = ; + }; + spi2_gpio40: spi2_gpio40 { + brcm,pins = <40 41 42 43 44 45>; + brcm,function = ; + }; + + uart0_gpio14: uart0_gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + /* Separate from the uart0_gpio14 group + * because it conflicts with spi1_gpio16, and + * people often run uart0 on the two pins + * without flow contrl. + */ + uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart0_gpio30: uart0_gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + }; + uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + }; + + uart1_gpio14: uart1_gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart1_gpio32: uart1_gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + }; + uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + }; + uart1_gpio36: uart1_gpio36 { + brcm,pins = <36 37 38 39>; + brcm,function = ; + }; + uart1_gpio40: uart1_gpio40 { + brcm,pins = <40 41>; + brcm,function = ; + }; + uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { + brcm,pins = <42 43>; + brcm,function = ; + }; }; uart0: serial@7e201000 { @@ -187,6 +390,13 @@ interrupts = <2 14>; /* pwa1 */ }; + thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; + status = "disabled"; + }; + aux: aux@0x7e215000 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts new file mode 100644 index 000000000000..35e6ed6a3ef7 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "luxul,xap-1510v1", "brcm,bcm4708"; + model = "Luxul XAP-1510 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 8ade7def2e8a..eac0f52e5ebd 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 0653e7ef248c..aab39c9864da 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index a22ed144040b..fd38d2aa3521 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index ca181516c28a..92f8a7219e98 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { @@ -107,6 +107,10 @@ }; }; +&uart0 { + status = "okay"; +}; + &usb2 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts new file mode 100644 index 000000000000..9a92c24ac2d8 --- /dev/null +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4709.dtsi" + +/ { + compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; + model = "TP-LINK Archer C9 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-blue { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi new file mode 100644 index 000000000000..f03976597a6d --- /dev/null +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include "bcm4708.dtsi" + +&uart0 { + clock-frequency = <125000000>; +}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index c8c0b3616935..661348dbb7ce 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm47094.dtsi" #include "bcm5301x-nand-cs0-bch1.dtsi" / { @@ -107,7 +107,6 @@ &uart0 { status = "okay"; - clock-frequency = <125000000>; }; &usb3 { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts new file mode 100644 index 000000000000..169b35fe5651 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWR-3100 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + lan3 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan4 { + label = "bcm53xx:green:lan0"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan1 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + 2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts new file mode 100644 index 000000000000..521b4155de60 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; + model = "Netgear R8500"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi new file mode 100644 index 000000000000..4f09aa0114e6 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include "bcm4708.dtsi" + +/ { + usb3_phy: usb3-phy { + compatible = "brcm,ns-bx-usb3-phy"; + }; +}; + +&uart0 { + clock-frequency = <125000000>; +}; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts new file mode 100644 index 000000000000..4403ae8790c2 --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; + model = "Tenda AC9"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:blue:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi new file mode 100644 index 000000000000..b4e875df9528 --- /dev/null +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ae4b3880616d..f09a2bb08979 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -149,6 +149,13 @@ clock-names = "phy-ref-clk"; }; + usb3_phy: usb3-phy { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x18105000 0x1000>, <0x18003000 0x1000>; + reg-names = "dmp", "ccb-mii"; + #phy-cells = <0>; + }; + axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi new file mode 100644 index 000000000000..e2c496a96c32 --- /dev/null +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + chosen { + stdout-path = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + mpcore { + compatible = "simple-bus"; + ranges = <0x00000000 0x18310000 0x00008000>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x0100>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + alp: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 0 */ + <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 1 */ + <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + compatible = "simple-bus"; + reg = <0x00000000 0x1000>; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + gpio-controller; + #gpio-cells = <2>; + + uart0: serial@0300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&alp>; + status = "okay"; + }; + }; + + usb2: usb2@4000 { + reg = <0x4000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + ehci: ehci@4000 { + compatible = "generic-ehci"; + reg = <0x4000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + ohci: ohci@d000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0xd000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac0: ethernet@5000 { + reg = <0x5000 0x1000>; + }; + + gmac1: ethernet@b000 { + reg = <0xb000 0x1000>; + }; + + pmu@12000 { + compatible = "simple-mfd", "syscon"; + reg = <0x00012000 0x00001000>; + + ilp: ilp { + compatible = "brcm,bcm53573-ilp"; + clocks = <&alp>; + #clock-cells = <0>; + clock-output-names = "ilp"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 05c5f98c8782..59d96fb91583 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -139,3 +139,37 @@ groups = "nand_grp"; }; }; + +&qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index f485308840ab..57aa5f8a7c77 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -48,7 +48,7 @@ reg = <0x00000000 0x80000000>; }; - choosen { + chosen { bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; @@ -58,7 +58,7 @@ #address-cells = <1>; #size-cells = <0>; - reg_usb0_vbus: regulator@0 { + reg_usb0_vbus: regulator_usb0 { compatible = "regulator-fixed"; regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; @@ -67,7 +67,7 @@ enable-active-high; }; - reg_usb1_vbus: regulator@1 { + reg_usb1_vbus: regulator_usb1 { compatible = "regulator-fixed"; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; @@ -76,7 +76,7 @@ enable-active-high; }; - reg_usb2_vbus: regulator@2 { + reg_usb2_vbus: regulator_usb2 { compatible = "regulator-fixed"; regulator-name = "usb2_vbus"; regulator-min-microvolt = <5000000>; @@ -85,7 +85,7 @@ enable-active-high; }; - reg_sdio1_vmmc: regulator@3 { + reg_sdio1_vmmc: regulator_sdio1_vmmc { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -95,7 +95,7 @@ gpio = <&portb 21 GPIO_ACTIVE_HIGH>; }; - reg_sdio1_vqmmc: regulator@4 { + reg_sdio1_vqmmc: regulator_sido1_vqmmc { compatible = "regulator-gpio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts new file mode 100644 index 000000000000..bfde32e37123 --- /dev/null +++ b/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts @@ -0,0 +1,94 @@ +/* + * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 + * + * Copyright (C) 2016 Neil Armstrong + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox820.dtsi" + +/ { + model = "Cloud Engines PogoPlug Series 3"; + + compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; + }; + + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "pogoplug:blue"; + gpios = <&gpio0 2 0>; + default-state = "keep"; + }; + + orange { + label = "pogoplug:orange"; + gpios = <&gpio1 16 1>; + default-state = "keep"; + }; + + green { + label = "pogoplug:green"; + gpios = <&gpio1 17 1>; + default-state = "keep"; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&nandc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "hamming"; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00e00000>; + read-only; + }; + + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; + }; + }; +}; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 7b8ab21fed6c..afcb4821deb1 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -13,6 +13,7 @@ aliases { serial2 = &serial2; + ethernet0 = ð0; }; chosen { @@ -122,7 +123,7 @@ bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -158,6 +159,14 @@ rx-num-evt = <32>; }; +&usb_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + &aemif { pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; @@ -219,3 +228,11 @@ }; }; }; + +&prictrl { + status = "okay"; +}; + +&memctrl { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index f79e1b91c680..104155d12c2f 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -36,6 +36,7 @@ reg = <0x14120 0x50>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; @@ -186,7 +187,43 @@ 0xc 0x88888888 0xffffffff >; }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + /* + * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], + * LCD_D[6], LCD_D[7] + */ + 0x40 0x22222200 0xffffff00 + /* + * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], + * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] + */ + 0x44 0x22222222 0xffffffff + /* LCD_D[8], LCD_D[9] */ + 0x48 0x00000022 0x000000ff + /* LCD_PCLK */ + 0x48 0x02000000 0x0f000000 + /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ + 0x4c 0x02000022 0x0f0000ff + >; + }; + + }; + prictrl: priority-controller@14110 { + compatible = "ti,da850-mstpri"; + reg = <0x14110 0x0c>; + status = "disabled"; + }; + cfgchip: chip-controller@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + usb_phy: usb-phy { + compatible = "ti,da830-usb-phy"; + #phy-cells = <1>; + status = "disabled"; + }; }; edma0: edma@0 { compatible = "ti,edma3-tpcc"; @@ -280,6 +317,8 @@ mmc0: mmc@40000 { compatible = "ti,da830-mmc"; reg = <0x40000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; interrupts = <16>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; @@ -288,6 +327,8 @@ mmc1: mmc@21b000 { compatible = "ti,da830-mmc"; reg = <0x21b000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; interrupts = <72>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; @@ -336,6 +377,8 @@ num-cs = <6>; ti,davinci-spi-intr-line = <1>; interrupts = <20>; + dmas = <&edma0 14 0>, <&edma0 15 0>; + dma-names = "rx", "tx"; status = "disabled"; }; spi1: spi@30e000 { @@ -350,6 +393,16 @@ dma-names = "rx", "tx"; status = "disabled"; }; + usb0: usb@200000 { + compatible = "ti,da830-musb"; + reg = <0x200000 0x10000>; + interrupts = <58>; + interrupt-names = "mc"; + dr_mode = "otg"; + phys = <&usb_phy 0>; + phy-names = "usb-phy"; + status = "disabled"; + }; mdio: mdio@224000 { compatible = "ti,davinci_mdio"; #address-cells = <1>; @@ -386,6 +439,11 @@ ti,davinci-gpio-unbanked = <0>; status = "disabled"; }; + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + status = "disabled"; + }; mcasp0: mcasp@100000 { compatible = "ti,da830-mcasp-audio"; @@ -399,6 +457,13 @@ <&edma0 0 1>; dma-names = "tx", "rx"; }; + + display: display@213000 { + compatible = "ti,da850-tilcdc"; + reg = <0x213000 0x1000>; + interrupts = <52>; + status = "disabled"; + }; }; aemif: aemif@68000000 { compatible = "ti,da850-aemif"; @@ -410,4 +475,9 @@ 1 0 0x68000000 0x00008000>; status = "disabled"; }; + memctrl: memory-controller@b0000000 { + compatible = "ti,da850-ddr-controller"; + reg = <0xb0000000 0xe8>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index ff90a6ce6bdc..81b8cecb5820 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -12,6 +12,7 @@ interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c1; @@ -373,6 +374,7 @@ reg = <0x800 0x438>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x307ff>; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index f1e0f771ff29..6db652ae9bd5 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -12,6 +12,7 @@ interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c1; @@ -83,6 +84,7 @@ reg = <0x48140000 0x21000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x48140000 0x21000>; dm816x_pinmux: pinmux@800 { @@ -90,6 +92,7 @@ reg = <0x800 0x50a>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xf>; }; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d4fcd68f6349..1faf24acd521 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -18,6 +18,7 @@ compatible = "ti,dra7xx"; interrupt-parent = <&crossbar_mpu>; + chosen { }; aliases { i2c0 = &i2c1; @@ -171,6 +172,7 @@ reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts new file mode 100644 index 000000000000..2b9a5a8d69ad --- /dev/null +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra72-evm-common.dtsi" +#include + +/ { + compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; + model = "TI DRA718 EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; + + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { + compatible = "regulator-gpio"; + + regulator-name = "vddshv8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + vin-supply = <&evm_5v0>; + + gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3000000 0x1>; + }; + + poweroff: gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + lp8733: lp8733@60 { + compatible = "ti,lp8733"; + reg = <0x60>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&evm_5v0>; + ldo1-in-supply =<&evm_5v0>; + + lp8733_regulators: regulators { + lp8733_buck0_reg: buck0 { + /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */ + regulator-name = "lp8733-buck0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8733_buck1_reg: buck1 { + /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */ + regulator-name = "lp8733-buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8733_ldo0_reg: ldo0 { + /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */ + regulator-name = "lp8733-ldo0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lp8733_ldo1_reg: ldo1 { + /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */ + regulator-name = "lp8733-ldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + lp8732: lp8732@61 { + compatible = "ti,lp8732"; + reg = <0x61>; + + buck0-in-supply =<&vsys_3v3>; + buck1-in-supply =<&vsys_3v3>; + ldo0-in-supply =<&vsys_3v3>; + ldo1-in-supply =<&vsys_3v3>; + + lp8732_regulators: regulators { + lp8732_buck0_reg: buck0 { + /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */ + regulator-name = "lp8732-buck0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + lp8732_buck1_reg: buck1 { + /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */ + regulator-name = "lp8732-buck1"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo0_reg: ldo0 { + /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */ + regulator-name = "lp8732-ldo0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + lp8732_ldo1_reg: ldo1 { + /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */ + regulator-name = "lp8732-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio7>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; +}; + +&pcf_hdmi { + p0 { + /* + * PM_OEn to High: Disable routing I2C3 to PM_I2C + * With this PM_SEL(p3) should not matter + */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pm_oe_n"; + }; +}; + +&mmc1 { + vmmc_aux-supply = <&vpo_sd_1v8_3v3>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,impedance-control = <0x1f>; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,impedance-control = <0x1f>; + }; +}; + +/* No Sata on this device */ +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +/* No RTC on this device */ +&rtc { + status = "disabled"; +}; + +&usb2_phy1 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&usb2_phy2 { + phy-supply = <&lp8733_ldo1_reg>; +}; + +&dss { + /* Supplied by VDA_1V8_PLL */ + vdda_video-supply = <&lp8732_ldo0_reg>; +}; + +&hdmi { + /* Supplied by VDA_1V8_PHY */ + vdda_video-supply = <&lp8732_ldo1_reg>; +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index c94d8d64710d..e50fbeea96e0 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -18,11 +18,49 @@ display0 = &hdmi0; }; + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + evm_5v0: fixedregulator-evm5v0 { + /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "evm_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ + /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + evm_3v3_sw: fixedregulator-evm_3v3 { + /* TPS22965DSG */ compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; }; aic_dvdd: fixedregulator-aic_dvdd { @@ -39,6 +77,7 @@ regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&evm_3v3_sw>; enable-active-high; gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; }; @@ -69,9 +108,6 @@ tpd12s015: encoder { compatible = "ti,tpd12s015"; - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ @@ -134,72 +170,6 @@ }; &dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ @@ -240,161 +210,12 @@ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ - >; - }; - - mcasp3_pins: pinmux_mcasp3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) - >; - }; }; &i2c1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = ; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - tps65917_regulators: regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; @@ -423,8 +244,6 @@ &i2c5 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { @@ -462,8 +281,6 @@ &gpmc { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: @@ -548,14 +365,6 @@ }; }; -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - &omap_dwc3_1 { extcon = <&extcon_usb1>; }; @@ -566,14 +375,10 @@ &usb1 { dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; }; &usb2 { dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; }; &mmc1 { @@ -581,7 +386,6 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode @@ -603,71 +407,8 @@ max-frequency = <192000000>; }; -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; -}; - &mac { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; }; &dcan1 { @@ -741,16 +482,11 @@ &dss { status = "ok"; - - vdda_video-supply = <&ldo5_reg>; }; &hdmi { status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; @@ -759,9 +495,6 @@ }; &atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_gfclk_mux>, <&dpll_abe_ck>, @@ -780,9 +513,6 @@ &mcasp3 { #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clock-parents = <&atl_clkin2_ck>; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 3b23b32e1b30..c3d939c9666c 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -17,17 +17,22 @@ }; }; -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> VDDA_1V8_PHY2 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ }; }; +#include "dra72-evm-tps65917.dtsi" + +&ldo2_reg { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-always-on; + regulator-boot-on; +}; + &hdmi { vdda-supply = <&ldo2_reg>; }; diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi new file mode 100644 index 000000000000..e6df676886c0 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf + */ + +&tps65917 { + compatible = "ti,tps65917"; + + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + smps1-in-supply = <&vsys_3v3>; + smps2-in-supply = <&vsys_3v3>; + smps3-in-supply = <&vsys_3v3>; + smps4-in-supply = <&vsys_3v3>; + smps5-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + ldo3-in-supply = <&vsys_3v3>; + ldo4-in-supply = <&evm_5v0>; + ldo5-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&dss { + vdda_video-supply = <&ldo5_reg>; +}; + +&mmc1 { + vmmc_aux-supply = <&ldo1_reg>; +}; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index e3a9b6985693..cd9c4ff12654 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -15,16 +15,16 @@ }; }; -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-allow-bypass; +&i2c1 { + tps65917: tps65917@58 { + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ }; }; +#include "dra72-evm-tps65917.dtsi" + &hdmi { vdda-supply = <&ldo3_reg>; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index cd119400f440..0124faf175c8 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -8,13 +8,14 @@ * kind, whether express or implied. */ -#include "skeleton.dtsi" #include #include / { compatible = "renesas,emev2"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { gpio0 = &gpio0; diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index be4d6aa379f3..4bd2ee87124e 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -28,7 +28,7 @@ vqmmc-supply = <&ldo3_reg>; card-detect-delay = <200>; clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + max-frequency = <100000000>; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index a70819b1b739..59c89d7662a8 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -310,7 +310,7 @@ card-detect-delay = <200>; vmmc-supply = <&ldo12_reg>; clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + max-frequency = <100000000>; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 66f04f6ba6bb..cccfe4b791d1 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -435,7 +435,7 @@ card-detect-delay = <200>; vmmc-supply = <&vemmc_reg>; clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + max-frequency = <100000000>; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index ec331169c3d9..a149f148e659 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -362,8 +362,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -373,8 +379,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 3967ee5f7752..548413e23c47 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -649,7 +649,7 @@ card-detect-delay = <200>; vmmc-supply = <&ldo12_reg>; clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + max-frequency = <100000000>; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index e9d2556c0dfd..ba17ee1eb749 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -20,6 +20,8 @@ #include "exynos4-cpu-thermal.dtsi" #include "exynos-syscon-restart.dtsi" #include +#include +#include / { compatible = "samsung,exynos3250"; @@ -211,7 +213,8 @@ rtc: rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; + interrupts = , + ; interrupt-parent = <&pmu_system_controller>; status = "disabled"; }; @@ -219,7 +222,7 @@ tmu: tmu@100C0000 { compatible = "samsung,exynos3250-tmu"; reg = <0x100C0000 0x100>; - interrupts = <0 216 0>; + interrupts = ; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -234,14 +237,21 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; mct@10050000 { compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + interrupts = , + , + , + , + , + , + , + ; clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; clock-names = "fin_pll", "mct"; }; @@ -249,24 +259,24 @@ pinctrl_1: pinctrl@11000000 { compatible = "samsung,exynos3250-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; + interrupts = ; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = <0 48 0>; + interrupts = ; }; }; pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos3250-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; + interrupts = ; }; jpeg: codec@11830000 { compatible = "samsung,exynos3250-jpeg"; reg = <0x11830000 0x1000>; - interrupts = <0 171 0>; + interrupts = ; clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; clock-names = "jpeg", "sclk"; power-domains = <&pd_cam>; @@ -280,7 +290,8 @@ sysmmu_jpeg: sysmmu@11A60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11a60000 0x1000>; - interrupts = <0 156 0>, <0 161 0>; + interrupts = , + ; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; power-domains = <&pd_cam>; @@ -291,7 +302,9 @@ compatible = "samsung,exynos3250-fimd"; reg = <0x11c00000 0x30000>; interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; + interrupts = , + , + ; clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; power-domains = <&pd_lcd0>; @@ -303,7 +316,7 @@ dsi_0: dsi@11C80000 { compatible = "samsung,exynos3250-mipi-dsi"; reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; + interrupts = ; samsung,phy-type = <0>; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; @@ -318,7 +331,8 @@ sysmmu_fimd0: sysmmu@11E20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; + interrupts = , + ; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; power-domains = <&pd_lcd0>; @@ -328,7 +342,7 @@ hsotg: hsotg@12480000 { compatible = "snps,dwc2"; reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; + interrupts = ; clocks = <&cmu CLK_USBOTG>; clock-names = "otg"; phys = <&exynos_usbphy 0>; @@ -339,7 +353,7 @@ mshc_0: mshc@12510000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; + interrupts = ; clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -351,7 +365,7 @@ mshc_1: mshc@12520000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; + interrupts = ; clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -363,7 +377,7 @@ mshc_2: mshc@12530000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; + interrupts = ; clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; @@ -391,7 +405,7 @@ pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; + interrupts = ; clocks = <&cmu CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -402,7 +416,7 @@ pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; + interrupts = ; clocks = <&cmu CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -415,7 +429,7 @@ compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2"; reg = <0x126C0000 0x100>; - interrupts = <0 137 0>; + interrupts = ; clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; #io-channel-cells = <1>; @@ -427,7 +441,7 @@ mfc: codec@13400000 { compatible = "samsung,mfc-v7"; reg = <0x13400000 0x10000>; - interrupts = <0 102 0>; + interrupts = ; clock-names = "mfc", "sclk_mfc"; clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; power-domains = <&pd_mfc>; @@ -437,7 +451,8 @@ sysmmu_mfc: sysmmu@13620000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13620000 0x1000>; - interrupts = <0 96 0>, <0 98 0>; + interrupts = , + ; clock-names = "sysmmu", "master"; clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; power-domains = <&pd_mfc>; @@ -447,7 +462,7 @@ serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; - interrupts = <0 109 0>; + interrupts = ; clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -458,7 +473,7 @@ serial_1: serial@13810000 { compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; - interrupts = <0 110 0>; + interrupts = ; clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -469,7 +484,7 @@ serial_2: serial@13820000 { compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; - interrupts = <0 111 0>; + interrupts = ; clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; @@ -482,7 +497,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; - interrupts = <0 113 0>; + interrupts = ; clocks = <&cmu CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; @@ -495,7 +510,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; - interrupts = <0 114 0>; + interrupts = ; clocks = <&cmu CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; @@ -508,7 +523,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; - interrupts = <0 115 0>; + interrupts = ; clocks = <&cmu CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; @@ -521,7 +536,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; - interrupts = <0 116 0>; + interrupts = ; clocks = <&cmu CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; @@ -534,7 +549,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; + interrupts = ; clocks = <&cmu CLK_I2C4>; clock-names = "i2c"; pinctrl-names = "default"; @@ -547,7 +562,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; + interrupts = ; clocks = <&cmu CLK_I2C5>; clock-names = "i2c"; pinctrl-names = "default"; @@ -560,7 +575,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; + interrupts = ; clocks = <&cmu CLK_I2C6>; clock-names = "i2c"; pinctrl-names = "default"; @@ -573,7 +588,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; + interrupts = ; clocks = <&cmu CLK_I2C7>; clock-names = "i2c"; pinctrl-names = "default"; @@ -584,7 +599,7 @@ spi_0: spi@13920000 { compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; - interrupts = <0 121 0>; + interrupts = ; dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -600,7 +615,7 @@ spi_1: spi@13930000 { compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; - interrupts = <0 122 0>; + interrupts = ; dmas = <&pdma1 7>, <&pdma1 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -616,7 +631,7 @@ i2s2: i2s@13970000 { compatible = "samsung,s3c6410-i2s"; reg = <0x13970000 0x100>; - interrupts = <0 126 0>; + interrupts = ; clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; clock-names = "iis", "i2s_opclk0"; dmas = <&pdma0 14>, <&pdma0 13>; @@ -629,15 +644,19 @@ pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; + interrupts = , + , + , + , + ; #pwm-cells = <3>; status = "disabled"; }; pmu { compatible = "arm,cortex-a7-pmu"; - interrupts = <0 18 0>, <0 19 0>; + interrupts = , + ; }; ppmu_dmc0: ppmu_dmc0@106a0000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5f034eb5a5e2..c64737baa45e 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -21,6 +21,8 @@ #include #include +#include +#include #include "exynos-syscon-restart.dtsi" / { @@ -78,6 +80,11 @@ reg = <0x10000000 0x100>; }; + scu: snoop-control-unit@10500000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x10500000 0x2000>; + }; + memory-controller@12570000 { compatible = "samsung,exynos4210-srom"; reg = <0x12570000 0x14>; @@ -168,7 +175,7 @@ dsi_0: dsi@11C80000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; - interrupts = <0 79 0>; + interrupts = ; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; phy-names = "dsim"; @@ -191,7 +198,7 @@ fimc_0: fimc@11800000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11800000 0x1000>; - interrupts = <0 84 0>; + interrupts = ; clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -203,7 +210,7 @@ fimc_1: fimc@11810000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11810000 0x1000>; - interrupts = <0 85 0>; + interrupts = ; clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -215,7 +222,7 @@ fimc_2: fimc@11820000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11820000 0x1000>; - interrupts = <0 86 0>; + interrupts = ; clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -227,7 +234,7 @@ fimc_3: fimc@11830000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11830000 0x1000>; - interrupts = <0 87 0>; + interrupts = ; clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; @@ -239,7 +246,7 @@ csis_0: csis@11880000 { compatible = "samsung,exynos4210-csis"; reg = <0x11880000 0x4000>; - interrupts = <0 78 0>; + interrupts = ; clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; clock-names = "csis", "sclk_csis"; bus-width = <4>; @@ -254,7 +261,7 @@ csis_1: csis@11890000 { compatible = "samsung,exynos4210-csis"; reg = <0x11890000 0x4000>; - interrupts = <0 80 0>; + interrupts = ; clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; clock-names = "csis", "sclk_csis"; bus-width = <2>; @@ -270,7 +277,7 @@ watchdog: watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; - interrupts = <0 43 0>; + interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; status = "disabled"; @@ -280,7 +287,8 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupt-parent = <&pmu_system_controller>; - interrupts = <0 44 0>, <0 45 0>; + interrupts = , + ; clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -289,7 +297,7 @@ keypad: keypad@100A0000 { compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; - interrupts = <0 109 0>; + interrupts = ; clocks = <&clock CLK_KEYIF>; clock-names = "keypad"; status = "disabled"; @@ -298,7 +306,7 @@ sdhci_0: sdhci@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; - interrupts = <0 73 0>; + interrupts = ; clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -307,7 +315,7 @@ sdhci_1: sdhci@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; - interrupts = <0 74 0>; + interrupts = ; clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -316,7 +324,7 @@ sdhci_2: sdhci@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; - interrupts = <0 75 0>; + interrupts = ; clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -325,7 +333,7 @@ sdhci_3: sdhci@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; - interrupts = <0 76 0>; + interrupts = ; clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; @@ -344,7 +352,7 @@ hsotg: hsotg@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; - interrupts = <0 71 0>; + interrupts = ; clocks = <&clock CLK_USB_DEVICE>; clock-names = "otg"; phys = <&exynos_usbphy 0>; @@ -355,7 +363,7 @@ ehci: ehci@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; - interrupts = <0 70 0>; + interrupts = ; clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; @@ -381,7 +389,7 @@ ohci: ohci@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; - interrupts = <0 70 0>; + interrupts = ; clocks = <&clock CLK_USB_HOST>; clock-names = "usbhost"; status = "disabled"; @@ -423,7 +431,7 @@ mfc: codec@13400000 { compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; + interrupts = ; power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; clock-names = "mfc", "sclk_mfc"; @@ -434,7 +442,7 @@ serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; - interrupts = <0 52 0>; + interrupts = ; clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma0 15>, <&pdma0 16>; @@ -445,7 +453,7 @@ serial_1: serial@13810000 { compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; - interrupts = <0 53 0>; + interrupts = ; clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma1 15>, <&pdma1 16>; @@ -456,7 +464,7 @@ serial_2: serial@13820000 { compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; - interrupts = <0 54 0>; + interrupts = ; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma0 17>, <&pdma0 18>; @@ -467,7 +475,7 @@ serial_3: serial@13830000 { compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; - interrupts = <0 55 0>; + interrupts = ; clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; dmas = <&pdma1 17>, <&pdma1 18>; @@ -480,7 +488,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; - interrupts = <0 58 0>; + interrupts = ; clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; @@ -493,7 +501,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; - interrupts = <0 59 0>; + interrupts = ; clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; @@ -506,7 +514,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; - interrupts = <0 60 0>; + interrupts = ; clocks = <&clock CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; @@ -519,7 +527,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; - interrupts = <0 61 0>; + interrupts = ; clocks = <&clock CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; @@ -532,7 +540,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; - interrupts = <0 62 0>; + interrupts = ; clocks = <&clock CLK_I2C4>; clock-names = "i2c"; pinctrl-names = "default"; @@ -545,7 +553,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; - interrupts = <0 63 0>; + interrupts = ; clocks = <&clock CLK_I2C5>; clock-names = "i2c"; pinctrl-names = "default"; @@ -558,7 +566,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; - interrupts = <0 64 0>; + interrupts = ; clocks = <&clock CLK_I2C6>; clock-names = "i2c"; pinctrl-names = "default"; @@ -571,7 +579,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; - interrupts = <0 65 0>; + interrupts = ; clocks = <&clock CLK_I2C7>; clock-names = "i2c"; pinctrl-names = "default"; @@ -584,7 +592,7 @@ #size-cells = <0>; compatible = "samsung,s3c2440-hdmiphy-i2c"; reg = <0x138E0000 0x100>; - interrupts = <0 93 0>; + interrupts = ; clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; @@ -598,7 +606,7 @@ spi_0: spi@13920000 { compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; - interrupts = <0 66 0>; + interrupts = ; dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -613,7 +621,7 @@ spi_1: spi@13930000 { compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; - interrupts = <0 67 0>; + interrupts = ; dmas = <&pdma1 7>, <&pdma1 6>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -628,7 +636,7 @@ spi_2: spi@13940000 { compatible = "samsung,exynos4210-spi"; reg = <0x13940000 0x100>; - interrupts = <0 68 0>; + interrupts = ; dmas = <&pdma0 9>, <&pdma0 8>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -643,7 +651,11 @@ pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; + interrupts = , + , + , + , + ; clocks = <&clock CLK_PWM>; clock-names = "timers"; #pwm-cells = <3>; @@ -660,7 +672,7 @@ pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; - interrupts = <0 35 0>; + interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -671,7 +683,7 @@ pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; - interrupts = <0 36 0>; + interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -682,7 +694,7 @@ mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; - interrupts = <0 34 0>; + interrupts = ; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -712,7 +724,7 @@ jpeg_codec: jpeg-codec@11840000 { compatible = "samsung,exynos4210-jpeg"; reg = <0x11840000 0x1000>; - interrupts = <0 88 0>; + interrupts = ; clocks = <&clock CLK_JPEG>; clock-names = "jpeg"; power-domains = <&pd_cam>; @@ -722,7 +734,7 @@ rotator: rotator@12810000 { compatible = "samsung,exynos4210-rotator"; reg = <0x12810000 0x64>; - interrupts = <0 83 0>; + interrupts = ; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -731,7 +743,7 @@ hdmi: hdmi@12D00000 { compatible = "samsung,exynos4210-hdmi"; reg = <0x12D00000 0x70000>; - interrupts = <0 92 0>; + interrupts = ; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, @@ -746,7 +758,7 @@ hdmicec: cec@100B0000 { compatible = "samsung,s5p-cec"; reg = <0x100B0000 0x200>; - interrupts = <0 114 0>; + interrupts = ; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -757,7 +769,7 @@ mixer: mixer@12C10000 { compatible = "samsung,exynos4210-mixer"; - interrupts = <0 91 0>; + interrupts = ; reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; power-domains = <&pd_tv>; iommus = <&sysmmu_tv>; @@ -984,7 +996,7 @@ sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = ; clocks = <&clock CLK_SSS>; clock-names = "secss"; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index d9b6d25e4abe..f280954b260a 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -537,8 +537,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -548,8 +554,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2d9b02967105..7f3a18c8f60f 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -109,12 +109,12 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &gic 0 69 0>, + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, <2 &combiner 12 6>, <3 &combiner 12 7>, - <4 &gic 0 42 0>, - <5 &gic 0 48 0>; + <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -127,18 +127,18 @@ pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; + interrupts = ; }; pinctrl_1: pinctrl@11000000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; + interrupts = ; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = ; }; }; @@ -182,7 +182,7 @@ g2d: g2d@12800000 { compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; + interrupts = ; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; power-domains = <&pd_lcd0>; @@ -424,10 +424,22 @@ &combiner { samsung,combiner-nr = <16>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; &mdma1 { diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts new file mode 100644 index 000000000000..76d87f397178 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -0,0 +1,240 @@ +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li + * + * Device tree source file for TOPEET iTop Exynos 4412 core board + * which is based on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include "exynos4412-itop-scp-core.dtsi" + +/ { + model = "TOPEET iTop 4412 Elite board based on Exynos4412"; + compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; + stdout-path = "serial2:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led2 { + label = "red:system"; + gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led3 { + label = "red:user"; + gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + home { + label = "GPIO Key Home"; + linux,code = ; + gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; + }; + + back { + label = "GPIO Key Back"; + linux,code = ; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + }; + + sleep { + label = "GPIO Key Sleep"; + linux,code = ; + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + }; + + vol-up { + label = "GPIO Key Vol+"; + linux,code = ; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + }; + + vol-down { + label = "GPIO Key Vol-"; + linux,code = ; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm-sound"; + + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, + <0>, + <112896000>, + <11289600>; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + system-clock-frequency = <11289600>; + }; + }; + + beep { + compatible = "pwm-beeper"; + pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>; + }; + + camera: camera { + pinctrl-0 = <&cam_port_a_clk_active>; + pinctrl-names = "default"; + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + +&ehci { + status = "okay"; + /* In order to reset USB ethernet */ + samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + + port@0 { + status = "okay"; + }; + + port@2 { + status = "okay"; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&hsotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>; + clock-names = "MCLK1"; + wlf,shared-lrclk; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; +}; + +&pinctrl_1 { + ether-reset { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + status = "okay"; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; + cap-sd-highspeed; + vmmc-supply = <&ldo23_reg>; + vqmmc-supply = <&ldo17_reg>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi new file mode 100644 index 000000000000..a36cd36a26b8 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -0,0 +1,501 @@ +/* + * TOPEET's Exynos4412 based itop board device tree source + * + * Copyright (c) 2016 SUMOMO Computer Association + * https://www.sumomo.mobi + * Randy Li + * + * Device tree source file for TOPEET iTop Exynos 4412 SCP package core + * board which is based on Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + firmware@0203F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>; + }; + }; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsic_reset>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767: s5m8767-pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + + s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>, + <&gpb 6 GPIO_ACTIVE_HIGH>, + <&gpb 7 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, + <&gpm3 6 GPIO_ACTIVE_HIGH>, + <&gpm3 7 GPIO_ACTIVE_HIGH>; + + /* VDD_ARM */ + s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>, + <1243750>, <1118750>, + <1068750>, <1012500>, + <956250>, <900000>; + /* VDD_INT */ + s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>, + <925000>, <925000>, + <887500>, <887500>, + <850000>, <850000>; + /* VDD_G3D */ + s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>, + <1025000>, <950000>, + <918750>, <900000>, + <875000>, <831250>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + /* SCP uses 1.5v, POP uses 1.2v */ + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M12"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo3_reg: LDO3 { + regulator-name = "VDDIOAP_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_LDO5"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD33_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD18_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_UOTG"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDIOPERI_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB02"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_USH"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDIOAP_MMC012_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + /* Used by HSIC */ + ldo18_reg: LDO18 { + regulator-name = "VDDIOPERI_28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_LDO19"; + op_mode = <0>; /* Always off Mode */ + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD28_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD28_AF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo22_reg: LDO22 { + regulator-name = "VDDA28_2M"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD28_TF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD33_A31"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD18_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD18_A31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo27_reg: LDO27 { + regulator-name = "GPS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; /* Normal Mode */ + }; + + ldo28_reg: LDO28 { + regulator-name = "DVDD12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; /* Normal Mode */ + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1456250>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_m12"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd12_5m"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck7_reg: BUCK7 { + regulator-name = "pvdd_buck7"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck8_reg: BUCK8 { + regulator-name = "pvdd_buck8"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck9_reg: BUCK9 { + regulator-name = "vddf28_emmc"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; /* Normal Mode */ + }; + }; + + s5m8767_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", + "s5m8767_cp", "s5m8767_bt"; + }; + + }; +}; + +&mfc { + status = "okay"; +}; + +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + vmmc-supply = <&buck9_reg>; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset { + samsung,pins = "gpm2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu { + vtmu-supply = <&ldo16_reg>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 61906b35ea7a..153a75fe6e24 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -64,6 +64,11 @@ }; }; +&adc { + vdd-supply = <&ldo10_reg>; + status = "okay"; +}; + /* VDDQ for MSHC (eMMC card) */ &buck8_reg { regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi deleted file mode 100644 index 76cfd872ead3..000000000000 --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi deleted file mode 100644 index 3c40f8a956dd..000000000000 --- a/arch/arm/boot/dts/exynos4415.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Samsung's Exynos4415 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 - * based board files can include this file and provide values for board - * specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -/ { - compatible = "samsung,exynos4415"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x50000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@4f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x4f000 0x1000>; - }; - }; - - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 242 0>; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sysreg_system_controller: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4415-pmu", "syscon"; - reg = <0x10020000 0x4000>; - }; - - mipi_phy: video-phy@10020710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: cam-power-domain@10024000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024000 0x20>; - #power-domain-cells = <0>; - }; - - pd_tv: tv-power-domain@10024020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024020 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10024040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024040 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10024060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024060 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10024080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024080 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp0: isp0-power-domain@100240A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240A0 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp1: isp1-power-domain@100240E0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240E0 0x20>; - #power-domain-cells = <0>; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos4415-cmu"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; - status = "disabled"; - }; - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - cmu_dmc: clock-controller@105C0000 { - compatible = "samsung,exynos4415-cmu-dmc"; - reg = <0x105C0000 0x3000>; - #clock-cells = <1>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 48 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; - }; - - fimd: fimd@11C00000 { - compatible = "samsung,exynos4415-fimd"; - reg = <0x11C00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos4415-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; - samsung,phy-type = <0>; - samsung,power-domain = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; - clocks = <&cmu CLK_USBDEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; - status = "disabled"; - }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; - status = "disabled"; - }; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos3250-adc", - "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; - interrupts = <0 137 0>; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 110 0>; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 111 0>; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 112 0>; - clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 113 0>; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 114 0>; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 115 0>; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 116 0>; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 121 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 122 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 123 0>; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - clock_audss: clock-controller@03810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - interrupts = <0 124 0>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; - dma-names = "tx", "rx", "tx-sec"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - samsung,idma-addr = <0x03000000>; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; - }; - }; -}; - -#include "exynos4415-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index a56bf9b1a412..2f866f6e5838 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -572,8 +572,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -583,8 +589,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 3394bdcf10ae..85a7122658f1 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -88,11 +88,11 @@ #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, <1 &combiner 12 5>, <2 &combiner 12 6>, <3 &combiner 12 7>, - <4 &gic 1 12 0>; + <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -112,7 +112,7 @@ g2d: g2d@10800000 { compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; - interrupts = <0 89 0>; + interrupts = ; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; iommus = <&sysmmu_g2d>; @@ -127,7 +127,7 @@ fimc_lite_0: fimc-lite@12390000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x12390000 0x1000>; - interrupts = <0 105 0>; + interrupts = ; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>; clock-names = "flite"; @@ -138,7 +138,7 @@ fimc_lite_1: fimc-lite@123A0000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x123A0000 0x1000>; - interrupts = <0 106 0>; + interrupts = ; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE1>; clock-names = "flite"; @@ -147,9 +147,10 @@ }; fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is", "simple-bus"; + compatible = "samsung,exynos4212-fimc-is"; reg = <0x12000000 0x260000>; - interrupts = <0 90 0>, <0 95 0>; + interrupts = , + ; power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>, <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, @@ -200,7 +201,7 @@ mshc_0: mmc@12550000 { compatible = "samsung,exynos4412-dw-mshc"; reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; fifo-depth = <0x80>; @@ -461,11 +462,26 @@ }; &combiner { - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; &exynos_usbphy { @@ -529,18 +545,18 @@ &pinctrl_0 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; + interrupts = ; }; &pinctrl_1 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; + interrupts = ; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = ; }; }; @@ -554,7 +570,7 @@ &pinctrl_3 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x106E0000 0x1000>; - interrupts = <0 72 0>; + interrupts = ; }; &pmu_system_controller { diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 8f06609879f5..7fd870ee5093 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -13,6 +13,8 @@ * published by the Free Software Foundation. */ +#include +#include #include "exynos-syscon-restart.dtsi" / { @@ -53,14 +55,38 @@ interrupt-controller; samsung,combiner-nr = <32>; reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; }; gic: interrupt-controller@10481000 { @@ -71,7 +97,8 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; sysreg_system_controller: syscon@10050000 { @@ -82,31 +109,31 @@ serial_0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; }; serial_1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; }; serial_2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; + interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>; }; serial_3: serial@12C30000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; }; i2c_0: i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -116,7 +143,7 @@ i2c_1: i2c@12C70000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -126,7 +153,7 @@ i2c_2: i2c@12C80000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -136,7 +163,7 @@ i2c_3: i2c@12C90000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>; @@ -153,7 +180,8 @@ rtc: rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>, + <0 44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index d5d51916bb74..8f3a80430748 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -523,6 +523,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -536,6 +537,7 @@ cap-mmc-highspeed; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; @@ -553,6 +555,8 @@ /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. + * + * WiFi SDIO module */ &mmc_3 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f7357d99b47c..b6d7444d8585 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -181,8 +181,8 @@ <0x1 0 &combiner 23 4>, <0x2 0 &combiner 25 2>, <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; + <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -195,31 +195,31 @@ pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x11400000 0x1000>; - interrupts = <0 46 0>; + interrupts = ; wakup_eint: wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = ; }; }; pinctrl_1: pinctrl@13400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = ; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; + interrupts = ; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = ; }; pmu_system_controller: system-controller@10040000 { @@ -236,7 +236,7 @@ watchdog@101D0000 { compatible = "samsung,exynos5250-wdt"; reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; + interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -245,7 +245,7 @@ g2d@10850000 { compatible = "samsung,exynos5250-g2d"; reg = <0x10850000 0x1000>; - interrupts = <0 91 0>; + interrupts = ; clocks = <&clock CLK_G2D>; clock-names = "fimg2d"; iommus = <&sysmmu_g2d>; @@ -254,7 +254,7 @@ mfc: codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; + interrupts = ; power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; @@ -265,7 +265,7 @@ rotator: rotator@11C00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; + interrupts = ; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -274,7 +274,7 @@ tmu: tmu@10060000 { compatible = "samsung,exynos5250-tmu"; reg = <0x10060000 0x100>; - interrupts = <0 65 0>; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -284,7 +284,7 @@ compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; - interrupts = <0 115 0>; + interrupts = ; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; clock-names = "sata", "sclk_sata"; phys = <&sata_phy>; @@ -306,7 +306,7 @@ i2c_4: i2c@12CA0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C4>; @@ -319,7 +319,7 @@ i2c_5: i2c@12CB0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C5>; @@ -332,7 +332,7 @@ i2c_6: i2c@12CC0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C6>; @@ -345,7 +345,7 @@ i2c_7: i2c@12CD0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C7>; @@ -358,7 +358,7 @@ i2c_8: i2c@12CE0000 { compatible = "samsung,s3c2440-hdmiphy-i2c"; reg = <0x12CE0000 0x1000>; - interrupts = <0 64 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_I2C_HDMI>; @@ -380,7 +380,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d20000 0x100>; - interrupts = <0 66 0>; + interrupts = ; dmas = <&pdma0 5 &pdma0 4>; dma-names = "tx", "rx"; @@ -396,7 +396,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d30000 0x100>; - interrupts = <0 67 0>; + interrupts = ; dmas = <&pdma1 5 &pdma1 4>; dma-names = "tx", "rx"; @@ -412,7 +412,7 @@ compatible = "samsung,exynos4210-spi"; status = "disabled"; reg = <0x12d40000 0x100>; - interrupts = <0 68 0>; + interrupts = ; dmas = <&pdma0 7 &pdma0 6>; dma-names = "tx", "rx"; @@ -426,7 +426,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x1000>; @@ -438,7 +438,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x1000>; @@ -450,7 +450,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; @@ -463,7 +463,7 @@ mmc_3: mmc@12230000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; @@ -526,7 +526,7 @@ usbdrd_dwc3: dwc3@12000000 { compatible = "synopsys,dwc3"; reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; + interrupts = ; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -544,7 +544,7 @@ ehci: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; - interrupts = <0 71 0>; + interrupts = ; clocks = <&clock CLK_USB2>; clock-names = "usbhost"; @@ -559,7 +559,7 @@ ohci: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; - interrupts = <0 71 0>; + interrupts = ; clocks = <&clock CLK_USB2>; clock-names = "usbhost"; @@ -591,7 +591,7 @@ pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; + interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -602,7 +602,7 @@ pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; + interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -613,7 +613,7 @@ mdma0: mdma@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; + interrupts = ; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -624,7 +624,7 @@ mdma1: mdma@11C10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; + interrupts = ; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -636,7 +636,7 @@ gsc_0: gsc@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; + interrupts = ; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; @@ -646,7 +646,7 @@ gsc_1: gsc@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; + interrupts = ; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; @@ -656,7 +656,7 @@ gsc_2: gsc@13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; - interrupts = <0 87 0>; + interrupts = ; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; @@ -666,7 +666,7 @@ gsc_3: gsc@13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; - interrupts = <0 88 0>; + interrupts = ; power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; @@ -677,7 +677,7 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; power-domains = <&pd_disp1>; - interrupts = <0 95 0>; + interrupts = ; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, <&clock CLK_MOUT_HDMI>; @@ -690,7 +690,7 @@ compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; power-domains = <&pd_disp1>; - interrupts = <0 94 0>; + interrupts = ; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; @@ -706,7 +706,7 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v1"; reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; + interrupts = ; clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; @@ -718,7 +718,7 @@ sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = ; clocks = <&clock CLK_SSS>; clock-names = "secss"; }; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index a86a4898d077..5818718618b1 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -10,6 +10,8 @@ */ #include +#include +#include / { compatible = "samsung,exynos5260", "samsung,exynos5"; @@ -168,7 +170,8 @@ <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; chipid: chipid@10000000 { @@ -181,10 +184,18 @@ reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 122 0>, <0 123 0>, - <0 124 0>, <0 125 0>, <0 126 0>, - <0 127 0>, <0 128 0>, <0 129 0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; }; cci: cci@10F00000 { @@ -210,25 +221,25 @@ pinctrl_0: pinctrl@11600000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x11600000 0x1000>; - interrupts = <0 79 0>; + interrupts = ; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = ; }; }; pinctrl_1: pinctrl@12290000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x12290000 0x1000>; - interrupts = <0 157 0>; + interrupts = ; }; pinctrl_2: pinctrl@128B0000 { compatible = "samsung,exynos5260-pinctrl"; reg = <0x128B0000 0x1000>; - interrupts = <0 243 0>; + interrupts = ; }; pmu_system_controller: system-controller@10D50000 { @@ -239,7 +250,7 @@ uart0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; + interrupts = ; clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -248,7 +259,7 @@ uart1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; - interrupts = <0 147 0>; + interrupts = ; clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -257,7 +268,7 @@ uart2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; - interrupts = <0 148 0>; + interrupts = ; clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -266,7 +277,7 @@ uart3: serial@12860000 { compatible = "samsung,exynos4210-uart"; reg = <0x12860000 0x100>; - interrupts = <0 145 0>; + interrupts = ; clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; @@ -275,7 +286,7 @@ mmc_0: mmc@12140000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12140000 0x2000>; - interrupts = <0 156 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; @@ -287,7 +298,7 @@ mmc_1: mmc@12150000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12150000 0x2000>; - interrupts = <0 158 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; @@ -299,7 +310,7 @@ mmc_2: mmc@12160000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12160000 0x2000>; - interrupts = <0 159 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 3c271cb4b2be..c4de1353e5df 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -15,6 +15,7 @@ #include #include #include +#include #include "exynos54xx-odroidxu-leds.dtsi" / { @@ -57,6 +58,61 @@ compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; + + sound: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "Odroid-XU"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,cpu { + sound-dai = <&audi2s0 0>; + system-clock-frequency = <19200000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&max98090>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + }; + }; +}; + +&audi2s0 { + status = "okay"; +}; + +&clock { + clocks = <&fin_pll>; + assigned-clocks = <&clock CLK_FOUT_EPLL>; + assigned-clock-rates = <192000000>; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + + assigned-clock-rates = <0>, + <0>, + <96000000>, + <19200000>; }; &cpu0_thermal { @@ -440,6 +496,19 @@ }; }; +&i2c_1 { + status = "okay"; + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpj3>; + interrupts = <0 IRQ_TYPE_NONE>; + clocks = <&audi2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + &mmc_0 { status = "okay"; mmc-pwrseq = <&emmc_pwrseq>; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index a083d23fdee3..ff46a1c27182 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -615,4 +615,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + audi2s0_bus: audi2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 137f48464f8b..2b6adafe18e2 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -16,6 +16,7 @@ #include "exynos54xx.dtsi" #include "exynos-syscon-restart.dtsi" #include +#include #include / { @@ -82,10 +83,18 @@ #clock-cells = <1>; }; + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5410-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; + clock-names = "pll_ref", "pll_in"; + }; + tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = ; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -94,7 +103,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = ; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -103,7 +112,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10068000 0x100>; - interrupts = ; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -112,7 +121,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu"; reg = <0x1006c000 0x100>; - interrupts = ; + interrupts = ; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -121,7 +130,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; @@ -133,7 +142,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; @@ -145,7 +154,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; @@ -157,31 +166,81 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = ; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = ; }; }; pinctrl_1: pinctrl@14000000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; + interrupts = ; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; + interrupts = ; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = ; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = ; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + audi2s0: i2s@03830000 { + compatible = "samsung,exynos5420-i2s"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + pinctrl-names = "default"; + pinctrl-0 = <&audi2s0_bus>; + status = "disabled"; }; }; @@ -329,7 +388,7 @@ }; &usbdrd_dwc3_1 { - interrupts = ; + interrupts = ; }; &usbdrd_phy1 { diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index ec4a00f1ce01..1f964ec35c5e 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -697,6 +697,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -714,6 +715,7 @@ bus-width = <8>; }; +/* WiFi SDIO module */ &mmc_1 { status = "okay"; num-slots = <1>; @@ -733,6 +735,7 @@ vqmmc-supply = <&buck10_reg>; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 00c4cfa54839..906a1a42a7ea 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -193,7 +193,7 @@ mfc: codec@11000000 { compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; power-domains = <&mfc_pd>; @@ -203,7 +203,7 @@ mmc_0: mmc@12200000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 0>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x2000>; @@ -215,7 +215,7 @@ mmc_1: mmc@12210000 { compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 0>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x2000>; @@ -227,7 +227,7 @@ mmc_2: mmc@12220000 { compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 0>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; @@ -320,37 +320,37 @@ pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 32 0>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_1: pinctrl@13410000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13410000 0x1000>; - interrupts = <0 78 0>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_2: pinctrl@14000000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_3: pinctrl@14010000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x14010000 0x1000>; - interrupts = <0 50 0>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_4: pinctrl@03860000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; }; amba { @@ -363,7 +363,7 @@ adma: adma@03880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; - interrupts = <0 110 0>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_audss EXYNOS_ADMA>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -374,7 +374,7 @@ pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -385,7 +385,7 @@ pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -396,7 +396,7 @@ mdma0: mdma@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -407,7 +407,7 @@ mdma1: mdma@11C10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -479,7 +479,7 @@ spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; - interrupts = <0 68 0>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 5 &pdma0 4>; dma-names = "tx", "rx"; @@ -495,7 +495,7 @@ spi_1: spi@12d30000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d30000 0x100>; - interrupts = <0 69 0>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma1 5 &pdma1 4>; dma-names = "tx", "rx"; @@ -511,7 +511,7 @@ spi_2: spi@12d40000 { compatible = "samsung,exynos4210-spi"; reg = <0x12d40000 0x100>; - interrupts = <0 70 0>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; dmas = <&pdma0 7 &pdma0 6>; dma-names = "tx", "rx"; @@ -539,7 +539,7 @@ dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; - interrupts = <0 82 0>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; @@ -552,7 +552,7 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; @@ -564,7 +564,7 @@ hsi2c_8: i2c@12E00000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E00000 0x1000>; - interrupts = <0 87 0>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -577,7 +577,7 @@ hsi2c_9: i2c@12E10000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E10000 0x1000>; - interrupts = <0 88 0>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -590,7 +590,7 @@ hsi2c_10: i2c@12E20000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12E20000 0x1000>; - interrupts = <0 203 0>; + interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -603,7 +603,7 @@ hdmi: hdmi@14530000 { compatible = "samsung,exynos5420-hdmi"; reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, <&clock CLK_MOUT_HDMI>; @@ -622,7 +622,7 @@ mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; @@ -633,7 +633,7 @@ rotator: rotator@11C00000 { compatible = "samsung,exynos5250-rotator"; reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; iommus = <&sysmmu_rotator>; @@ -642,7 +642,7 @@ gsc_0: video-scaler@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -652,7 +652,7 @@ gsc_1: video-scaler@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; power-domains = <&gsc_pd>; @@ -662,7 +662,7 @@ jpeg_0: jpeg@11F50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; - interrupts = <0 89 0>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; iommus = <&sysmmu_jpeg0>; @@ -671,7 +671,7 @@ jpeg_1: jpeg@11F60000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F60000 0x1000>; - interrupts = <0 168 0>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; iommus = <&sysmmu_jpeg1>; @@ -691,7 +691,7 @@ tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; - interrupts = <0 65 0>; + interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -700,7 +700,7 @@ tmu_cpu1: tmu@10064000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; - interrupts = <0 183 0>; + interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -709,7 +709,7 @@ tmu_cpu2: tmu@10068000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -718,7 +718,7 @@ tmu_cpu3: tmu@1006c000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; + interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -727,7 +727,7 @@ tmu_gpu: tmu@100a0000 { compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; + interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; #include "exynos4412-tmu-sensor-conf.dtsi" @@ -799,7 +799,7 @@ sysmmu_scaler1r: sysmmu@0x12890000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12890000 0x1000>; - interrupts = <0 186 0>; + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; #iommu-cells = <0>; @@ -808,7 +808,7 @@ sysmmu_scaler2r: sysmmu@0x128A0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128A0000 0x1000>; - interrupts = <0 188 0>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; #iommu-cells = <0>; @@ -867,7 +867,7 @@ sysmmu_jpeg1: sysmmu@0x11F20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F20000 0x1000>; - interrupts = <0 169 0>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; #iommu-cells = <0>; @@ -1445,7 +1445,7 @@ }; &usbdrd_dwc3_1 { - interrupts = ; + interrupts = ; }; &usbdrd_phy1 { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 246d298557f5..05b9afdd6757 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -147,6 +147,11 @@ }; }; +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + &bus_wcore { devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, <&nocp_mem1_0>, <&nocp_mem1_1>; @@ -293,6 +298,12 @@ regulator-max-microvolt = <1800000>; }; + ldo4_reg: LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + ldo5_reg: LDO5 { regulator-name = "vdd_ldo5"; regulator-min-microvolt = <1800000>; @@ -499,7 +510,6 @@ &mmc_0 { status = "okay"; mmc-pwrseq = <&emmc_pwrseq>; - cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index e6bffd13cedd..2a2e570bbee6 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -10,6 +10,8 @@ */ #include +#include +#include / { compatible = "samsung,exynos5440", "samsung,exynos5"; @@ -41,7 +43,8 @@ <0x2E2000 0x1000>, <0x2E4000 0x2000>, <0x2E6000 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; cpus { @@ -72,26 +75,26 @@ arm-pmu { compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 52 4>, - <0 53 4>, - <0 54 4>, - <0 55 4>; + interrupts = , + , + , + ; }; timer { compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = , + , + , + ; clock-frequency = <50000000>; }; cpufreq@160000 { compatible = "samsung,exynos5440-cpufreq"; reg = <0x160000 0x1000>; - interrupts = <0 57 0>; + interrupts = ; operating-points = < /* KHz uV */ 1500000 1100000 @@ -108,7 +111,7 @@ serial_0: serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; - interrupts = <0 2 0>; + interrupts = ; clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -116,7 +119,7 @@ serial_1: serial@C0000 { compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; - interrupts = <0 3 0>; + interrupts = ; clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; clock-names = "uart", "clk_uart_baud0"; }; @@ -124,7 +127,7 @@ spi_0: spi@D0000 { compatible = "samsung,exynos5440-spi"; reg = <0xD0000 0x100>; - interrupts = <0 4 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; samsung,spi-src-clk = <0>; @@ -136,8 +139,14 @@ pin_ctrl: pinctrl@E0000 { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; + interrupts = , + , + , + , + , + , + , + ; interrupt-controller; #interrupt-cells = <2>; #gpio-cells = <2>; @@ -162,7 +171,7 @@ i2c@F0000 { compatible = "samsung,exynos5440-i2c"; reg = <0xF0000 0x1000>; - interrupts = <0 5 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_B_125>; @@ -172,7 +181,7 @@ i2c@100000 { compatible = "samsung,exynos5440-i2c"; reg = <0x100000 0x1000>; - interrupts = <0 6 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_B_125>; @@ -182,16 +191,16 @@ watchdog@110000 { compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; - interrupts = <0 1 0>; + interrupts = ; clocks = <&clock CLK_B_125>; clock-names = "watchdog"; }; gmac: ethernet@00230000 { - compatible = "snps,dwmac-3.70a"; + compatible = "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x00230000 0x8000>; interrupt-parent = <&gic>; - interrupts = <0 31 4>; + interrupts = ; interrupt-names = "macirq"; phy-mode = "sgmii"; clocks = <&clock CLK_GMAC0>; @@ -209,7 +218,8 @@ rtc@130000 { compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; - interrupts = <0 17 0>, <0 16 0>; + interrupts = , + ; clocks = <&clock CLK_B_125>; clock-names = "rtc"; }; @@ -217,7 +227,7 @@ tmuctrl_0: tmuctrl@160118 { compatible = "samsung,exynos5440-tmu"; reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = ; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -226,7 +236,7 @@ tmuctrl_1: tmuctrl@16011C { compatible = "samsung,exynos5440-tmu"; reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = ; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -235,7 +245,7 @@ tmuctrl_2: tmuctrl@160120 { compatible = "samsung,exynos5440-tmu"; reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; + interrupts = ; clocks = <&clock CLK_B_125>; clock-names = "tmu_apbif"; #include "exynos5440-tmu-sensor-conf.dtsi" @@ -259,7 +269,7 @@ sata@210000 { compatible = "snps,exynos5440-ahci"; reg = <0x210000 0x10000>; - interrupts = <0 30 0>; + interrupts = ; clocks = <&clock CLK_SATA>; clock-names = "sata"; }; @@ -267,7 +277,7 @@ ohci@220000 { compatible = "samsung,exynos5440-ohci"; reg = <0x220000 0x1000>; - interrupts = <0 29 0>; + interrupts = ; clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -275,7 +285,7 @@ ehci@221000 { compatible = "samsung,exynos5440-ehci"; reg = <0x221000 0x1000>; - interrupts = <0 29 0>; + interrupts = ; clocks = <&clock CLK_USB>; clock-names = "usbhost"; }; @@ -285,7 +295,9 @@ reg = <0x290000 0x1000 0x270000 0x1000 0x271000 0x40>; - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + interrupts = , + , + ; clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; @@ -306,7 +318,9 @@ reg = <0x2a0000 0x1000 0x272000 0x1000 0x271040 0x40>; - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + interrupts = , + , + ; clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 9d31cdce1959..0389e8a10d0b 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -62,34 +62,34 @@ <1 &combiner 23 4>, <2 &combiner 25 2>, <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; + <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>, + <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>, + <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>, + <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>, + <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>, + <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>, + <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; }; }; watchdog: watchdog@101d0000 { compatible = "samsung,exynos5420-wdt"; reg = <0x101d0000 0x100>; - interrupts = <0 42 0>; + interrupts = ; }; sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>; - interrupts = <0 112 0>; + interrupts = ; }; /* i2c_0-3 are defined in exynos5.dtsi */ hsi2c_4: i2c@12ca0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12ca0000 0x1000>; - interrupts = <0 60 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -98,7 +98,7 @@ hsi2c_5: i2c@12cb0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cb0000 0x1000>; - interrupts = <0 61 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -107,7 +107,7 @@ hsi2c_6: i2c@12cc0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cc0000 0x1000>; - interrupts = <0 62 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -116,7 +116,7 @@ hsi2c_7: i2c@12cd0000 { compatible = "samsung,exynos5250-hsi2c"; reg = <0x12cd0000 0x1000>; - interrupts = <0 63 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -131,7 +131,7 @@ usbdrd_dwc3_0: dwc3@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; + interrupts = ; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -166,7 +166,7 @@ usbhost2: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; - interrupts = <0 71 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -179,7 +179,7 @@ usbhost1: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; - interrupts = <0 71 0>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 01f466816fea..f9ff7f07ae0c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -665,6 +665,7 @@ status = "okay"; }; +/* eMMC flash */ &mmc_0 { status = "okay"; num-slots = <1>; @@ -683,6 +684,7 @@ bus-width = <8>; }; +/* WiFi SDIO module */ &mmc_1 { status = "okay"; num-slots = <1>; @@ -702,6 +704,7 @@ vqmmc-supply = <&buck10_reg>; }; +/* uSD card */ &mmc_2 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index c85d07e6db61..541d70094544 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -11,10 +11,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart0; serial1 = &uart1; @@ -537,6 +539,7 @@ reg = <0x803000 0x188>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; #gpio-range-cells = <3>; ranges; @@ -558,6 +561,7 @@ reg = <0x803800 0x2dc>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges; pinctrl-single,register-width = <32>; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 4e9562f806a2..9d5fd5cfefa6 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -11,8 +11,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" - / { interrupt-parent = <&gic>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 0da76c5ff6d7..6c712a97e1fe 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart0; }; @@ -436,7 +438,7 @@ }; gmac0: ethernet@1840000 { - compatible = "hisilicon,hix5hd2-gemac", "hisilicon,hisi-gemac-v1"; + compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; reg = <0x1840000 0x1000>,<0x184300c 0x4>; interrupts = <0 71 4>; clocks = <&clock HIX5HD2_MAC0_CLK>; @@ -445,7 +447,7 @@ }; gmac1: ethernet@1841000 { - compatible = "hisilicon,hix5hd2-gemac", "hisilicon,hisi-gemac-v1"; + compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1"; reg = <0x1841000 0x1000>,<0x1843010 0x4>; interrupts = <0 72 4>; clocks = <&clock HIX5HD2_MAC1_CLK>; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index 22f5d1db5b31..b792eee3899b 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -9,7 +9,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx1-pinfunc.h" #include @@ -17,6 +16,9 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { gpio0 = &gpio1; gpio1 = &gpio2; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 440ee9a4a158..ac2a9da62b6c 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -9,10 +9,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx23-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&icoll>; aliases { @@ -464,7 +466,7 @@ reg = <0x80038000 0x2000>; status = "disabled"; }; - }; + }; apbx@80040000 { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index af6af8741fe5..831d09a28155 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -9,10 +9,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx25-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index f818ea483aeb..9d8b5969ee3b 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -9,7 +9,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx27-pinfunc.h" #include @@ -18,6 +17,9 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 214bb1506b53..a69856e41ba4 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -12,8 +12,8 @@ #include "imx28.dtsi" / { - model = "DENX M28"; - compatible = "denx,m28", "fsl,imx28"; + model = "Aries/DENX M28"; + compatible = "aries,m28", "denx,m28", "fsl,imx28"; memory { reg = <0x40000000 0x08000000>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 8d04e57039bc..dbfb8aab505f 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -13,8 +13,8 @@ #include "imx28-m28.dtsi" / { - model = "DENX M28EVK"; - compatible = "denx,m28evk", "fsl,imx28"; + model = "Aries/DENX M28EVK"; + compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; apb@80000000 { apbh@80000000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 0ad893bf5f43..3aabf65a6a52 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -10,10 +10,12 @@ */ #include -#include "skeleton.dtsi" #include "imx28-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&icoll>; aliases { diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 1ce7ae94e7ad..85cd8be22f71 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -9,9 +9,10 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; @@ -30,11 +31,11 @@ }; }; - avic: avic-interrupt-controller@60000000 { + avic: interrupt-controller@68000000 { compatible = "fsl,imx31-avic", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; - reg = <0x60000000 0x100000>; + reg = <0x68000000 0x100000>; }; soc { @@ -118,13 +119,6 @@ interrupts = <19>; clocks = <&clks 25>; }; - - clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <0 31 0x04 0 53 0x04>; - #clock-cells = <1>; - }; }; aips@53f00000 { /* AIPS2 */ @@ -134,6 +128,13 @@ reg = <0x53f00000 0x100000>; ranges; + clks: ccm@53f80000{ + compatible = "fsl,imx31-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>, <53>; + #clock-cells = <1>; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index f812d586c5ce..9f40e6229189 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -8,10 +8,12 @@ * Free Software Foundation. */ -#include "skeleton.dtsi" #include "imx35-pinfunc.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 8fe8beeb68a4..fe0221e4cbf7 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -11,11 +11,13 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx50-pinfunc.h" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -103,8 +105,8 @@ reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -115,8 +117,8 @@ reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -127,7 +129,7 @@ reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -139,7 +141,7 @@ reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -164,8 +166,8 @@ reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -176,8 +178,8 @@ reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -279,7 +281,7 @@ reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -298,7 +300,7 @@ compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -308,7 +310,7 @@ compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -318,7 +320,7 @@ reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -328,7 +330,7 @@ reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -383,7 +385,7 @@ reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; + <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -401,7 +403,7 @@ reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; + <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -420,7 +422,7 @@ reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -430,7 +432,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; }; @@ -442,7 +444,7 @@ reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -492,8 +494,8 @@ reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index f46fe9bf0bcb..33526cade735 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -10,7 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx51-pinfunc.h" #include #include @@ -18,6 +17,9 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -130,8 +132,8 @@ reg = <0x40000000 0x20000000>; interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; @@ -169,8 +171,8 @@ reg = <0x70004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -180,8 +182,8 @@ reg = <0x70008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -192,7 +194,7 @@ reg = <0x7000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -204,7 +206,7 @@ reg = <0x70010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -229,8 +231,8 @@ reg = <0x70020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -241,8 +243,8 @@ reg = <0x70024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -364,7 +366,7 @@ reg = <0x73fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -378,7 +380,7 @@ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -388,7 +390,7 @@ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -398,7 +400,7 @@ reg = <0x73fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -408,7 +410,7 @@ reg = <0x73fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -456,7 +458,7 @@ reg = <0x83fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -466,7 +468,7 @@ reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; @@ -479,7 +481,7 @@ reg = <0x83fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -582,8 +584,8 @@ reg = <0x83fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index d259f57bfd98..ec390aa562c3 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -12,8 +12,8 @@ #include "imx53.dtsi" / { - model = "DENX M53"; - compatible = "denx,imx53-m53", "fsl,imx53"; + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; memory { reg = <0x70000000 0x20000000>, diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index dcee1e0f968f..4347a321c782 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -13,8 +13,8 @@ #include "imx53-m53.dtsi" / { - model = "DENX M53EVK"; - compatible = "denx,imx53-m53evk", "fsl,imx53"; + model = "Aries/DENX M53EVK"; + compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; display1: display@di1 { compatible = "fsl,imx-parallel-display"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 0777b41cdfe8..ca51dc03e327 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -10,7 +10,6 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" #include "imx53-pinfunc.h" #include #include @@ -18,6 +17,9 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -131,8 +133,8 @@ reg = <0x18000000 0x08000000>; interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; @@ -199,8 +201,8 @@ reg = <0x50004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -211,8 +213,8 @@ reg = <0x50008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -223,7 +225,7 @@ reg = <0x5000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; + <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; dma-names = "rx", "tx"; @@ -237,7 +239,7 @@ reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; + <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -264,8 +266,8 @@ reg = <0x50020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -276,8 +278,8 @@ reg = <0x50024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; @@ -419,7 +421,7 @@ reg = <0x53fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; + <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; @@ -440,11 +442,11 @@ reg = <0x53fa8008 0x4>; gpr = <&gpr>; clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di0", "di1"; @@ -486,7 +488,7 @@ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; + <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; @@ -496,7 +498,7 @@ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; + <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; @@ -506,7 +508,7 @@ reg = <0x53fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; + <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; dma-names = "rx", "tx"; @@ -518,7 +520,7 @@ reg = <0x53fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; + <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; dma-names = "rx", "tx"; @@ -530,7 +532,7 @@ reg = <0x53fc8000 0x4000>; interrupts = <82>; clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, - <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -540,7 +542,7 @@ reg = <0x53fcc000 0x4000>; interrupts = <83>; clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, - <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -603,7 +605,7 @@ reg = <0x53ff0000 0x4000>; interrupts = <13>; clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; + <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; dma-names = "rx", "tx"; @@ -635,7 +637,7 @@ reg = <0x63f90000 0x4000>; interrupts = <86>; clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; + <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; dma-names = "rx", "tx"; @@ -656,7 +658,7 @@ reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; + <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -666,7 +668,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_SDMA_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; @@ -679,7 +681,7 @@ reg = <0x63fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; + <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; @@ -755,8 +757,8 @@ reg = <0x63fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; @@ -766,7 +768,7 @@ reg = <0x63ff0000 0x1000>; interrupts = <92>; clocks = <&clks IMX5_CLK_TVE_GATE>, - <&clks IMX5_CLK_IPU_DI1_SEL>; + <&clks IMX5_CLK_IPU_DI1_SEL>; clock-names = "tve", "di_sel"; status = "disabled"; @@ -782,7 +784,7 @@ reg = <0x63ff4000 0x1000>; interrupts = <9>; clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; + <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; resets = <&src 1>; iram = <&ocram>; @@ -793,7 +795,7 @@ reg = <0x63ff8000 0x4000>; interrupts = <19 20>; clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; + <&clks IMX5_CLK_SAHARA_IPG_GATE>; clock-names = "ipg", "ahb"; }; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts new file mode 100644 index 000000000000..e0c21727866d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -0,0 +1,253 @@ +/* + * Copyright 2014-2016 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + clocks { + /* Fixed crystal dedicated to mcp251x */ + clk16m: clk@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; +}; + +&backlight { + brightness-levels = <0 127 191 223 239 247 251 255>; + default-brightness-level = <1>; + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; + + mcp251x0: mcp251x@1 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <27 0x2>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +&hdmi { + status = "okay"; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + status = "okay"; +}; + +&weim { + status = "okay"; + + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000>; + + /* SRAM on Colibri nEXT_CS0 */ + sram@0,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <0 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; + + /* SRAM on Colibri nEXT_CS1 */ + sram@1,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <1 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts new file mode 100644 index 000000000000..aec332c14af1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-icore.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 75d73437adf7..2cb72824e800 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -390,7 +390,7 @@ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index 063fe7510da5..aac42ac465b6 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index b7a72840b7f0..d1f1298ec55a 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ipu1_di0_disp0 { diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 207b85b91ada..0ea75f7b6039 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -147,28 +147,6 @@ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; }; - - pwmleds { - compatible = "pwm-leds"; - - ledpwm1 { - label = "PWM1"; - pwms = <&pwm1 0 50000>; - max-brightness = <255>; - }; - - ledpwm2 { - label = "PWM2"; - pwms = <&pwm2 0 50000>; - max-brightness = <255>; - }; - - ledpwm3 { - label = "PWM3"; - pwms = <&pwm3 0 50000>; - max-brightness = <255>; - }; - }; }; &backlight { diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index d85388725426..1dcaee23ed9c 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -98,3 +98,9 @@ line-name = "PCA9539-P05"; }; }; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <55>; + fsl,tx-cal-45-dp-ohms = <55>; + fsl,tx-d-cal = <100>; +}; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 59bc5a4dce17..a150bca84daa 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -183,7 +183,6 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index 6de21ff47c3a..7c7c1a855ece 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -232,10 +232,7 @@ }; &weim { - #address-cells = <2>; - #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts new file mode 100644 index 000000000000..025f54350c28 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-icore.dts @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts new file mode 100644 index 000000000000..cf4feefe02c5 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_som2.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board"; + compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 1723e89e3acc..758bca96786f 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -451,6 +451,10 @@ status = "okay"; }; +&pwm1 { + status = "okay"; +}; + &sata { target-supply = <®_sata>; fsl,transmit-level-mV = <1025>; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index c139ac0ebe15..1f4771304da8 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -23,5 +23,5 @@ }; &sata { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index 65e95ae7509a..71746edc2ee9 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index 20cd0e7b3e21..f9cd21a41a79 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ipu1_di0_disp0 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 9ed243b704ff..959ff3fb7304 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -105,7 +105,7 @@ pixelclk-active = <1>; }; }; - }; + }; }; &can1 { diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index 347b531d3763..b49133d25d80 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -199,7 +199,7 @@ pixelclk-active = <0>; }; }; - }; + }; }; &ds1339 { diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index 61990630a748..22009947cebc 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -68,7 +68,41 @@ label = "Power Button"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; linux,code = ; - gpio-key,wakeup; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1mux>; + #address-cells = <1>; + #size-cells = <0>; + + mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + em3027: rtc@56 { + compatible = "emmicro,em3027"; + reg = <0x56>; + }; + }; + + i2c_dvi_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; }; }; }; @@ -82,17 +116,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - - eeprom@50 { - compatible = "at24,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - em3027: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; }; &i2c2 { @@ -115,6 +138,12 @@ >; }; + pinctrl_i2c1mux: i2c1muxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 99e323b57261..8c8a049eb3d0 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -49,7 +49,10 @@ backlight: backlight { compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; pwms = <&pwm4 0 5000000>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -620,6 +623,12 @@ >; }; + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 + >; + }; + pinctrl_gpio_keys: gpio1io04grp { fsl,pins = < /* Power button */ diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index edbce222c782..5e7792d6bf58 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -347,13 +347,13 @@ fsl,pins = < MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi new file mode 100644 index 000000000000..e6faa653f91a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -0,0 +1,890 @@ +/* + * Copyright 2014-2016 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + model = "Toradex Colibri iMX6DL/S Module"; + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + pwms = <&pwm3 0 5000000>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "disabled"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + status = "disabled"; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6dl-colibri-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; + + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + status = "disabled"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; + status = "okay"; +}; + +/* Optional on SODIMM 55/63 */ +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +/* Optional on SODIMM 178/188 */ +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +/* Colibri SSP */ +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ddc>; + status = "disabled"; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* vgen1: unused */ + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vgen3: unused */ + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; +}; + +/* + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "recovery"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +/* Colibri PWM */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "disabled"; +}; + +/* Optional S/PDIF out on SODIMM 137 */ +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + fsl,dte-mode; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_B */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + fsl,dte-mode; + uart-has-rtscts; + status = "disabled"; +}; + +/* Colibri UART_C */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dte>; + fsl,dte-mode; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + disable-over-current; + dr_mode = "peripheral"; + status = "disabled"; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vqmmc-supply = <®_3p3v>; + bus-width = <4>; + voltage-ranges = <3300 3300>; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_3p3v>; + bus-width = <8>; + voltage-ranges = <3300 3300>; + non-removable; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 + &pinctrl_weim_cs1 &pinctrl_weim_cs2 + &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_cam_mclk: cammclkgrp { + fsl,pins = < + /* Parallel Camera CAM sys_mclk */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeys { + fsl,pins = < + /* Power button */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 + /* Disable PWM pins on camera interface */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 + >; + }; + + pinctrl_mic_gnd: gpiomicgnd { + fsl,pins = < + /* Controls Mic GND, PU or '1' pull Mic GND to GND */ + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 + >; + }; + + pinctrl_mmc_cd: gpiommccd { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + fsl,pins = < + /* USBH_EN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touch_int: gpiotouchintgrp { + fsl,pins = < + /* STMPE811 interrupt */ + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3_dte: uart3dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbc_det: usbcdetgrp { + fsl,pins = < + /* USBC_DET */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 + /* USBC_DET_OVERWRITE */ + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 + >; + }; + + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + /* nEXT_CS0 */ + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_cs1: weimcs1grp { + fsl,pins = < + /* nEXT_CS1 */ + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 + >; + }; + + pinctrl_weim_cs2: weimcs2grp { + fsl,pins = < + /* nEXT_CS2 */ + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 + >; + }; + + pinctrl_weim_sram: weimsramgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + /* Data */ + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + /* Address */ + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + pinctrl_weim_rdnwr: weimrdnwr { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 + >; + }; + + pinctrl_weim_npwe: weimnpwe { + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + >; + }; + + /* ADDRESS[16:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weimgpio-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weimgpio-2 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* DATA[16:31] used as GPIO */ + pinctrl_weim_gpio_3: weimgpio-3 { + fsl,pins = < + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weimgpio-4 { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weimgpio-5 { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weimgpio-6 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index a7100f99123e..54aca3a07ce4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -153,9 +153,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &ecspi3 { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 8953eba0573d..88e5cb3b6be9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -154,9 +154,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &fec { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 6ac41c7ed32e..1753ab720b0b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -144,9 +144,9 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; }; &fec { diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 805e23674a94..ee83161f674b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -291,7 +291,7 @@ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 >; - }; + }; pinctrl_wdog: wdoggrp { fsl,pins = < diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi new file mode 100644 index 000000000000..023839a02dd0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + memory { + reg = <0x10000000 0x80000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + rmii_clk: clock-rmii-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; /* 25MHz for example */ + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + phy-mode = "rmii"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 880bd782a5b7..63acd54f5278 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -97,15 +97,6 @@ }; }; - bt_rfkill { - compatible = "rfkill-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - name = "bt_rfkill"; - type = <2>; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -160,7 +151,7 @@ }; }; - backlight_lcd { + backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -169,7 +160,7 @@ status = "okay"; }; - backlight_lvds0: backlight_lvds0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -178,7 +169,7 @@ status = "okay"; }; - panel_lvds0 { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; @@ -328,19 +319,6 @@ >; }; - pinctrl_bt_rfkill: bt_rfkillgrp { - fsl,pins = < - /* BT wake */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* BT reset */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 - /* BT reg en */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* BT host wake irq */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 - >; - }; - pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -374,7 +352,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Home Button: J14 pin 5 */ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 @@ -457,7 +435,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 >; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index b0b3220a1fd9..34887a10c5f1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -229,7 +229,7 @@ }; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -238,7 +238,7 @@ status = "okay"; }; - backlight_lvds0: backlight_lvds0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -247,7 +247,7 @@ status = "okay"; }; - backlight_lvds1: backlight_lvds1 { + backlight_lvds1: backlight-lvds1 { compatible = "pwm-backlight"; pwms = <&pwm2 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -282,7 +282,7 @@ }; }; - panel_lcd { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -293,7 +293,7 @@ }; }; - panel_lvds0 { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; @@ -304,7 +304,7 @@ }; }; - panel_lvds1 { + panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; @@ -447,7 +447,7 @@ }; &iomuxc { - imx6q-nitrogen6_max { + imx6q-nitrogen6-max { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 @@ -504,7 +504,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -720,7 +720,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi new file mode 100644 index 000000000000..d80f21abea62 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -0,0 +1,770 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + status = "okay"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_lvds1>; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_j15>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel-lvds0 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds0>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel-lvds1 { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds1>; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_som2-sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + rtc@68 { + compatible = "st,rv4162"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rv4162>; + reg = <0x68>; + interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight_lvds1: backlight-lvds1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_can_xcvr: can-xcvrgrp { + fsl,pins = < + /* Flexcan XCVR enable */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + /* PCIe I2C enable */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 + >; + }; + + pinctrl_j15: j15grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* PCIe reset */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1 + >; + }; + + pinctrl_rv4162: rv4162grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_wlan_vmmc: wlan-vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0 + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wlan_vmmc>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index db868bc42c0f..26d060484728 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -167,7 +167,7 @@ mux-ext-port = <3>; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -176,7 +176,7 @@ status = "okay"; }; - backlight_lvds: backlight_lvds { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -211,7 +211,7 @@ }; }; - lcd_panel { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -222,7 +222,7 @@ }; }; - panel { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; @@ -413,7 +413,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -533,7 +533,6 @@ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 >; }; @@ -561,7 +560,7 @@ >; }; - pinctrl_wlan_vmmc: wlan_vmmcgrp { + pinctrl_wlan_vmmc: wlan-vmmcgrp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e0280cac2484..e9801a26f3b4 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -427,10 +427,10 @@ }; &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_cdwp>; cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "disabled"; + status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e000e6f12bf5..52390ba83e81 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -283,7 +283,7 @@ VD-supply = <®_audio>; VLS-supply = <®_audio>; VLC-supply = <®_audio>; - }; + }; }; @@ -613,8 +613,6 @@ &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - #address-cells = <2>; - #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; status = "disabled"; /* pin conflict with SPI NOR */ diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 81dd6cd1937d..1f9076e271e4 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -153,7 +153,7 @@ mux-ext-port = <4>; }; - backlight_lcd: backlight_lcd { + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -162,7 +162,7 @@ status = "okay"; }; - backlight_lvds: backlight_lvds { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -197,7 +197,7 @@ }; }; - lcd_panel { + panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; @@ -208,7 +208,7 @@ }; }; - panel { + panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; @@ -378,7 +378,7 @@ >; }; - pinctrl_gpio_keys: gpio_keysgrp { + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < /* Power Button */ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 8e9e0d98db2f..55ef53571fdd 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -129,8 +129,8 @@ pinctrl-0 = <&pinctrl_gpio_leds>; red { - gpios = <&gpio1 2 0>; - default-state = "on"; + gpios = <&gpio1 2 0>; + default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index ac9529f85593..2bf2e623ac1e 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -429,8 +429,8 @@ pinctrl_edt_ft5x06: edt-ft5x06grp { fsl,pins = < MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ >; }; @@ -481,21 +481,21 @@ pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi index ef7fa62b9898..a32089132263 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi @@ -28,7 +28,7 @@ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 2b9c2be436f9..82dc5744ae19 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -129,8 +129,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b13b0b2db881..89b834f3fa17 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -13,9 +13,10 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; can0 = &can1; @@ -204,9 +205,9 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; @@ -1092,10 +1093,14 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; }; ocotp: ocotp@021bc000 { diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 886dbf2eca49..0d4977ab7d29 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -85,5 +85,22 @@ pcie: pcie@0x01000000 { compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; }; + + aips-bus@02100000 { + mmdc0: mmdc@021b0000 { /* MMDC0 */ + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + }; }; }; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; +}; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 02378db3f5fc..19cbd879c448 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -8,11 +8,13 @@ */ #include -#include "skeleton.dtsi" #include "imx6sl-pinfunc.h" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec; gpio0 = &gpio1; @@ -893,8 +895,12 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; reg = <0x021b8000 0x4000>; interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; }; ocotp: ocotp@021bc000 { diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 9d70cfd40aff..da815527a7f8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -192,10 +192,10 @@ }; &i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; codec: wm8962@1a { compatible = "wlf,wm8962"; @@ -290,6 +290,14 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts new file mode 100644 index 000000000000..0c1fc1a8f913 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Basic"; + compatible = "udoo,neobasic", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts new file mode 100644 index 000000000000..5d6c2274ee2b --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Extended"; + compatible = "udoo,neoextended", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts new file mode 100644 index 000000000000..653ceb29e28b --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx-udoo-neo.dtsi" + +/ { + model = "UDOO Neo Full"; + compatible = "udoo,neofull", "fsl,imx6sx"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; + +&fec1 { + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi new file mode 100644 index 000000000000..2b65d26f4396 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6sx.dtsi" + +/ { + compatible = "fsl,imx6sx"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + red { + label = "udoo-neo:red:mmc"; + gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + orange { + label = "udoo-neo:orange:user"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + reg_sdio_pwr: regulator-sdio-pwr { + compatible = "regulator-fixed"; + gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "SDIO_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = + , + , + , + , + , + , + + , + , + , + , + , + , + + ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = + , + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , + ; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = + , + ; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , + , + , + , + , + , + ; /* CD */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Cortex-M4 serial */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +/* Arduino serial */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_sdio_pwr>; + bus-width = <4>; + cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 1a473e83efbf..10f333016197 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -11,9 +11,11 @@ #include #include #include "imx6sx-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { can0 = &flexcan1; can1 = &flexcan2; @@ -858,7 +860,7 @@ fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; status = "disabled"; - }; + }; mlb: mlb@0218c000 { reg = <0x0218c000 0x4000>; @@ -968,10 +970,14 @@ }; weim: weim@021b8000 { + #address-cells = <2>; + #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; }; ocotp: ocotp@021bc000 { @@ -1143,7 +1149,7 @@ lcdif1: lcdif@02220000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; @@ -1154,7 +1160,7 @@ lcdif2: lcdif@02224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; @@ -1181,7 +1187,7 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; adc2: adc@02284000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; @@ -1192,7 +1198,7 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; wdog3: wdog@02288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index e281d5087d4a..00f98e5bfcaf 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -225,7 +225,7 @@ }; &usbotg1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; @@ -235,6 +235,14 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/imx6ul-liteboard.dts new file mode 100644 index 000000000000..6e04cb9202f4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-liteboard.dts @@ -0,0 +1,147 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul-litesom.dtsi" + +/ { + model = "Grinn i.MX6UL liteBoard"; + compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom", + "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usb_otg1_vbus: usb-otg1-vbus { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79 + >; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi new file mode 100644 index 000000000000..461292d33417 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright 2016 Grinn + * + * Author: Marcin Niestroj + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" + +/ { + model = "Grinn i.MX6UL liteSOM"; + compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 + >; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c5c05fdccc78..39845a7e0463 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -11,9 +11,11 @@ #include #include #include "imx6ul-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { ethernet0 = &fec1; ethernet1 = &fec2; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts new file mode 100644 index 000000000000..db5bc076e1cc --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul-14x14-evk.dts" + +/ { + model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + assigned-clock-rates = <320000000>; +}; diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h new file mode 100644 index 000000000000..118202336691 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-pinfunc.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_H +#define __DTS_IMX6ULL_PINFUNC_H + +#include "imx6ul-pinfunc.h" +/* + * The pin function ID is a tuple of + * + */ +#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi new file mode 100644 index 000000000000..dee8ab8135e1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" +#include "imx6ull-pinfunc.h" diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index 3f9f0d9c8094..7bc3c00e56c6 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -43,26 +43,30 @@ #define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 #define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 #define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 #define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 #define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 #define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 #define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 #define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 #define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 #define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 #define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 #define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 #define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 #define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 #define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 #define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 2b6cb05bc01a..8ff2cbdd8f0d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -46,9 +46,11 @@ #include #include #include "imx7d-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { gpio0 = &gpio1; gpio1 = &gpio2; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 6f16d09dc5a4..e8b249f92fb3 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -10,6 +10,41 @@ compatible = "arm,integrator-ap"; dma-ranges = <0x80000000 0x0 0x80000000>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm926ej-s"; */ + reg = <0>; + /* + * The documentation in ARM DUI 0138E page 3-12 states + * that the maximum frequency for this clock is 200 MHz + * but painful trial-and-error has proved to me that it + * is actually just hanging the system above 71 MHz. + * Sad but true. + */ + /* kHz uV */ + operating-points = <71000 0 + 66000 0 + 60000 0 + 48000 0 + 36000 0 + 24000 0 + 12000 0>; + clocks = <&cmosc>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + aliases { arm,timer-primary = &timer2; arm,timer-secondary = &timer1; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 1b5e4b006b72..97f38b57a702 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -13,6 +13,32 @@ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm920t"; */ + reg = <0>; + /* + * TBD comment. + */ + /* kHz uV */ + operating-points = <50000 0 + 48000 0>; + clocks = <&cmcore>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + /* * The Integrator/CP overall clocking architecture can be found in * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 2919c5190653..63c7cf0c6b6d 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -72,6 +72,7 @@ soc { #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; compatible = "ti,keystone","simple-bus"; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 2ee3d0ac2816..0c5e74e79ba2 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -59,6 +59,7 @@ reg = <0x02620690 0xc>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x1>; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 1e9a72100a45..330aada6d33f 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -4,7 +4,7 @@ #include "kirkwood-6282.dtsi" / { - model = "Univeral Scientific Industrial Co. Topkick-1281P2"; + model = "Universal Scientific Industrial Co. Topkick-1281P2"; compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; memory { diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b5841fab51c1..d81fe433e3c8 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -479,6 +479,8 @@ compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; status = "disabled"; }; @@ -486,6 +488,8 @@ compatible = "nxp,lpc3220-pwm"; reg = <0x4005C004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e21934285..282d854f4342 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -47,6 +47,7 @@ #include "skeleton64.dtsi" #include +#include / { compatible = "fsl,ls1021a"; @@ -70,14 +71,15 @@ #address-cells = <1>; #size-cells = <0>; - cpu@f00 { + cpu0: cpu@f00 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; clocks = <&cluster1_clk>; + #cooling-cells = <2>; }; - cpu@f01 { + cpu1: cpu@f01 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; @@ -251,6 +253,84 @@ }; }; + tmu: tmu@1f00000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f00000 0x0 0x10000>; + interrupts = ; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; + fsl,tmu-calibration = <0x00000000 0x0000000f + 0x00000001 0x00000017 + 0x00000002 0x0000001e + 0x00000003 0x00000026 + 0x00000004 0x0000002e + 0x00000005 0x00000035 + 0x00000006 0x0000003d + 0x00000007 0x00000044 + 0x00000008 0x0000004c + 0x00000009 0x00000053 + 0x0000000a 0x0000005b + 0x0000000b 0x00000064 + + 0x00010000 0x00000011 + 0x00010001 0x0000001c + 0x00010002 0x00000024 + 0x00010003 0x0000002b + 0x00010004 0x00000034 + 0x00010005 0x00000039 + 0x00010006 0x00000042 + 0x00010007 0x0000004c + 0x00010008 0x00000051 + 0x00010009 0x0000005a + 0x0001000a 0x00000063 + + 0x00020000 0x00000013 + 0x00020001 0x00000019 + 0x00020002 0x00000024 + 0x00020003 0x0000002c + 0x00020004 0x00000035 + 0x00020005 0x0000003d + 0x00020006 0x00000046 + 0x00020007 0x00000050 + 0x00020008 0x00000059 + + 0x00030000 0x00000002 + 0x00030001 0x0000000d + 0x00030002 0x00000019 + 0x00030003 0x00000024>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + dspi0: dspi@2100000 { compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/mps2-an385.dts index 31c374d72a6f..aebbebfc25d1 100644 --- a/arch/arm/boot/dts/mps2-an385.dts +++ b/arch/arm/boot/dts/mps2-an385.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:9600n8"; }; - memory { + memory@21000000 { device_type = "memory"; reg = <0x21000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts index 5e7e5ca2edbf..349abf70b2a5 100644 --- a/arch/arm/boot/dts/mps2-an399.dts +++ b/arch/arm/boot/dts/mps2-an399.dts @@ -59,7 +59,7 @@ stdout-path = "serial0:9600n8"; }; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index efb8a03cb970..23467390558d 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -42,10 +42,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + oscclk0: clk-osc0 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 18596a2c58a1..7eab6f4c4665 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,8 +12,10 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include "skeleton64.dtsi" #include "mt2701-pinfunc.h" @@ -71,10 +73,18 @@ #clock-cells = <0>; }; - uart_clk: dummy26m { + clk26m: oscillator@0 { compatible = "fixed-clock"; - clock-frequency = <26000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + rtc32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; }; timer { @@ -104,6 +114,26 @@ reg = <0 0x10005000 0 0x1000>; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt2701-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2701-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2701-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; @@ -128,6 +158,12 @@ reg = <0 0x10200100 0 0x1c>; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2701-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; @@ -144,7 +180,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -153,7 +190,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -162,7 +200,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -171,7 +210,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 4f793a025a72..f1d6de8b3c19 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -17,6 +17,7 @@ interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { serial0 = &uart1; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index fb712b9aa874..aba542d63d6d 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -38,6 +38,7 @@ reg = <0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x0 0x1000>; omap2420_pmx: pinmux@30 { @@ -46,6 +47,7 @@ reg = <0x30 0x0113>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <8>; pinctrl-single,function-mask = <0x3f>; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 455aaea407dd..84635eeb99cd 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -38,6 +38,7 @@ reg = <0x2000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x2000 0x1000>; omap2430_pmx: pinmux@30 { @@ -46,6 +47,7 @@ reg = <0x30 0x0154>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <8>; pinctrl-single,function-mask = <0x3f>; }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 87ca50b53002..4d448f145ed1 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -734,6 +734,8 @@ vmmc_aux-supply = <&vsim>; bus-width = <8>; non-removable; + no-sdio; + no-sd; }; &mmc3 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 353d818ce5a6..a3ff4933dbc1 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -17,6 +17,7 @@ interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c1; @@ -106,6 +107,7 @@ reg = <0x30 0x238>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -145,6 +147,7 @@ reg = <0xa00 0x5c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index e41c52d3b113..834fdf13601f 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -34,6 +34,7 @@ reg = <0x480025d8 0x24>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 718fa88407cd..d1a3e56b50ce 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -66,6 +66,7 @@ reg = <0x480025a0 0x5c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts new file mode 100644 index 000000000000..f3ccb4ceed9e --- /dev/null +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -0,0 +1,188 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap443x.dtsi" + +/ { + model = "Motorola Droid 4 XT894"; + compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; + + chosen { + stdout-path = &uart3; + }; + + /* + * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, + * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes + * below about SRAM and L3_ICLK2 being unused by default, + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x3fd00000>; /* 1021 MB */ + }; + + /* CPCAP really supports 1650000 to 3400000 range */ + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + /* CPCAP really supports 3000000 to 3100000 range */ + vemmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "vemmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + /* CPCAP really supports 1650000 to 1950000 range */ + wl12xx_vmmc: regulator-wl12xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */ +&gpmc { + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + bus-width = <4>; + cd-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ +}; + +&mmc2 { + vmmc-supply = <&vemmc>; + bus-width = <8>; + non-removable; +}; + +&mmc3 { + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0xde>; + + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */ +&ocmcram { + status = "disabled"; +}; + +&omap4_pmx_core { + usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { + /* gpio_60 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) + >; + }; + + usb_ulpi_pins: pinmux_usb_ulpi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + /* usb0_otg_dp and usb0_otg_dm */ + usb_utmi_pins: pinmux_usb_utmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; + + /* uart3_tx_irtx and uart3_rx_irrx */ + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x196, MUX_MODE7) + OMAP4_IOPAD(0x198, MUX_MODE7) + OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1ba, MUX_MODE2) + OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2) + OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7) + OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) + >; + }; +}; + +&omap4_pmx_wkup { + usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + /* gpio_wk0 */ + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; +}; + +&uart3 { + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x17c>; +}; + +/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */ +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 0ced079b7ae3..578c53f08309 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -15,6 +15,7 @@ interrupt-parent = <&wakeupgen>; #address-cells = <1>; #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c1; @@ -184,6 +185,7 @@ reg = <0x40 0x0196>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -256,6 +258,7 @@ reg = <0x1e040 0x0038>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 53d31a87b44b..a8c72611fbe3 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -27,12 +27,98 @@ default-state = "off"; }; }; + + evm_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&evm_keys_pins>; + + #address-cells = <7>; + #size-cells = <0>; + + btn1 { + label = "BTN1"; + linux,code = <169>; + gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ + wakeup-source; + autorepeat; + debounce_interval = <50>; + }; + }; + + evm_leds { + compatible = "gpio-leds"; + + led1 { + label = "omap5:red:led"; + gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "omap5:green:led"; + gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led3 { + label = "omap5:blue:led"; + gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + default-state = "off"; + }; + + led4 { + label = "omap5:green:led1"; + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led5 { + label = "omap5:green:led2"; + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led6 { + label = "omap5:green:led3"; + gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led7 { + label = "omap5:green:led4"; + gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "off"; + }; + + led8 { + label = "omap5:green:led5"; + gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; }; &hdmi { vdda-supply = <&ldo4_reg>; }; +&i2c1 { + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; +}; + &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; @@ -48,6 +134,12 @@ }; &omap5_pmx_core { + evm_keys_pins: pinmux_evm_keys_gpio_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ + >; + }; + i2c5_pins: pinmux_i2c5_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 25262118ec3d..7cd92babc41a 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -17,6 +17,7 @@ compatible = "ti,omap5"; interrupt-parent = <&wakeupgen>; + chosen { }; aliases { i2c0 = &i2c1; @@ -171,6 +172,7 @@ reg = <0x40 0x01b6>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; @@ -270,6 +272,7 @@ reg = <0xc840 0x003c>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; diff --git a/arch/arm/boot/dts/orion5x-lschl.dts b/arch/arm/boot/dts/orion5x-lschl.dts new file mode 100644 index 000000000000..947409252845 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lschl.dts @@ -0,0 +1,171 @@ +/* + * Device Tree file for Buffalo Linkstation LS-CHLv3 + * + * Copyright (C) 2016 Ash Hughes + * Copyright (C) 2015, 2016 + * Roger Shimizu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include "mvebu-linkstation-gpio-simple.dtsi" +#include "mvebu-linkstation-fan.dtsi" +#include + +/ { + model = "Buffalo Linkstation Live v3 (LS-CHL)"; + compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + gpio_keys { + func { + label = "Function Button"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + power-on-switch { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + power-auto-switch { + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds { + pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>; + blue-power-led { + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + red-alarm-led { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + amber-info-led { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + func { + label = "lschl:func:blue:top"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_fan { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW + &gpio0 16 GPIO_ACTIVE_LOW>; + + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + pmx_led_power: pmx-leds { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_led_alarm: pmx-leds { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_led_info: pmx-leds { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_fan_lock: pmx-fan-lock { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_power_switch: pmx-power-switch { + marvell,pins = "mpp8", "mpp10", "mpp15"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_fan_high: pmx-fan-high { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_fan_low: pmx-fan-low { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_led_func: pmx-leds { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_sw_init: pmx-sw-init { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi new file mode 100644 index 000000000000..e40f282a023a --- /dev/null +++ b/arch/arm/boot/dts/ox820.dtsi @@ -0,0 +1,296 @@ +/* + * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC + * + * Copyright (C) 2016 Neil Armstrong + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" +#include + +/ { + compatible = "oxsemi,ox820"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "oxsemi,ox820-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + clocks = <&armclk>; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + clocks = <&armclk>; + reg = <1>; + }; + }; + + memory { + /* Max 512MB @ 0x60000000 */ + reg = <0x60000000 0x20000000>; + }; + + clocks { + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gmacclk: gmacclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&osc>; + }; + + plla: plla { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <850000000>; + }; + + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clocks = <&plla>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&gic>; + + nandc: nand-controller@41000000 { + compatible = "oxsemi,ox820-nand"; + reg = <0x41000000 0x100000>; + clocks = <&stdclk 11>; + resets = <&reset 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + etha: ethernet@40400000 { + compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; + reg = <0x40400000 0x2000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "rgmii"; + + clocks = <&stdclk 9>, <&gmacclk>; + clock-names = "gmac", "stmmaceth"; + resets = <&reset 6>; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + status = "disabled"; + }; + + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x44000000 0x1000000>; + + pinctrl: pinctrl { + compatible = "oxsemi,ox820-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart0: uart0 { + uart0 { + pins = "gpio30", "gpio31"; + function = "fct5"; + }; + }; + + pinctrl_uart0_modem: uart0_modem { + uart0_modem_a { + pins = "gpio24", "gpio24", "gpio26", "gpio27"; + function = "fct4"; + }; + uart0_modem_b { + pins = "gpio28", "gpio29"; + function = "fct5"; + }; + }; + + pinctrl_uart1: uart1 { + uart1 { + pins = "gpio7", "gpio8"; + function = "fct4"; + }; + }; + + pinctrl_uart1_modem: uart1_modem { + uart1_modem { + pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; + function = "fct4"; + }; + }; + + pinctrl_etha_mdio: etha_mdio { + etha_mdio { + pins = "gpio3", "gpio4"; + function = "fct1"; + }; + }; + + pinctrl_nand: nand { + nand { + pins = "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24"; + function = "fct1"; + }; + }; + }; + + gpio0: gpio@000000 { + compatible = "oxsemi,ox820-gpio"; + reg = <0x000000 0x100000>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <32>; + oxsemi,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + gpio1: gpio@100000 { + compatible = "oxsemi,ox820-gpio"; + reg = <0x100000 0x100000>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <18>; + oxsemi,gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 18>; + }; + + uart0: serial@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + interrupts = ; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + clocks = <&sysclk>; + resets = <&reset 17>; + }; + + uart1: serial@300000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + interrupts = ; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + clocks = <&sysclk>; + resets = <&reset 18>; + }; + + rps@400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x400000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; + interrupt-controller; + reg = <0 0x200>; + interrupts = ; + #interrupt-cells = <1>; + valid-mask = <0xFFFFFFFF>; + clear-mask = <0>; + }; + + timer0: timer@200 { + compatible = "oxsemi,ox820-rps-timer"; + reg = <0x200 0x40>; + clocks = <&sysclk>; + interrupt-parent = <&intc>; + interrupts = <4>; + }; + }; + + sys: sys-ctrl@e00000 { + compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; + reg = <0xe00000 0x200000>; + + reset: reset-controller { + compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; + #reset-cells = <1>; + }; + + stdclk: stdclk { + compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; + }; + }; + + apb-bridge@47000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x47000000 0x1000000>; + + scu: scu@0 { + compatible = "arm,arm11mp-scu"; + reg = <0x0 0x100>; + }; + + local-timer@600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&armclk>; + }; + + gic: gic@1000 { + compatible = "arm,arm11mp-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1000 0x1000>, + <0x100 0x500>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi new file mode 100644 index 000000000000..f9f4726396a0 --- /dev/null +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2016 Robert Jarzmik + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa-clock.h" + +/ { + model = "Marvell PXA25x family SoC"; + compatible = "marvell,pxa250"; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa250-core-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + + /* timer oscillator */ + clktimer: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3686400>; + clock-output-names = "ostimer"; + }; + }; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-channels = <16>; + #dma-cells = <2>; + #dma-requests = <40>; + status = "okay"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <32>; + }; + + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa25x-pinctrl"; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa25x-gpio"; + gpio-ranges = <&pinctrl 0 0 84>; + clocks = <&clks CLK_NONE>; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clktimer>; + status = "okay"; + }; + + pxa250_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@99532800 { + opp-hz = /bits/ 64 <99532800>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@199065600 { + opp-hz = /bits/ 64 <199065600>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@298598400 { + opp-hz = /bits/ 64 <298598400>; + opp-microvolt = <1100000 1045000 1650000>; + clock-latency-ns = <20>; + }; + opp@398131200 { + opp-hz = /bits/ 64 <398131200>; + opp-microvolt = <1300000 1235000 1650000>; + clock-latency-ns = <20>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 9e73dc6b3ed3..e0fab48ba6fa 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -137,4 +137,44 @@ clocks = <&clks CLK_OSTIMER>; status = "okay"; }; + + pxa270_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@104000000 { + opp-hz = /bits/ 64 <104000000>; + opp-microvolt = <900000 900000 1705000>; + clock-latency-ns = <20>; + }; + opp@156000000 { + opp-hz = /bits/ 64 <156000000>; + opp-microvolt = <1000000 1000000 1705000>; + clock-latency-ns = <20>; + }; + opp@208000000 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1180000 1180000 1705000>; + clock-latency-ns = <20>; + }; + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1250000 1250000 1705000>; + clock-latency-ns = <20>; + }; + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <1350000 1350000 1705000>; + clock-latency-ns = <20>; + }; + opp@520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1450000 1450000 1705000>; + clock-latency-ns = <20>; + }; + opp@624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <1550000 1550000 1705000>; + clock-latency-ns = <20>; + }; + }; }; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 3ff077ca4400..e4ebcde17837 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -54,8 +54,8 @@ reg = <0x40e00000 0x10000>; gpio-controller; #gpio-cells = <0x2>; - interrupts = <10>; - interrupt-names = "gpio_mux"; + interrupts = <8>, <9>, <10>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; interrupt-controller; #interrupt-cells = <0x2>; ranges; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 9d6f3aacedb7..7a0cc4ea819a 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -138,6 +138,7 @@ reg = <0x40e10000 0xffff>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 6c0038398ef2..4b8872cc8bf9 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -51,6 +51,29 @@ regulator-boot-on; }; + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; + + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; + /* This is a levelshifter for SDCC5 */ dragon_vio_txb: txb0104rgyr { compatible = "regulator-fixed"; @@ -167,6 +190,36 @@ bias-pull-up; }; }; + + dragon_ebi2_pins: ebi2 { + /* + * Pins used by EBI2 on the Dragonboard, actually only + * CS2 is used by a real peripheral. CS0 is just + * routed to a test point. + */ + mux0 { + pins = + /* "gpio39", CS1A_N this is not good to mux */ + "gpio40", /* CS2A_N */ + "gpio134"; /* CS0_N testpoint TP29 */ + function = "ebi2cs"; + }; + mux1 { + pins = + /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */ + "gpio135", "gpio136", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", + "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", + "gpio151", /* EBI2_OE_N */ + "gpio153", /* EBI2_ADV */ + "gpio157"; /* EBI2_WE_N */ + function = "ebi2"; + }; + }; }; qcom,ssbi@500000 { @@ -201,6 +254,15 @@ }; gpio@150 { + dragon_ethernet_gpios: ethernet-gpios { + pinconf { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; + }; dragon_bmp085_gpios: bmp085-gpios { pinconf { pins = "gpio16"; @@ -238,6 +300,14 @@ power-source = ; }; }; + dragon_veth_gpios: veth-gpios { + pinconf { + pins = "gpio40"; + function = "normal"; + bias-disable; + drive-push-pull; + }; + }; }; led@48 { @@ -322,6 +392,55 @@ }; }; + external-bus@1a100000 { + /* The EBI2 will instantiate first, then populate its children */ + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ebi2_pins>; + + /* + * An on-board SMSC LAN9221 chip for "debug ethernet", + * which is actually just an ordinary ethernet on the + * EBI2. This has a 25MHz chrystal next to it, so no + * clocking is needed. + */ + ethernet-ebi2@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + /* + * GPIO7 has interrupt 198 on the PM8058 + * The second interrupt is the PME interrupt + * for network wakeup, connected to the TLMM. + */ + interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + vdd33a-supply = <&dragon_veth>; + vddvario-supply = <&dragon_vario>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_ethernet_gpios>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + /* IRQ on edge falling = active low */ + smsc,irq-active-low; + smsc,irq-push-pull; + + /* + * SLOW chipselect config + * Delay 9 cycles (140ns@64MHz) between SMSC + * LAN9221 Ethernet controller reads and writes + * on CS2. + */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; + }; + rpm@104000 { /* * Set up of the PMIC RPM regulators for this board diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index b72e09506448..e39440a86739 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -15,6 +15,20 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + ext_3p3v: regulator-fixed@1 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -99,6 +113,7 @@ l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; }; /* msm_otg-HSUSB_3p3 */ @@ -133,13 +148,14 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; bias-pull-down; + regulator-always-on; }; /* pwm_power for backlight */ l17 { regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; + regulator-max-microvolt = <3000000>; + regulator-always-on; }; /* camera, qdsp6 */ @@ -184,6 +200,63 @@ }; }; + mdp@5100000 { + status = "okay"; + ports { + port@1 { + mdp_dsi1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: mdss_dsi@4700000 { + status = "okay"; + vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ + vdd-supply = <&pm8921_l8>; + vddio-supply = <&pm8921_lvs7>; + avdd-supply = <&pm8921_l11>; + vcss-supply = <&ext_3p3v>; + + panel@0 { + reg = <0>; + compatible = "jdi,lt070me05000"; + + vddp-supply = <&pm8921_l17>; + iovcc-supply = <&pm8921_lvs7>; + + enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; + dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + port@0 { + dsi0_in: endpoint { + remote-endpoint = <&mdp_dsi1_out>; + }; + }; + + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + + dsi-phy@4700200 { + status = "okay"; + vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/ + }; + gsbi@16200000 { status = "okay"; qcom,mode = ; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2eeb0904eaa7..3d37cab3b9a9 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -43,6 +43,17 @@ }; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + soc { pinctrl@800000 { card_detect: card_detect { @@ -64,6 +75,25 @@ bias-disable; }; }; + + hdmi_pinctrl: hdmi-pinctrl { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "hdmi"; + }; + + pinconf_ddc { + pins = "gpio70", "gpio71"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf_hpd { + pins = "gpio72"; + bias-pull-down; + drive-strength = <16>; + }; + }; }; rpm@108000 { @@ -329,5 +359,49 @@ mmc-pwrseq = <&sdcc4_pwrseq>; }; }; + + hdmi-tx@4a00000 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + hdmi-mux-supply = <&ext_3p3v>; + + hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + + ports { + port@0 { + endpoint { + remote-endpoint = <&mdp_dtv_out>; + }; + }; + + port@1 { + endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-phy@4a00400 { + status = "okay"; + + core-vdda-supply = <&pm8921_hdmi_switch>; + }; + + mdp@5100000 { + status = "okay"; + + ports { + port@3 { + endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1dbe697b2e90..407a4610f4a7 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -303,6 +304,9 @@ firmware { scm { compatible = "qcom,scm-apq8064"; + + clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; + clock-names = "core"; }; }; @@ -1060,6 +1064,231 @@ reg = <0x1a400000 0x100>; }; + gpu: adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + + iommus = <&gfx3d 0 + &gfx3d 1 + &gfx3d 2 + &gfx3d 3 + &gfx3d 4 + &gfx3d 5 + &gfx3d 6 + &gfx3d 7 + &gfx3d 8 + &gfx3d 9 + &gfx3d 10 + &gfx3d 11 + &gfx3d 12 + &gfx3d 13 + &gfx3d 14 + &gfx3d 15 + &gfx3d 16 + &gfx3d 17 + &gfx3d 18 + &gfx3d 19 + &gfx3d 20 + &gfx3d 21 + &gfx3d 22 + &gfx3d 23 + &gfx3d 24 + &gfx3d 25 + &gfx3d 26 + &gfx3d 27 + &gfx3d 28 + &gfx3d 29 + &gfx3d 30 + &gfx3d 31 + &gfx3d1 0 + &gfx3d1 1 + &gfx3d1 2 + &gfx3d1 3 + &gfx3d1 4 + &gfx3d1 5 + &gfx3d1 6 + &gfx3d1 7 + &gfx3d1 8 + &gfx3d1 9 + &gfx3d1 10 + &gfx3d1 11 + &gfx3d1 12 + &gfx3d1 13 + &gfx3d1 14 + &gfx3d1 15 + &gfx3d1 16 + &gfx3d1 17 + &gfx3d1 18 + &gfx3d1 19 + &gfx3d1 20 + &gfx3d1 21 + &gfx3d1 22 + &gfx3d1 23 + &gfx3d1 24 + &gfx3d1 25 + &gfx3d1 26 + &gfx3d1 27 + &gfx3d1 28 + &gfx3d1 29 + &gfx3d1 30 + &gfx3d1 31>; + + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mmss_sfpb: syscon@5700000 { + compatible = "syscon"; + reg = <0x5700000 0x70>; + }; + + dsi0: mdss_dsi@4700000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x04700000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI_M_AHB_CLK>, + <&mmcc DSI_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI_CLK>, + <&mmcc DSI1_BYTE_CLK>, + <&mmcc DSI_PIXEL_CLK>, + <&mmcc DSI1_ESC_CLK>; + clock-names = "iface_clk", "bus_clk", "core_mmss_clk", + "src_clk", "byte_clk", "pixel_clk", + "core_clk"; + + assigned-clocks = <&mmcc DSI1_BYTE_SRC>, + <&mmcc DSI1_ESC_SRC>, + <&mmcc DSI_SRC>, + <&mmcc DSI_PIXEL_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi0_phy 1>; + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi0_phy>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + + dsi0_phy: dsi-phy@4700200 { + compatible = "qcom,dsi-phy-28nm-8960"; + #clock-cells = <1>; + + reg = <0x04700200 0x100>, + <0x04700300 0x200>, + <0x04700500 0x5c>; + reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; + clock-names = "iface_clk"; + clocks = <&mmcc DSI_M_AHB_CLK>; + }; + + + mdp_port0: iommu@7500000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + mdp_port1: iommu@7600000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07600000 0x100000>; + interrupts = + , + ; + qcom,ncb = <2>; + }; + + gfx3d: iommu@7c00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07c00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + + gfx3d1: iommu@7d00000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg = <0x07d00000 0x100000>; + interrupts = + , + ; + qcom,ncb = <3>; + }; + pcie: pci@1b500000 { compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; reg = <0x1b500000 0x1000 @@ -1095,6 +1324,102 @@ reset-names = "axi", "ahb", "por", "pci", "phy"; status = "disabled"; }; + + hdmi: hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg = <0x04a00000 0x2f0>; + reg-names = "core_physical"; + interrupts = ; + clocks = <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + clock-names = "core_clk", + "master_iface_clk", + "slave_iface_clk"; + + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + hdmi_out: endpoint { + }; + }; + }; + }; + + hdmi_phy: hdmi-phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + reg-names = "hdmi_phy", + "hdmi_pll"; + + clocks = <&mmcc HDMI_S_AHB_CLK>; + clock-names = "slave_iface_clk"; + }; + + mdp: mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = ; + clocks = <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + clock-names = "core_clk", + "iface_clk", + "bus_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + + iommus = <&mdp_port0 0 + &mdp_port0 2 + &mdp_port1 0 + &mdp_port1 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + }; + }; + }; + }; }; }; #include "qcom-apq8064-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 39eb7a4ed16a..80d48867107f 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -182,13 +182,13 @@ }; clocks { - xo_board { + xo_board: xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -416,8 +416,10 @@ reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; status = "disabled"; }; @@ -427,8 +429,10 @@ reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts new file mode 100644 index 000000000000..26160c324802 --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -0,0 +1,281 @@ +/* + * Device Tree Source for mangOH Green Board with WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "qcom-mdm9615-wp8548.dtsi" +#include +#include + +/ { + model = "MangOH Green with WP8548 Module"; + compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615"; + + aliases { + spi0 = &gsbi3_spi; + serial0 = &gsbi4_serial; + serial1 = &gsbi5_serial; + i2c0 = &gsbi5_i2c; + mmc0 = &sdcc1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&msmgpio { + /* MangOH GPIO Mapping : + * - 2 : GPIOEXP_INT2 + * - 7 : IOT1_GPIO2 + * - 8 : IOT0_GPIO4 + * - 13: IOT0_GPIO3 + * - 21: IOT1_GPIO4 + * - 22: IOT2_GPIO1 + * - 23: IOT2_GPIO2 + * - 24: IOT2_GPIO3 + * - 25: IOT1_GPIO1 + * - 32: IOT1_GPIO3 + * - 33: IOT0_GPIO2 + * - 42: IOT0_GPIO1 and SD Card Detect + */ + + gpioext1_pins: gpioext1_pins { + pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + sdc_cd_pins: sdc_cd_pins { + pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi3_spi { + spi@0 { + compatible = "swir,mangoh-iotport-spi", "spidev"; + spi-max-frequency = <24000000>; + reg = <0>; + }; +}; + +&gsbi5_i2c { + mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c_iot0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_iot1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_iot2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + usbhub: hub@8 { + compatible = "smsc,usb3503a"; + reg = <0x8>; + connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>; + intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpioext0: gpio@3e { + /* GPIO Expander 0 Mapping : + * - 0: ARDUINO_RESET_Level shift + * - 1: BattChrgr_PG_N + * - 2: BattGauge_GPIO + * - 3: LED_ON (out active high) + * - 4: ATmega_reset_GPIO + * - 5: X + * - 6: PCM_ANALOG_SELECT (out active high) + * - 7: X + * - 8: Board_rev_res1 (in) + * - 9: Board_rev_res2 (in) + * - 10: UART_EXP1_ENn (out active low / pull-down) + * - 11: UART_EXP1_IN (out pull-down) + * - 12: UART_EXP2_IN (out pull-down) + * - 13: SDIO_SEL (out pull-down) + * - 14: SPI_EXP1_ENn (out active low / pull-down) + * - 15: SPI_EXP1_IN (out pull-down) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&gpioext1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + gpioext1: gpio@3f { + /* GPIO Expander 1 Mapping : + * - 0: GPIOEXP_INT1 + * - 1: Battery detect + * - 2: GPIO_SCF3_RESET + * - 3: LED_CARD_DETECT_IOT0 (in) + * - 4: LED_CARD_DETECT_IOT1 (in) + * - 5: LED_CARD_DETECT_IOT2 (in) + * - 6: UIM2_PWM_SELECT + * - 7: UIM2_M2_S_SELECT + * - 8: TP900 + * - 9: SENSOR_INT1 (in) + * - 10: SENSOR_INT2 (in) + * - 11: CARD_DETECT_IOT0 (in pull-up) + * - 12: CARD_DETECT_IOT2 (in pull-up) + * - 13: CARD_DETECT_IOT1 (in pull-up) + * - 14: GPIOEXP_INT3 (in active low / pull-up) + * - 15: BattChrgr_INT_N + */ + pinctrl-0 = <&gpioext1_pins>; + pinctrl-names = "default"; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3f>; + interrupt-parent = <&msmgpio>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + gpioext2: gpio@70 { + /* GPIO Expander 2 Mapping : + * - 0: USB_HUB_INTn + * - 1: HUB_CONNECT + * - 2: GPIO_IOT2_RESET (out active low / pull-up) + * - 3: GPIO_IOT1_RESET (out active low / pull-up) + * - 4: GPIO_IOT0_RESET (out active low / pull-up) + * - 5: TP901 + * - 6: TP902 + * - 7: TP903 + * - 8: UART_EXP2_ENn (out active low / pull-down) + * - 9: PCM_EXP1_ENn (out active low) + * - 10: PCM_EXP1_SEL (out) + * - 11: ARD_FTDI + * - 12: TP904 + * - 13: TP905 + * - 14: TP906 + * - 15: RS232_Enable (out active high / pull-up) + */ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x70>; + interrupt-parent = <&gpioext1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + probe-reset; + + gpio-controller; + interrupt-controller; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&sdcc1 { + pinctrl-0 = <&sdc_cd_pins>; + pinctrl-names = "default"; + disable-wp; + cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */ +}; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi new file mode 100644 index 000000000000..7869898e392d --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -0,0 +1,170 @@ +/* + * Device Tree Source for Sierra Wireless WP8548 Module + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "qcom-mdm9615.dtsi" + +/ { + model = "Sierra Wireless WP8548 Module"; + compatible = "swir,wp8548", "qcom,mdm9615"; + + memory { + reg = <0x48000000 0x7F00000>; + }; +}; + +&msmgpio { + pinctrl-0 = <&reset_out_pins>; + pinctrl-names = "default"; + + gsbi3_pins: gsbi3_pins { + mux { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi4_pins: gsbi4_pins { + mux { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gsbi4"; + drive-strength = <8>; + bias-disable; + }; + }; + + gsbi5_i2c_pins: gsbi5_i2c_pins { + pin16 { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + pin17 { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + + gsbi5_uart_pins: gsbi5_uart_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + reset_out_pins: reset_out_pins { + pins { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; + +&pmicgpio { + usb_vbus_5v_pins: usb_vbus_5v_pins { + pins = "gpio4"; + function = "normal"; + output-high; + bias-disable; + qcom,drive-strength = <1>; + power-source = <2>; + }; +}; + +&gsbi3 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi3_spi { + status = "ok"; + pinctrl-0 = <&gsbi3_pins>; + pinctrl-names = "default"; + assigned-clocks = <&gcc GSBI3_QUP_CLK>; + assigned-clock-rates = <24000000>; +}; + +&gsbi4 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi4_serial { + status = "ok"; + pinctrl-0 = <&gsbi4_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "ok"; + qcom,mode = ; +}; + +&gsbi5_i2c { + status = "ok"; + clock-frequency = <200000>; + pinctrl-0 = <&gsbi5_i2c_pins>; + pinctrl-names = "default"; +}; + +&gsbi5_serial { + status = "ok"; + pinctrl-0 = <&gsbi5_uart_pins>; + pinctrl-names = "default"; +}; + +&sdcc1 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi new file mode 100644 index 000000000000..5ae4ec59e6ea --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -0,0 +1,557 @@ +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = ; + }; + + clocks { + cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + regulators { + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: l2-cache@2040000 { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = , + , + ; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = ; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi@16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = ; + spi-max-frequency = <24000000>; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c@16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = ; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8018", "qcom,pm8921"; + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpp@50 { + compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@11d { + compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio@150 { + compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_NONE>, + <25 IRQ_TYPE_NONE>, + <26 IRQ_TYPE_NONE>, + <27 IRQ_TYPE_NONE>, + <28 IRQ_TYPE_NONE>, + <29 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam: dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam: dma@12142000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = ; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: sdcc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 8c65e0d82559..4d828f810746 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,6 +141,23 @@ }; }; + external-bus@1a100000 { + compatible = "qcom,msm8660-ebi2"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x1a800000 0x00800000>, + <1 0x0 0x1b000000 0x00800000>, + <2 0x0 0x1b800000 0x00800000>, + <3 0x0 0x1d000000 0x08000000>, + <4 0x0 0x1c800000 0x00800000>, + <5 0x0 0x1c000000 0x00800000>; + reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; + reg-names = "ebi2", "xmem"; + clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; + clock-names = "ebi2x", "ebi2"; + status = "disabled"; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index c0fb4a698c56..382bcc3231a9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -224,6 +224,35 @@ status = "ok"; }; + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d2109475bdfd..49d579f28865 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -220,13 +220,13 @@ }; clocks { - xo_board { + xo_board: xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -558,8 +558,10 @@ reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; status = "disabled"; }; @@ -569,8 +571,10 @@ reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index e5dea5bb4032..dd4418195ca6 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -56,6 +56,11 @@ }; }; +&sdhi1 { + bus-width = <4>; + status = "okay"; +}; + &scif2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index fb9ef9ca120e..3dd427d68c83 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -117,6 +117,15 @@ clock-output-names = "ether"; }; + mstp8_clks: mstp8_clks@fcfe0434 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0434 4>; + clocks = <&p1_clk>; + clock-indices = ; + clock-output-names = "mmcif"; + }; + mstp9_clks: mstp9_clks@fcfe0438 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -140,6 +149,14 @@ >; clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; }; + mstp12_clks: mstp12_clks@fcfe0444 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; + clocks = <&p1_clk>, <&p1_clk>; + clock-indices = ; + clock-output-names = "sdhi1", "sdhi0"; + }; }; cpus { @@ -441,4 +458,42 @@ #size-cells = <0>; status = "disabled"; }; + + mmcif: mmc@e804c800 { + compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; + reg = <0xe804c800 0x80>; + interrupts = ; + clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; + reg-io-width = <4>; + bus-width = <8>; + status = "disabled"; + }; + + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sd@e804e800 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e800 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index ca8672778fe0..53183ffe04c1 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -751,6 +751,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 159e04eb1b9e..34159a8349de 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include #include #include @@ -17,6 +15,8 @@ / { compatible = "renesas,r8a7740"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts new file mode 100644 index 000000000000..3a22538208f2 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -0,0 +1,57 @@ +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743.dtsi" + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi new file mode 100644 index 000000000000..216cb1f37f87 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,476 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts new file mode 100644 index 000000000000..97840b340197 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -0,0 +1,52 @@ +/* + * Device Tree Source for the SK-RZG1E board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745.dtsi" + +/ { + model = "SK-RZG1E"; + compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif2 { + status = "okay"; +}; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi new file mode 100644 index 000000000000..0b2e2f37150f --- /dev/null +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -0,0 +1,476 @@ +/* + * Device Tree Source for the r8a7745 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7745"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; + power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA7: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7745_PD_CA7_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7745", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7745-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7745-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7745-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7745", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7745", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7745", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7745", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7745", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7745"; + reg = <0 0xee700000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 3d0a18abd408..d0db998effc8 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -14,8 +14,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include #include #include @@ -23,6 +21,8 @@ / { compatible = "renesas,r8a7778"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 541678df90a9..676151b70185 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -170,7 +170,7 @@ du_pins: du { du0 { - groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in"; function = "du0"; }; du1 { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8cf16008a09b..55a7c1e37c57 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -9,8 +9,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include #include #include @@ -19,6 +17,8 @@ / { compatible = "renesas,r8a7779"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; @@ -420,7 +420,7 @@ du: display@fff80000 { compatible = "renesas,du-r8a7779"; - reg = <0 0xfff80000 0 0x40000>; + reg = <0xfff80000 0x40000>; interrupts = ; clocks = <&mstp1_clks R8A7779_CLK_DU>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -590,6 +590,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0xff000044 4>; + }; + rst: reset-controller@ffcc0000 { compatible = "renesas,r8a7779-reset-wdt"; reg = <0xffcc0000 0x48>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 52b56fcaddf2..bd512c86e852 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -50,7 +50,9 @@ aliases { serial0 = &scif0; serial1 = &scifa1; - i2c8 = "i2cexio"; + i2c8 = &gpioi2c1; + i2c10 = &i2cexio0; + i2c11 = &i2cexio1; }; chosen { @@ -231,12 +233,23 @@ }; }; + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con: endpoint { + hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; @@ -254,6 +267,17 @@ clock-frequency = <148500000>; }; + gpioi2c1: i2c-8 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */ + &gpio1 16 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + /* * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. * We use the I2C demuxer, so the desired IP core can be selected at runtime @@ -262,11 +286,26 @@ * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and * instantiate the slave device at runtime according to the documentation. * You can then communicate with the slave via IIC3. + * + * IIC0/I2C0 does not appear to support fallback to GPIO. */ - i2cexio: i2c-8 { + i2cexio0: i2c-10 { compatible = "i2c-demux-pinctrl"; i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio"; + i2c-bus-name = "i2c-exio0"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). + * This is similar to the arangement described for i2cexio0 (above) + * with a fallback to GPIO also provided. + */ + i2cexio1: i2c-11 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; #address-cells = <1>; #size-cells = <0>; }; @@ -392,6 +431,11 @@ function = "iic0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + iic1_pins: iic1 { groups = "iic1"; function = "iic1"; @@ -427,6 +471,11 @@ function = "usb2"; }; + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + vin1_pins: vin1 { groups = "vin1_data8", "vin1_clk"; function = "vin1"; @@ -559,6 +608,7 @@ vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; @@ -580,18 +630,22 @@ &i2c0 { pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio"; + pinctrl-names = "i2c-exio0"; }; &iic0 { pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio"; + pinctrl-names = "i2c-exio0"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; }; &iic1 { - status = "okay"; pinctrl-0 = <&iic1_pins>; - pinctrl-names = "default"; + pinctrl-names = "i2c-exio1"; }; &iic2 { @@ -646,7 +700,34 @@ port@1 { reg = <1>; adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; }; }; }; @@ -722,6 +803,25 @@ status = "okay"; }; +/* HDMI video input */ +&vin0 { + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + port { + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + /* composite video input */ &vin1 { pinctrl-0 = <&vin1_pins>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 3f10b0bf1b08..0c8900d4b824 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -711,7 +711,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "fck"; @@ -725,7 +725,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "fck"; @@ -739,7 +739,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7790", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "fck"; @@ -1471,6 +1471,11 @@ }; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index f8a7d090fd01..5405d337d744 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -50,6 +50,8 @@ aliases { serial0 = &scif0; serial1 = &scif1; + i2c9 = &gpioi2c1; + i2c12 = &i2cexio1; }; chosen { @@ -265,12 +267,23 @@ }; }; + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; port { - hdmi_con: endpoint { + hdmi_con_out: endpoint { remote-endpoint = <&adv7511_out>; }; }; @@ -287,6 +300,29 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c1: i2c-9 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */ + &gpio7 15 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + + /* + * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio1: i2c-12 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c1>, <&gpioi2c1>; + i2c-bus-name = "i2c-exio1"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -322,6 +358,11 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + i2c2_pins: i2c2 { groups = "i2c2"; function = "i2c2"; @@ -360,16 +401,37 @@ sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; }; sdhi2_pins: sd2 { groups = "sdhi2_data4", "sdhi2_ctrl"; function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; }; qspi_pins: qspi { @@ -393,6 +455,11 @@ function = "usb1"; }; + vin0_pins: vin0 { + groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; + function = "vin0"; + }; + vin1_pins: vin1 { groups = "vin1_data8", "vin1_clk"; function = "vin1"; @@ -454,33 +521,40 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; @@ -538,6 +612,11 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "i2c-exio1"; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -590,7 +669,34 @@ port@1 { reg = <1>; adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; + + hdmi-in@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + adv7612_out: endpoint { + remote-endpoint = <&vin0ep2>; }; }; }; @@ -672,6 +778,27 @@ cpu0-supply = <&vdd_dvfs>; }; +/* HDMI video input */ +&vin0 { + status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin0ep2: endpoint { + remote-endpoint = <&adv7612_out>; + bus-width = <24>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + data-active = <1>; + }; + }; +}; + /* composite video input */ &vin1 { status = "okay"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index c465c79bcca6..87214668d70f 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -584,6 +584,7 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -596,6 +597,7 @@ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -608,6 +610,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -699,7 +702,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; clock-names = "fck"; @@ -713,7 +716,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; clock-names = "fck"; @@ -727,7 +730,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7791", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; clock-names = "fck"; @@ -1487,6 +1490,11 @@ reg = <0 0xe6160000 0 0x0100>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7791-sysc"; reg = <0 0xe6180000 0 0x0200>; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 6dbb94114a93..c24f26fdab1f 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -86,6 +86,34 @@ gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + hdmi-out0 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con0: endpoint { + remote-endpoint = <&adv7513_0_out>; + }; + }; + }; + + hdmi-out1 { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con1: endpoint { + remote-endpoint = <&adv7513_1_out>; + }; + }; + }; + + osc2_clk: osc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -128,6 +156,16 @@ groups = "qspi_ctrl", "qspi_data4"; function = "qspi"; }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; }; &scif0 { @@ -197,3 +235,91 @@ }; }; }; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@3d { + compatible = "adi,adv7513"; + reg = <0x3d>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_0_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7513_0_out: endpoint { + remote-endpoint = <&hdmi_con0>; + }; + }; + }; + }; + + hdmi@39 { + compatible = "adi,adv7513"; + reg = <0x39>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_1_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + + port@1 { + reg = <1>; + adv7513_1_out: endpoint { + remote-endpoint = <&hdmi_con1>; + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins &du1_pins>; + pinctrl-names = "default"; + + clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, + <&osc2_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7513_0_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7513_1_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 6e1f61f65d29..6ced3c1ec377 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -26,6 +26,8 @@ i2c4 = &i2c4; i2c5 = &i2c5; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; vin0 = &vin0; vin1 = &vin1; vin2 = &vin2; @@ -123,6 +125,11 @@ reg = <0 0xe6160000 0 0x0100>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7792-sysc"; reg = <0 0xe6180000 0 0x0200>; @@ -577,6 +584,34 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7792"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7792"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7792"; reg = <0 0xfeb00000 0 0x40000>; @@ -768,6 +803,13 @@ clock-div = <48>; clock-mult = <1>; }; + mp_clk: mp { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + }; m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -798,6 +840,15 @@ }; /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "msiof0"; + }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -816,12 +867,13 @@ compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&zs_clk>, <&zs_clk>; + clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < + R8A7792_CLK_MSIOF1 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 >; - clock-output-names = "sys-dmac1", "sys-dmac0"; + clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7792-mstp-clocks", diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 90af18600124..dc311eba4444 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -346,18 +346,18 @@ }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: qspi { diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index e4b385eccf74..2fb527ca0b15 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -666,7 +666,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; clock-names = "fck"; @@ -680,7 +680,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; clock-names = "fck"; @@ -694,7 +694,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7793", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; clock-names = "fck"; @@ -852,6 +852,33 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7793_CLK_VIN0>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7793_CLK_VIN1>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7793_CLK_VIN2>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + status = "disabled"; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7793", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; @@ -1284,6 +1311,11 @@ reg = <0 0xe6160000 0 0x0100>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7793-sysc"; reg = <0 0xe6180000 0 0x0200>; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 8d1b35afaf82..569e3f0e97a5 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -18,6 +18,8 @@ aliases { serial0 = &scif2; + i2c10 = &gpioi2c4; + i2c12 = &i2cexio4; }; chosen { @@ -135,6 +137,29 @@ #clock-cells = <0>; clock-frequency = <148500000>; }; + + gpioi2c4: i2c-10 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ + &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + + /* + * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). + * A fallback to GPIO is provided. + */ + i2cexio4: i2c-14 { + compatible = "i2c-demux-pinctrl"; + i2c-parent = <&i2c4>, <&gpioi2c4>; + i2c-bus-name = "i2c-exio4"; + #address-cells = <1>; + #size-cells = <0>; + }; }; &du { @@ -165,8 +190,8 @@ pinctrl-names = "default"; du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; - function = "du"; + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; + function = "du1"; }; scif2_pins: scif2 { @@ -194,6 +219,11 @@ function = "i2c1"; }; + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + vin0_pins: vin0 { groups = "vin0_data8", "vin0_clk"; function = "vin0"; @@ -207,11 +237,25 @@ sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; }; }; @@ -255,23 +299,28 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; }; &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; @@ -296,6 +345,11 @@ }; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "i2c-exio4"; +}; + &vin0 { status = "okay"; pinctrl-0 = <&vin0_pins>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 69e4f4fad89b..fb576dba748c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -319,7 +319,7 @@ "ch12"; clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; clock-names = "fck"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <13>; }; @@ -411,7 +411,7 @@ scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; + reg = <0 0xe6c20000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "fck"; @@ -425,7 +425,7 @@ scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; + reg = <0 0xe6c30000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "fck"; @@ -439,7 +439,7 @@ scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7794", "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; + reg = <0 0xe6ce0000 0 0x100>; interrupts = ; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "fck"; @@ -731,6 +731,7 @@ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -743,6 +744,7 @@ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -755,6 +757,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1025,8 +1028,7 @@ clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan"; + "lb", "qspi", "sdh", "sd0", "rcan"; #power-domain-cells = <0>; }; /* Variable factor clocks */ @@ -1260,7 +1262,7 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&mp_clk>, + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>; @@ -1380,6 +1382,11 @@ reg = <0 0xe6160000 0 0x0100>; }; + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7794-sysc"; reg = <0 0xe6180000 0 0x0200>; @@ -1488,67 +1495,67 @@ "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; rcar_sound,dvc { - dvc0: dvc@0 { + dvc0: dvc-0 { dmas = <&audma0 0xbc>; dma-names = "tx"; }; - dvc1: dvc@1 { + dvc1: dvc-1 { dmas = <&audma0 0xbe>; dma-names = "tx"; }; }; rcar_sound,mix { - mix0: mix@0 { }; - mix1: mix@1 { }; + mix0: mix-0 { }; + mix1: mix-1 { }; }; rcar_sound,ctu { - ctu00: ctu@0 { }; - ctu01: ctu@1 { }; - ctu02: ctu@2 { }; - ctu03: ctu@3 { }; - ctu10: ctu@4 { }; - ctu11: ctu@5 { }; - ctu12: ctu@6 { }; - ctu13: ctu@7 { }; + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; rcar_sound,src { - src@0 { + src-0 { status = "disabled"; }; - src1: src@1 { + src1: src-1 { interrupts = ; dmas = <&audma0 0x87>, <&audma0 0x9c>; dma-names = "rx", "tx"; }; - src2: src@2 { + src2: src-2 { interrupts = ; dmas = <&audma0 0x89>, <&audma0 0x9e>; dma-names = "rx", "tx"; }; - src3: src@3 { + src3: src-3 { interrupts = ; dmas = <&audma0 0x8b>, <&audma0 0xa0>; dma-names = "rx", "tx"; }; - src4: src@4 { + src4: src-4 { interrupts = ; dmas = <&audma0 0x8d>, <&audma0 0xb0>; dma-names = "rx", "tx"; }; - src5: src@5 { + src5: src-5 { interrupts = ; dmas = <&audma0 0x8f>, <&audma0 0xb2>; dma-names = "rx", "tx"; }; - src6: src@6 { + src6: src-6 { interrupts = ; dmas = <&audma0 0x91>, <&audma0 0xb4>; dma-names = "rx", "tx"; @@ -1556,61 +1563,61 @@ }; rcar_sound,ssi { - ssi0: ssi@0 { + ssi0: ssi-0 { interrupts = ; dmas = <&audma0 0x01>, <&audma0 0x02>, <&audma0 0x15>, <&audma0 0x16>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi1: ssi@1 { + ssi1: ssi-1 { interrupts = ; dmas = <&audma0 0x03>, <&audma0 0x04>, <&audma0 0x49>, <&audma0 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi2: ssi@2 { + ssi2: ssi-2 { interrupts = ; dmas = <&audma0 0x05>, <&audma0 0x06>, <&audma0 0x63>, <&audma0 0x64>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi3: ssi@3 { + ssi3: ssi-3 { interrupts = ; dmas = <&audma0 0x07>, <&audma0 0x08>, <&audma0 0x6f>, <&audma0 0x70>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi4: ssi@4 { + ssi4: ssi-4 { interrupts = ; dmas = <&audma0 0x09>, <&audma0 0x0a>, <&audma0 0x71>, <&audma0 0x72>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi5: ssi@5 { + ssi5: ssi-5 { interrupts = ; dmas = <&audma0 0x0b>, <&audma0 0x0c>, <&audma0 0x73>, <&audma0 0x74>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi6: ssi@6 { + ssi6: ssi-6 { interrupts = ; dmas = <&audma0 0x0d>, <&audma0 0x0e>, <&audma0 0x75>, <&audma0 0x76>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi7: ssi@7 { + ssi7: ssi-7 { interrupts = ; dmas = <&audma0 0x0f>, <&audma0 0x10>, <&audma0 0x79>, <&audma0 0x7a>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi8: ssi@8 { + ssi8: ssi-8 { interrupts = ; dmas = <&audma0 0x11>, <&audma0 0x12>, <&audma0 0x7b>, <&audma0 0x7c>; dma-names = "rx", "tx", "rxu", "txu"; }; - ssi9: ssi@9 { + ssi9: ssi-9 { interrupts = ; dmas = <&audma0 0x13>, <&audma0 0x14>, <&audma0 0x7d>, <&audma0 0x7e>; diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts new file mode 100644 index 000000000000..3956cff4ca79 --- /dev/null +++ b/arch/arm/boot/dts/rk1108-evb.dts @@ -0,0 +1,69 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk1108.dtsi" + +/ { + model = "Rockchip RK1108 Evaluation board"; + compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi new file mode 100644 index 000000000000..d7700235e0f5 --- /dev/null +++ b/arch/arm/boot/dts/rk1108.dtsi @@ -0,0 +1,452 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rk1108"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rk1108-grf", "syscon"; + reg = <0x10300000 0x1000>; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rk1108-pmugrf", "syscon"; + reg = <0x20060000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rk1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + emmc: dwmmc@30110000 { + compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30110000 0x4000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30120000 0x4000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 100000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30130000 0x4000>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + }; + + i2c2m1_gpio: i2c2m1-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + }; + + i2c2m05v_gpio: i2c2m05v-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index 8db9e9b197a2..2f5f15524fba 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3036 Evaluation board"; compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 1df1557a46c3..3de958ec29c0 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 7c2dc19925a1..4ed49a243e5c 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -44,9 +44,11 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + compatible = "rockchip,rk3036"; interrupt-parent = <&gic>; @@ -243,7 +245,7 @@ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -254,7 +256,7 @@ sdio: dwmmc@10218000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10218000 0x4000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -270,7 +272,7 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index bc674ee206ec..c0d8b5446ba7 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -49,7 +49,7 @@ model = "bq Curie 2"; compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index a2b763e949b4..0a54c4beff8d 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -47,7 +47,7 @@ model = "MarsBoard RK3066"; compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts new file mode 100644 index 000000000000..658eb7ddeaf5 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2016 Paweł Jarosz + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3066a.dtsi" + +/ { + model = "Rikomagic MK808"; + compatible = "rikomagic,mk808", "rockchip,rk3066a"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + device_type = "memory"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue { + label = "mk808:blue:power"; + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "default-on"; + }; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&host_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_wifi: sdio-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + num-slots = <1>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_drv: host-drv { + rockchip,pins = ; + }; + }; + + usb-otg { + otg_drv: otg-drv { + rockchip,pins = ; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = ; + }; + }; + + sdio { + wifi_pwr: wifi-pwr { + rockchip,pins = ; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 6e7f2187a0e3..82465b644443 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -48,7 +48,7 @@ model = "Rayeager PX2"; compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 0d0dae3a1694..e498c362b9e7 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -151,6 +151,14 @@ #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; }; timer@2000e000 { @@ -162,7 +170,7 @@ }; efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3066a-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; @@ -197,7 +205,7 @@ clock-names = "saradc", "apb_pclk"; interrupts = ; #io-channel-cells = <1>; - resets = <&cru SRST_SARADC>; + resets = <&cru SRST_TSADC>; reset-names = "saradc-apb"; status = "disabled"; }; @@ -628,15 +636,26 @@ }; &mmc0 { + clock-frequency = <50000000>; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + max-frequency = <50000000>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; }; &mmc1 { + dmas = <&dmac2 3>; + dma-names = "rx-tx"; pinctrl-names = "default"; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; }; +&emmc { + dmas = <&dmac2 4>; + dma-names = "rx-tx"; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pwm0_out>; @@ -668,21 +687,29 @@ }; &uart0 { + dmas = <&dmac1_s 0>, <&dmac1_s 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; }; &uart1 { + dmas = <&dmac1_s 2>, <&dmac1_s 3>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; }; &uart2 { + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart2_xfer>; }; &uart3 { + dmas = <&dmac2 8>, <&dmac2 9>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart3_xfer>; }; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts new file mode 100644 index 000000000000..df727bafd6dc --- /dev/null +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2016 Andy Yan + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include +#include "rk3188.dtsi" + +/ { + model = "Rockchip PX3-EVB"; + compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x80000000>; + device_type = "memory"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_cif: LDO_REG1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_cif"; + }; + + vcc_jetta33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_jetta33"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + lvds_12: LDO_REG4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "lvds_12"; + }; + + lvds_25: LDO_REG5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lvds_25"; + }; + + cif_18: LDO_REG6 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "cif_18"; + }; + + vcc_sd: LDO_REG7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + wl_18: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wl_18"; + }; + + lcd_33: SWITCH_REG1 { + regulator-name = "lcd_33"; + }; + }; + }; + +}; + +&i2c2 { + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&mmc0 { + num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 1da46d138029..5e8a235ed02d 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -48,7 +48,7 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 31f81b265cef..869e189331ec 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -147,7 +147,7 @@ }; efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3188-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 904668e2e666..58834330a5ba 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3228 Evaluation board"; compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index b6a12035a6bb..dcdd0cee619e 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3229 Evaluation board"; compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 9e6bf0e311bb..9d3aee5abc15 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -44,9 +44,11 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; aliases { @@ -402,7 +404,7 @@ reg = <0x30020000 0x4000>; interrupts = ; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index d59208b5eb6c..bf7ccfad3260 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -43,7 +43,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index 2e3c34135ed8..805c0d26770b 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -46,7 +46,7 @@ model = "Rockchip RK3288 Fennec Board"; compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - memory { + memory@0 { reg = <0x0 0x80000000>; device_type = "memory"; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index ec418c99de95..d242588bae0d 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -45,7 +45,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 114c90fb65e2..44935af1fb0e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -44,7 +44,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 24488421f0f0..441d450fd151 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -52,7 +52,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 56dd377d5658..bc6d10054f6a 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -48,7 +48,7 @@ model = "PopMetal-RK3288"; compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - memory{ + memory@0 { device_type = "memory"; reg = <0 0x80000000>; }; @@ -68,7 +68,7 @@ pinctrl-0 = <&pwrbtn>; power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = ; label = "GPIO Key Power"; linux,input-type = <1>; @@ -79,7 +79,7 @@ ir: ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_int>; }; @@ -94,7 +94,7 @@ vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_pwr>; regulator-name = "vcc_sd"; @@ -128,7 +128,7 @@ vcc28_dvp: vcc28-dvp-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&dvp_pwr>; regulator-name = "vcc28_dvp"; @@ -147,6 +147,8 @@ bus-width = <8>; cap-mmc-highspeed; disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; non-removable; num-slots = <1>; pinctrl-names = "default"; @@ -165,6 +167,10 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; vmmc-supply = <&vcc_sd>; vqmmc-supply = <&vccio_sd>; status = "okay"; @@ -174,7 +180,7 @@ phy-supply = <&vcc_lan>; phy-mode = "rgmii"; clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; + snps,reset-gpio = <&gpio4 RK_PB0 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; assigned-clocks = <&cru SCLK_MAC>; @@ -280,7 +286,7 @@ vccio_sd: LDO_REG2 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-name = "vccio_sd"; regulator-state-mem { @@ -443,43 +449,43 @@ &pinctrl { ak8963 { comp_int: comp-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; buttons { pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; dvp { dvp_pwr: dvp-pwr { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; ir { ir_int: ir-int { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; mma8452 { gsensor_int: gsensor-int { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; pmic { pmic_int: pmic-int { - rockchip,pins = ; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; sdmmc { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 4b8a8adb243c..04faa72dbd95 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -48,7 +48,7 @@ / { compatible = "netxeon,r89", "rockchip,rk3288"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index bb1f01e037ba..b25ba806d5ee 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -42,7 +42,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { reg = <0x0 0x80000000>; device_type = "memory"; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 3dd2cca48c11..2251d28e9d2a 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -47,7 +47,7 @@ #include "rk3288.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 74a749c566ee..4fad13368a7b 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -46,9 +46,11 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + compatible = "rockchip,rk3288"; interrupt-parent = <&gic>; @@ -227,7 +229,7 @@ sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -239,7 +241,7 @@ sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -251,7 +253,7 @@ sdio1: dwmmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -263,7 +265,7 @@ emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -1115,7 +1117,7 @@ }; efuse: efuse@ffb40000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x20>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 8fbd3c806fa0..0b45811cf28b 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -44,9 +44,11 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 7173ec9059a1..ceb9783ff7e1 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -735,6 +735,11 @@ atmel,clk-output-range = <0 83000000>; }; + securam_clk: securam_clk { + #clock-cells = <0>; + reg = <51>; + }; + i2s0_clk: i2s0_clk { #clock-cells = <0>; reg = <54>; @@ -1030,6 +1035,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&twi0_clk>; + atmel,fifo-size = <16>; status = "disabled"; }; @@ -1058,6 +1064,15 @@ status = "disabled"; }; + securam: sram@f8044000 { + compatible = "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xf8044000 0x1420>; + clocks = <&securam_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf8044000 0x1420>; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; @@ -1088,30 +1103,12 @@ status = "disabled"; }; - sckc@f8048050 { - compatible = "atmel,at91sam9x5-sckc"; + clk32k: sckc@f8048050 { + compatible = "atmel,sama5d4-sckc"; reg = <0xf8048050 0x4>; - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; rtc@f80480b0 { @@ -1231,6 +1228,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&twi1_clk>; + atmel,fifo-size = <16>; status = "disabled"; }; @@ -1260,6 +1258,11 @@ clocks = <&pioA_clk>; }; + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + }; + tdes@fc044000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc044000 0x100>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 4c84d333fc7e..b06448ba6649 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -549,8 +549,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PB31 periph A with pullup */ + ; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 65e725fb5679..4f60c1b7b137 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1314,30 +1314,11 @@ status = "disabled"; }; - sckc@fc068650 { - compatible = "atmel,at91sam9x5-sckc"; + clk32k: sckc@fc068650 { + compatible = "atmel,sama5d4-sckc"; reg = <0xfc068650 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; + #clock-cells = <0>; + clocks = <&slow_xtal>; }; rtc@fc0686b0 { @@ -1461,8 +1442,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - , /* conflicts with D14 and TDI */ - ; /* conflicts with D15 and TDO */ + ; /* conflicts with D15 and TDO */ }; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 032fe2f14b16..e1267590b575 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -8,8 +8,6 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" - #include #include #include @@ -17,6 +15,8 @@ / { compatible = "renesas,sh73a0"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 9f48141270b8..da689659131f 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -686,6 +686,12 @@ arm,data-latency = <2 1 1>; prefetch-data = <1>; prefetch-instr = <1>; + arm,shared-override; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <0>; + arm,prefetch-offset = <7>; }; mmc: dwmmc0@ff704000 { @@ -700,11 +706,38 @@ status = "disabled"; }; + nand0: nand@ff900000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "denali,denali-nand-dt"; + reg = <0xff900000 0x100000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0x0 0x90 0x4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>; + status = "disabled"; + }; + ocram: sram@ffff0000 { compatible = "mmio-sram"; reg = <0xffff0000 0x10000>; }; + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f520cbff5e1c..551c636a4f01 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -562,6 +562,21 @@ status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; @@ -573,6 +588,9 @@ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff808000 { @@ -657,6 +675,20 @@ }; }; + qspi: spi@ff809000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 8e3a4adc389f..eb00ae37f316 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -36,6 +36,30 @@ reg = <0x0 0x40000000>; /* 1GB */ }; + a10leds { + compatible = "gpio-leds"; + + a10sr_led0 { + label = "a10sr-led0"; + gpios = <&a10sr_gpio 0 1>; + }; + + a10sr_led1 { + label = "a10sr-led1"; + gpios = <&a10sr_gpio 1 1>; + }; + + a10sr_led2 { + label = "a10sr-led2"; + gpios = <&a10sr_gpio 2 1>; + }; + + a10sr_led3 { + label = "a10sr-led3"; + gpios = <&a10sr_gpio 3 1>; + }; + }; + soc { clkmgr@ffd04000 { clocks { @@ -75,6 +99,31 @@ status = "okay"; }; +&gpio1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + /* low-level active IRQ at GPIO1_5 */ + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + &i2c1 { speed-mode = <0>; status = "okay"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 000000000000..beb2fc6b9eb6 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Intel. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00aa"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + label = "Boot and fpga data"; + reg = <0x0 0x2720000>; + }; + + partition@qspi-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x2720000 0x58E0000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 3c8867862b0d..f739ead074a2 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -82,6 +82,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts index afea3645ada4..5ecd2ef405e3 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts @@ -18,7 +18,7 @@ / { model = "Terasic DE-0(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index f86f9c060d7a..6ad3b1eb9b86 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,7 +18,7 @@ #include "socfpga_cyclone5.dtsi" / { - model = "DENX MCV"; + model = "Aries/DENX MCV"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts index 7186a29b8b86..e5a98e5696ca 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts @@ -18,8 +18,8 @@ #include "socfpga_cyclone5_mcv.dtsi" / { - model = "DENX MCV EVK"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + model = "Aries/DENX MCV EVK"; + compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 15e43f43f244..6306d008f01b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -19,7 +19,7 @@ / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -87,6 +87,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 02e22f554ef0..a0c90b3bdfd1 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -19,7 +19,7 @@ / { model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -175,6 +175,27 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index d79853775061..c3d52f27b21e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -80,3 +80,22 @@ &mmc { status = "okay"; }; + +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts new file mode 100644 index 000000000000..5b7e3c27e6e9 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2016 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "socfpga_cyclone5.dtsi" +#include +#include + +/ { + model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board"; + compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:green:led0"; + gpios = <&portb 12 GPIO_ACTIVE_LOW>; + }; + + hps_led1 { + label = "hps:green:led1"; + gpios = <&portb 13 GPIO_ACTIVE_LOW>; + }; + + hps_led2 { + label = "hps:green:led2"; + gpios = <&portb 14 GPIO_ACTIVE_LOW>; + }; + + hps_led3 { + label = "hps:green:led3"; + gpios = <&portb 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index b844473601d2..363ee62457fe 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -51,7 +51,7 @@ / { model = "samtec VIN|ING FPGA"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "console=ttyS0,115200"; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 449acf0d8272..17ea0abcdbd7 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -118,6 +118,7 @@ block_size = <0xfff>; dma-masters = <2>; data-width = <8 8>; + multi-block = <1 1 1 1 1 1 1 1>; }; dma@eb000000 { @@ -134,6 +135,7 @@ chan_priority = <1>; block_size = <0xfff>; data-width = <8 8>; + multi-block = <1 1 1 1 1 1 1 1>; }; fsmc: flash@b0000000 { diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 13029c03d7c6..34c119a66f14 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -101,6 +101,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +113,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = ; }; }; @@ -126,6 +128,7 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; clk_s_c0: clockgen-c@09103000 { @@ -139,6 +142,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +198,12 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = , + , + , + , + , + ; }; }; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 8f79b4147bba..c8b2944e304a 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -916,7 +916,7 @@ }; sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_0>; @@ -926,17 +926,13 @@ reg = <0x8d80000 0x158>; interrupts = ; dmas = <&fdma0 2 0 1>; - dai-name = "Uni Player #0 (HDMI)"; dma-names = "tx"; - st,uniperiph-id = <0>; - st,version = <5>; - st,mode = "HDMI"; status = "disabled"; }; sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-pcm-out"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_1>; @@ -946,17 +942,13 @@ reg = <0x8d81000 0x158>; interrupts = ; dmas = <&fdma0 3 0 1>; - dai-name = "Uni Player #1 (PIO)"; dma-names = "tx"; - st,uniperiph-id = <1>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-dac"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_PCM_2>; @@ -966,17 +958,13 @@ reg = <0x8d82000 0x158>; interrupts = ; dmas = <&fdma0 4 0 1>; - dai-name = "Uni Player #1 (DAC)"; dma-names = "tx"; - st,uniperiph-id = <2>; - st,version = <5>; - st,mode = "PCM"; status = "disabled"; }; sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,sti-uni-player"; + compatible = "st,stih407-uni-player-spdif"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; @@ -987,38 +975,30 @@ interrupts = ; dmas = <&fdma0 7 0 1>; dma-names = "tx"; - dai-name = "Uni Player #1 (PIO)"; - st,uniperiph-id = <3>; - st,version = <5>; - st,mode = "SPDIF"; status = "disabled"; }; sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-pcm_in"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d83000 0x158>; interrupts = ; dmas = <&fdma0 5 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #0 (PCM IN)"; - st,version = <3>; status = "disabled"; }; sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,sti-uni-reader"; + compatible = "st,stih407-uni-reader-hdmi"; #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d84000 0x158>; interrupts = ; dmas = <&fdma0 6 0 1>; dma-names = "rx"; - dai-name = "Uni Reader #1 (HDMI RX)"; - st,version = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index c325cc059ae4..daab16b5ae64 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -1157,7 +1157,7 @@ reg = <0x0923f080 0x4>; reg-names = "irqmux"; interrupts = ; - interrupts-names = "irqmux"; + interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; pio40: gpio@09230000 { diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 291ffacbd2e0..fa149837df14 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -102,7 +102,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 7fb507fcba7e..06b0696cb6b8 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -165,6 +165,9 @@ status = "okay"; }; + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { /* HDMI V1.3a supports Standard mode only */ @@ -174,9 +177,22 @@ status = "okay"; }; - sti-display-subsystem { - sti_hdmi: sti-hdmi@8d04000 { - status = "okay"; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + + simple-audio-card,dai-link@0 { + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; }; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 8598effd6c01..07c8ef9d77f6 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -208,7 +208,8 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; - clock-critical = , + clock-critical = , + , , , , diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index a3ef7341c051..281a12424cf6 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -193,7 +193,7 @@ <&clk_s_d2_quadfs 0>; }; - sti-hdmi@8d04000 { + sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts deleted file mode 100644 index bdfbd3765db2..000000000000 --- a/arch/arm/boot/dts/stih415-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH415 B2000 Board"; - compatible = "st,stih415-b2000", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts deleted file mode 100644 index 71903a87bd31..000000000000 --- a/arch/arm/boot/dts/stih415-b2020.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH415 B2020 Board"; - compatible = "st,stih415-b2020", "st,stih415"; -}; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi deleted file mode 100644 index 3ee34514bc4b..000000000000 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator input to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG1 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - ""; /* clk-s-stac-sys */ - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE41 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-apb-pm", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-disp", - ""; /* Unused */ - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-icn-dmu-0", - "clk-m-icn-dmu-1", - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-eram", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-fdma-12", - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-lmi", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-icn-gpu", - "clk-m-icn-vdp-0"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-icn-vdp-1", - "clk-m-icn-vdp-2", - "clk-m-icn-vdp-3", - "clk-m-prv-t1-bus", - "clk-m-icn-vdp-4", - "clk-m-icn-reg-10", - "", /* Unused */ - ""; /* clk-m-icn-st231 */ - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp-0", - "clk-m-icn-bdisp-1"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "", /* clk-m-icn-hqvdp0 */ - "", /* clk-m-icn-hqvdp1 */ - "clk-m-icn-compo", - "", /* clk-m-icn-vdpaux */ - "clk-m-icn-ts", - "clk-m-icn-reg-lp-10", - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = ""; /* Unused */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde00d8 { - reg = <0xfdde00d8 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde00d8 { - #clock-cells = <0>; - compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde00d8 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi deleted file mode 100644 index bd028ce98b61..000000000000 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - gpio6 = &pio6; - gpio7 = &pio7; - gpio8 = &pio8; - gpio9 = &pio9; - gpio10 = &pio10; - gpio11 = &pio11; - gpio12 = &pio12; - gpio13 = &pio13; - gpio14 = &pio14; - gpio15 = &pio15; - gpio16 = &pio16; - gpio17 = &pio17; - gpio18 = &pio18; - gpio19 = &pio100; - gpio20 = &pio101; - gpio21 = &pio102; - gpio22 = &pio103; - gpio23 = &pio104; - gpio24 = &pio105; - gpio25 = &pio106; - gpio26 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - sbc_serial1 { - pinctrl_sbc_serial1:sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; - }; - }; - - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x8000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x8000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0{ - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; - - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - - - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - }; - - pin-controller-left { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-left-pinctrl"; - st,syscfg = <&syscfg_left>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-right { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-right-pinctrl"; - st,syscfg = <&syscfg_right>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi deleted file mode 100644 index 12427e651e5e..000000000000 --- a/arch/arm/boot/dts/stih415.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih415-clock.dtsi" -#include "stih415-pinctrl.dtsi" -#include -#include -/ { - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <1 1 1>; - cache-unified; - cache-level = <2>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - syscfg_sbc: sbc-syscfg@fe600000{ - compatible = "st,stih415-sbc-syscfg", "syscon"; - reg = <0xfe600000 0xb4>; - }; - - syscfg_front: front-syscfg@fee10000{ - compatible = "st,stih415-front-syscfg", "syscon"; - reg = <0xfee10000 0x194>; - }; - - syscfg_rear: rear-syscfg@fe830000{ - compatible = "st,stih415-rear-syscfg", "syscon"; - reg = <0xfe830000 0x190>; - }; - - /* MPE syscfgs */ - syscfg_left: left-syscfg@fd690000{ - compatible = "st,stih415-left-syscfg", "syscon"; - reg = <0xfd690000 0x78>; - }; - - syscfg_right: right-syscfg@fd320000{ - compatible = "st,stih415-right-syscfg", "syscon"; - reg = <0xfd320000 0x180>; - }; - - syscfg_system: system-syscfg@fdde0000 { - compatible = "st,stih415-system-syscfg", "syscon"; - reg = <0xfdde0000 0x15c>; - }; - - syscfg_lpm: lpm-syscfg@fe4b5100{ - compatible = "st,stih415-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x08>; - }; - - serial2: serial@fed32000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - }; - - /* SBC comms block ASCs in SASG1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 147 0>, <0 148 0>, <0 149 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - resets = <&softreset STIH415_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_rear 0x148>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 150 0>, <0 151 0>, <0 152 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_sbc 0x74>; - - resets = <&softreset STIH415_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - clocks = <&clk_sysin>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH415_IRB_SOFTRESET>; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, - <&softreset STIH415_KEYSCAN_SOFTRESET>; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts deleted file mode 100644 index 488e80a5d69d..000000000000 --- a/arch/arm/boot/dts/stih416-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH416 B2000"; - compatible = "st,stih416-b2000", "st,stih416"; -}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts deleted file mode 100644 index 200a81844765..000000000000 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts deleted file mode 100644 index de320cd067de..000000000000 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -#include -/ { - model = "STiH416 B2020 REV-E"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&pio0 7>; - }; - - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - status = "okay"; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi deleted file mode 100644 index 5b4fb838cddb..000000000000 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics R&D Limited - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG2 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc-0", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - "clk-s-stac-sys", - "clk-s-card-mmc-1"; - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE42 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-fdma-12", - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-lmi", - "clk-m-vid-dmu-0"; - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-vid-dmu-1", - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-tx-icn-dmu-0", - "clk-m-tx-icn-dmu-1", - "clk-m-tx-icn-ts", - "clk-m-icn-vdp-0", - "clk-m-icn-vdp-1"; - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-vp8", - "", /* Unused */ - "clk-m-icn-reg-11", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-alt", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-rx-icn-dmu-0", - "clk-m-rx-icn-dmu-1"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-rx-icn-ts", - "clk-m-rx-icn-vdp-0", - "", /* Unused */ - "clk-m-prv-t1-bus", - "clk-m-icn-reg-12", - "clk-m-icn-reg-10", - "", /* Unused */ - "clk-m-icn-st231"; - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "clk-m-icn-reg-13", - "clk-m-tx-icn-gpu", - "clk-m-rx-icn-gpu", - "", /* Unused */ - "", /* Unused */ - "", /* clk-m-apb-pm-12 */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* clk-m-gpu-alt */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp", - "clk-m-icn-compo"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-icn-vdp-2", - "", /* Unused */ - "clk-m-icn-reg-14", - "clk-m-mdtp", - "clk-m-jpegdec", - "", /* Unused */ - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - ""; /* clk-m-apb-pm-11 */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde08b0 { - reg = <0xfdde08b0 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde08ac { - #clock-cells = <0>; - compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde08ac 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Frequency synthesizers on the SASG2 - */ - clockgen_b0: clockgen-b0@fee108b4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee108b4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-usb48", - "clk-s-dss", - "clk-s-stfe-frc-2", - "clk-s-thsens-scard"; - }; - - clockgen_b1: clockgen-b1@fe8308c4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfe8308c4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-pcm-0", - "clk-s-pcm-1", - "clk-s-pcm-2", - "clk-s-pcm-3"; - }; - - clockgen_c: clockgen-c@fe8307d0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs432", "st,quadfs"; - reg = <0xfe8307d0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-c-fs0-ch0", - "clk-s-c-vcc-sd", - "clk-s-c-fs0-ch2"; - }; - - clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; - reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ - - clocks = <&clk_sysin>, - <&clockgen_c 0>; - }; - - /* - * Add a dummy clock for the HDMI PHY for the VCC input mux - */ - clk_s_tmds_fromphy: clk-s-tmds-fromphy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_c_vcc: clockgen-c-vcc@fe8308ac { - #clock-cells = <1>; - compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; - reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ - - clocks = <&clk_s_vcc_hd>, - <&clockgen_c 1>, - <&clk_s_tmds_fromphy>, - <&clockgen_c 2>; - - clock-output-names = "clk-s-pix-hdmi", - "clk-s-pix-dvo", - "clk-s-out-dvo", - "clk-s-pix-hd", - "clk-s-hddac", - "clk-s-denc", - "clk-s-sddac", - "clk-s-pix-main", - "clk-s-pix-aux", - "clk-s-stfe-frc-0", - "clk-s-ref-mcru", - "clk-s-slave-mcru", - "clk-s-tmds-hdmi", - "clk-s-hdmi-reject-pll", - "clk-s-thsens"; - }; - - clockgen_d: clockgen-d@fee107e0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee107e0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-ccsc", - "clk-s-stfe-frc-1", - "clk-s-tsout-1", - "clk-s-mchi"; - }; - - /* - * Frequency synthesizers on the MPE42 - */ - clockgen_e: clockgen-e@fd3208bc { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-E", "st,quadfs"; - reg = <0xfd3208bc 0xb0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-pix-mdtp-0", - "clk-m-pix-mdtp-1", - "clk-m-pix-mdtp-2", - "clk-m-mpelpc"; - }; - - clockgen_f: clockgen-f@fd320878 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-F", "st,quadfs"; - reg = <0xfd320878 0xf0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-main-vidfs", - "clk-m-hva-fs", - "clk-m-fvdp-vcpu", - "clk-m-fvdp-proc-fs"; - }; - - clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; - reg = <0xfd320910 0x4>; /* SYSCFG8580 */ - - clocks = <&clk_m_a1_div2 0>, - <&clockgen_f 3>; - }; - - clk_m_hva: clk-m-hva@fd690868 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; - reg = <0xfd690868 0x4>; /* SYSCFG9538 */ - - clocks = <&clockgen_f 1>, - <&clk_m_a1_div0 3>; - }; - - clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 7>, - <&clockgen_f 0>; - }; - - clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 8>, - <&clockgen_f 1>; - }; - - /* - * Add a dummy clock for the HDMIRx external signal clock - */ - clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_f_vcc: clockgen-f-vcc@fd32086c { - #clock-cells = <1>; - compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; - reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ - - clocks = <&clk_m_f_vcc_hd>, - <&clk_m_f_vcc_sd>, - <&clockgen_f 0>, - <&clk_m_pix_hdmirx_sas>; - - clock-output-names = "clk-m-pix-main-pipe", - "clk-m-pix-aux-pipe", - "clk-m-pix-main-cru", - "clk-m-pix-aux-cru", - "clk-m-xfer-be-compo", - "clk-m-xfer-pip-compo", - "clk-m-xfer-aux-compo", - "clk-m-vsens", - "clk-m-pix-hdmirx-0", - "clk-m-pix-hdmirx-1"; - }; - - /* - * DDR PLL - */ - clockgen-ddr@0xfdde07d8 { - reg = <0xfdde07d8 0x110>; - - clockgen_ddr_pll: clockgen-ddr-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-ddr0", - "clockgen-ddr1"; - }; - }; - - /* - * GPU PLL - */ - clockgen-gpu@fd68ff00 { - reg = <0xfd68ff00 0x910>; - - clockgen_gpu_pll: clockgen-gpu-pll { - #clock-cells = <1>; - compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-gpu-pll"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi deleted file mode 100644 index 9c97f7e651a0..000000000000 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ /dev/null @@ -1,692 +0,0 @@ - -/* - * Copyright (C) 2013 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio40; - gpio6 = &pio5; - gpio7 = &pio6; - gpio8 = &pio7; - gpio9 = &pio8; - gpio10 = &pio9; - gpio11 = &pio10; - gpio12 = &pio11; - gpio13 = &pio12; - gpio14 = &pio30; - gpio15 = &pio31; - gpio16 = &pio13; - gpio17 = &pio14; - gpio18 = &pio15; - gpio19 = &pio16; - gpio20 = &pio17; - gpio21 = &pio18; - gpio22 = &pio100; - gpio23 = &pio101; - gpio24 = &pio102; - gpio25 = &pio103; - gpio26 = &pio104; - gpio27 = &pio105; - gpio28 = &pio106; - gpio29 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x6000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - pio40: gpio@fe615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO40"; - st,retime-pin-mask = <0x7f>; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb3: usb3 { - st,pins { - oc-detect = <&pio40 0 ALT1 IN>; - pwr-enable = <&pio40 1 ALT1 OUT>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-out = <&pio4 4 ALT1 OUT>; - pwm-capturein = <&pio4 3 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x10000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - pio30: gpio@fee08000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@fee09000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO31"; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-out = <&pio9 7 ALT2 OUT>; - pwm-capturein = <&pio9 6 ALT2 IN>; - }; - }; - }; - - serial2-oe { - pinctrl_serial2_oe: serial2-1 { - st,pins { - output-enable = <&pio11 3 ALT2 OUT>; - }; - }; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb0: usb0 { - st,pins { - oc-detect = <&pio9 4 ALT1 IN>; - pwr-enable = <&pio9 5 ALT1 OUT>; - }; - }; - }; - - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio12 2 ALT1 OUT>; - spi-fsm-cs = <&pio12 3 ALT1 OUT>; - spi-fsm-mosi = <&pio12 4 ALT1 OUT>; - spi-fsm-miso = <&pio12 5 ALT1 IN>; - spi-fsm-hol = <&pio12 6 ALT1 OUT>; - spi-fsm-wp = <&pio12 7 ALT1 OUT>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x6000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - st,retime-pin-mask = <0xf>; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0 { - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - }; - }; - pinctrl_rgmii0: rgmii0 { - st,pins { - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&pio15 4 ALT2 OUT BYPASS 0>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - mmc1 { - pinctrl_mmc1: mmc1 { - st,pins { - mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; - data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; - data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; - data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; - cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; - data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; - data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; - data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; - data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; - pwr = <&pio16 2 ALT3 OUT>; - nreset = <&pio13 6 ALT3 OUT>; - }; - }; - }; - - usb { - pinctrl_usb1: usb1 { - st,pins { - oc-detect = <&pio18 0 ALT1 IN>; - pwr-enable = <&pio18 1 ALT1 OUT>; - }; - }; - pinctrl_usb2: usb2 { - st,pins { - oc-detect = <&pio18 2 ALT1 IN>; - pwr-enable = <&pio18 3 ALT1 OUT>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan1_default: pwm0-1-default { - st,pins { - pwm-out = <&pio13 2 ALT2 OUT>; - pwm-capturein = <&pio13 1 ALT2 IN>; - }; - }; - pinctrl_pwm0_chan2_default: pwm0-2-default { - st,pins { - pwm-out = <&pio15 2 ALT4 OUT>; - }; - }; - pinctrl_pwm0_chan3_default: pwm0-3-default { - st,pins { - pwm-out = <&pio17 4 ALT1 OUT>; - }; - }; - }; - - }; - - pin-controller-fvdp-fe { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-fe-pinctrl"; - st,syscfg = <&syscfg_fvdp_fe>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-fvdp-lite { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-lite-pinctrl"; - st,syscfg = <&syscfg_fvdp_lite>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - st,retime-pin-mask = <0xf>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi deleted file mode 100644 index fe1f9cf770e4..000000000000 --- a/arch/arm/boot/dts/stih416.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2012 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih416-clock.dtsi" -#include "stih416-pinctrl.dtsi" - -#include -#include -#include -#include -/ { - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih416-restart"; - st,syscfg = <&syscfg_sbc>; - status = "okay"; - }; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih416-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih416-softreset"; - }; - - syscfg_sbc:sbc-syscfg@fe600000{ - compatible = "st,stih416-sbc-syscfg", "syscon"; - reg = <0xfe600000 0x1000>; - }; - - syscfg_front:front-syscfg@fee10000{ - compatible = "st,stih416-front-syscfg", "syscon"; - reg = <0xfee10000 0x1000>; - }; - - syscfg_rear:rear-syscfg@fe830000{ - compatible = "st,stih416-rear-syscfg", "syscon"; - reg = <0xfe830000 0x1000>; - }; - - /* MPE */ - syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ - compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; - reg = <0xfddf0000 0x1000>; - }; - - syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ - compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; - reg = <0xfd6a0000 0x1000>; - }; - - syscfg_cpu:cpu-syscfg@fdde0000{ - compatible = "st,stih416-cpu-syscfg", "syscon"; - reg = <0xfdde0000 0x1000>; - }; - - syscfg_compo:compo-syscfg@fd320000{ - compatible = "st,stih416-compo-syscfg", "syscon"; - reg = <0xfd320000 0x1000>; - }; - - syscfg_transport:transport-syscfg@fd690000{ - compatible = "st,stih416-transport-syscfg", "syscon"; - reg = <0xfd690000 0x1000>; - }; - - syscfg_lpm:lpm-syscfg@fe4b5100{ - compatible = "st,stih416-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x8>; - }; - - irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - serial2: serial@fed32000{ - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; - }; - - /* SBC_UART1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 133 0>, <0 134 0>, <0 135 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_rear 0x8bc>; - resets = <&softreset STIH416_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 136 0>, <0 137 0>, <0 138 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_sbc 0x7f0>; - - resets = <&softreset STIH416_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH416_IRB_SOFTRESET>; - }; - - /* FSM */ - spifsm: spifsm@fe902000 { - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - pinctrl-0 = <&pinctrl_fsm>; - - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - - status = "disabled"; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, - <&softreset STIH416_KEYSCAN_SOFTRESET>; - }; - - temp0 { - compatible = "st,stih416-sas-thermal"; - clock-names = "thermal"; - clocks = <&clockgen_c_vcc 14>; - - status = "okay"; - }; - - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clocks = <&clockgen_e 3>; - clock-names = "thermal"; - interrupts = ; - - status = "okay"; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - - mmc1: sdhci@fe81f000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81f000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 8>; - }; - - miphy365x_phy: phy@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - #phy-cells = <1>; - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - }; - - phy_port1: port@fe38a000 { - #phy-cells = <1>; - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>; - reg-names = "sata", "pcie"; - }; - }; - - sata0: sata@fe380000 { - compatible = "st,sti-ahci"; - reg = <0xfe380000 0x1000>; - interrupts = ; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clock-names = "ahci_clk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - - status = "disabled"; - }; - - usb2_phy: phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; - }; - - ehci0: usb@fe1ffe00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe1ffe00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - status = "okay"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci1: usb@fe203c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe203c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci2: usb@fe303e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe303e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci2: usb@fe303c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe303c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci3: usb@fe343e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe343e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci3: usb@fe343c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe343c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfed10000 0x68>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default - &pinctrl_pwm0_chan1_default - &pinctrl_pwm0_chan2_default - &pinctrl_pwm0_chan3_default>; - - clock-names = "pwm", "capture"; - clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; - - st,pwm-num-chan = <4>; - st,capture-num-chan = <2>; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfe510000 0x68>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - /* - * Shared with SBC_OBS_NOTRST. Don't - * enable unless you really know what - * you're doing. - * - * &pinctrl_pwm1_chan1_default - */ - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <3>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi deleted file mode 100644 index 9bfa0674b452..000000000000 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include -#include - -/ { - - memory{ - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &serial2; - }; - - aliases { - ttyAS0 = &serial2; - ethernet0 = ðernet0; - ethernet1 = ðernet1; - }; - - soc { - serial2: serial@fed32000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - fp_led { - label = "Front Panel LED"; - gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - ethernet0: dwmac@fe810000 { - status = "okay"; - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_mii0>; - - snps,reset-gpio = <&pio106 2>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - ethernet1: dwmac@fef08000 { - status = "disabled"; - phy-mode = "mii"; - st,tx-retime-src = "txclk"; - - snps,reset-gpio = <&pio4 7>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - keyscan: keyscan@fe4b0000 { - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce-us = <5000>; - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi deleted file mode 100644 index 322e0e95176c..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x-b2020x.dtsi" -#include -/ { - memory{ - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial1; - }; - - aliases { - ttyAS0 = &sbc_serial1; - ethernet1 = ðernet1; - }; - soc { - sbc_serial1: serial@fe531000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - i2c@fed40000 { - status = "okay"; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - i2c@fe540000 { - status = "okay"; - }; - - i2c@fe541000 { - status = "okay"; - }; - - ethernet1: dwmac@fef08000 { - status = "okay"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&pio3 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-0 = <&pinctrl_rgmii1>; - }; - - mmc0: sdhci@fe81e000 { - bus-width = <8>; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi deleted file mode 100644 index f797a0607382..000000000000 --- a/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - soc { - mmc0: sdhci@fe81e000 { - status = "okay"; - }; - - spifsm: spifsm@fe902000 { - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - - partition@0 { - label = "SerialFlash1"; - reg = <0x00000000 0x00500000>; - }; - - partition@500000 { - label = "SerialFlash2"; - reg = <0x00500000 0x00b00000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi deleted file mode 100644 index 5cb0e63376b5..000000000000 --- a/arch/arm/boot/dts/stih41x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - intc: interrupt-controller@fffe1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffe1000 0x1000>, - <0xfffe0100 0x100>; - }; - - scu@fffe0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffe0000 0x1000>; - }; - - timer@fffe0200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffe0200 0x100>; - interrupts = <1 11 0x04>; - clocks = <&arm_periph_clk>; - }; -}; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index ed2b7a99ecff..4b8f62f89664 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -135,6 +135,10 @@ }; }; + sti_uni_player0: sti-uni-player@8d80000 { + status = "okay"; + }; + sti_uni_player2: sti-uni-player@8d82000 { status = "okay"; }; @@ -151,13 +155,26 @@ sound { compatible = "simple-audio-card"; - simple-audio-card,name = "sti audio card"; + simple-audio-card,name = "STI-B2120"; status = "okay"; simple-audio-card,dai-link@0 { + /* HDMI */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; + }; + + codec { + sound-dai = <&sti_hdmi>; + }; + }; + simple-audio-card,dai-link@1 { /* DAC */ format = "i2s"; mclk-fs = <256>; + frame-inversion = <1>; cpu { sound-dai = <&sti_uni_player2>; }; @@ -166,7 +183,7 @@ sound-dai = <&sti_sasg_codec 1>; }; }; - simple-audio-card,dai-link@1 { + simple-audio-card,dai-link@2 { /* SPDIF */ format = "left_j"; mclk-fs = <128>; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6bfc5959dac3..5436e880e28f 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -47,6 +47,7 @@ /dts-v1/; #include "stm32f429.dtsi" +#include / { model = "STMicroelectronics STM32429i-EVAL board"; @@ -65,6 +66,10 @@ serial0 = &usart1; }; + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; + leds { compatible = "gpio-leds"; green { @@ -82,6 +87,23 @@ }; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioa 0 0>; + }; + button@1 { + label = "Tamper"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; + usbotg_hs_phy: usbphy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -94,11 +116,12 @@ clock-frequency = <25000000>; }; -ðernet0 { +&mac { status = "okay"; - pinctrl-0 = <ðernet0_mii>; + pinctrl-0 = <ðernet_mii>; pinctrl-names = "default"; - phy-mode = "mii-id"; + phy-mode = "mii"; + phy-handle = <&phy1>; mdio0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts new file mode 100644 index 000000000000..aa03fac1ec55 --- /dev/null +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include + +/ { + model = "STMicroelectronics STM32746g-EVAL board"; + compatible = "st,stm32746g-eval", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xc0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiof 10 1>; + linux,default-trigger = "heartbeat"; + }; + red { + gpios = <&gpiob 7 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 01408073dd53..7d0415e80668 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -47,6 +47,7 @@ /dts-v1/; #include "stm32f429.dtsi" +#include / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -75,6 +76,18 @@ linux,default-trigger = "heartbeat"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 0>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 336ee4fb587d..e4dae0eda3cd 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -56,11 +56,21 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; }; soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - timer2: timer@40000000 { compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; @@ -122,6 +132,9 @@ interrupts = <39>; clocks = <&rcc 0 146>; status = "disabled"; + dmas = <&dma1 1 4 0x400 0x0>, + <&dma1 3 4 0x400 0x0>; + dma-names = "rx", "tx"; }; usart4: serial@40004c00 { @@ -162,6 +175,9 @@ interrupts = <37>; clocks = <&rcc 0 164>; status = "disabled"; + dmas = <&dma2 2 4 0x400 0x0>, + <&dma2 7 4 0x400 0x0>; + dma-names = "rx", "tx"; }; usart6: serial@40011400 { @@ -185,11 +201,18 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + pwrcfg: power-config@40007000 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl"; ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; pins-are-numbered; gpioa: gpio@40020000 { @@ -313,7 +336,7 @@ }; }; - ethernet0_mii: mii@0 { + ethernet_mii: mii@0 { pins { pinmux = , , @@ -340,6 +363,7 @@ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>; + st,syscfg = <&pwrcfg>; }; dma1: dma-controller@40026000 { @@ -373,24 +397,22 @@ st,mem2mem; }; - ethernet0: dwmac@40028000 { + mac: ethernet@40028000 { compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; reg = <0x40028000 0x8000>; reg-names = "stmmaceth"; - interrupts = <61>, <62>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", "tx-clk", "rx-clk"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; st,syscon = <&syscfg 0x4>; snps,pbl = <8>; snps,mixed-burst; - dma-ranges; status = "disabled"; }; usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; - dma-ranges; reg = <0x40040000 0x40000>; interrupts = <77>; clocks = <&rcc 0 29>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index e911af836471..8877c00ce8e8 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -64,6 +64,14 @@ aliases { serial0 = &usart3; }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; +}; + +&rcc { + compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; }; &clk_hse { diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi new file mode 100644 index 000000000000..f321ffe87144 --- /dev/null +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -0,0 +1,304 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include "armv7-m.dtsi" +#include + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&rcc 0 128>; + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&rcc 0 129>; + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&rcc 0 130>; + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 131>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&rcc 0 132>; + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&rcc 0 133>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 0 145>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 0 146>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 0 147>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32f7-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 0 148>; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 0 158>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 0 159>; + status = "disabled"; + }; + + usart1: serial@40011000 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + status = "disabled"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 0 165>; + status = "disabled"; + }; + + syscfg: system-config@40013800 { + compatible = "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f746-pinctrl"; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 256>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 257>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 258>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 259>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 260>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 261>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 262>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 263>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 264>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 265>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 266>; + st,bank-name = "GPIOK"; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; + }; + + rcc: rcc@40023800 { + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; + }; +}; + +&systick { + clocks = <&rcc 1 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 7e7dfc2b43db..b14a4281058d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -967,7 +967,8 @@ compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index aef91476f9ae..0684d7930d65 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -250,8 +250,8 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pins_b>, + <&spi2_cs0_pins_b>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index c41a2ba34dde..7aa8c7aa0153 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -243,14 +243,14 @@ allwinner,pull = ; }; - spi2_pins_a: spi2@0 { + spi2_pins_b: spi2@1 { allwinner,pins = "PB12", "PB13", "PB14"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; - spi2_cs0_pins_a: spi2_cs0@0 { + spi2_cs0_pins_b: spi2_cs0@1 { allwinner,pins = "PB11"; allwinner,function = "spi2"; allwinner,drive = ; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index b3c234c65ea1..bb7210e0e4a9 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -72,6 +72,47 @@ default-state = "on"; }; }; + + bridge { + compatible = "dumb-vga-dac"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; +}; + +&be0 { + status = "okay"; }; &ehci0 { @@ -211,6 +252,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index a8b0bcc04514..3d7ff10a48e9 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -83,22 +83,6 @@ allwinner,pins = "PG3"; }; -&i2c1 { - icn8318: touchscreen@40 { - compatible = "chipone,icn8318"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_wake_pin_p66>; - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; @@ -121,20 +105,26 @@ allwinner,drive = ; allwinner,pull = ; }; - - ts_wake_pin_p66: ts_wake_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; ®_usb0_vbus { gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ }; +&touchscreen { + compatible = "chipone,icn8318"; + reg = <0x40>; + /* The P66 uses a different EINT then the reference design */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + /* The icn8318 binding expects wake-gpios instead of power-gpios */ + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + status = "okay"; +}; + &uart1 { /* The P66 uses the uart pins as gpios */ status = "disabled"; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts new file mode 100644 index 000000000000..92a2dc6250a5 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -0,0 +1,266 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "NextThing C.H.I.P. Pro"; + compatible = "nextthing,chip-pro", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "chip-pro:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_pin_chip_pro>; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_pin_chip_pro: usb0-id-pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>; + status = "disabled"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +/* + * Both LDO3 and LDO4 are used in parallel to power up the + * WiFi/BT chip. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>; + status = "okay"; +}; + +&usb_otg { + /* + * The CHIP Pro doesn't have a controllable VBUS, nor does it + * have any 5v rail on the board itself. + * + * If one wants to use it as a true OTG port, it should be + * done in the baseboard, and its DT / overlay will add it. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pin_chip_pro>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 714381fd64d7..030605aa8065 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -75,6 +75,39 @@ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; }; + + sound-analog { + compatible = "simple-audio-card"; + simple-audio-card,name = "gr8-evb-wm8978"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + }; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &be0 { diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index ca54e03ef366..ea86d4d58db6 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -792,7 +792,7 @@ }; i2s0_mclk_pins_a: i2s0-mclk@0 { - allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,pins = "PB5"; allwinner,function = "i2s0"; allwinner,drive = ; allwinner,pull = ; @@ -854,6 +854,13 @@ allwinner,pull = ; }; + pwm1_pins: pwm1 { + allwinner,pins = "PG13"; + allwinner,function = "pwm1"; + allwinner,drive = ; + allwinner,pull = ; + }; + spdif_tx_pins_a: spdif@0 { allwinner,pins = "PB10"; allwinner,function = "spdif"; @@ -874,6 +881,34 @@ allwinner,drive = ; allwinner,pull = ; }; + + uart2_pins_a: uart2@1 { + allwinner,pins = "PD2", "PD3"; + allwinner,function = "uart2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart2_cts_rts_pins_a: uart2-cts-rts@0 { + allwinner,pins = "PD4", "PD5"; + allwinner,function = "uart2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart3_pins_a: uart3@1 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart3_cts_rts_pins_a: uart3-cts-rts@0 { + allwinner,pins = "PG11", "PG12"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; }; pwm: pwm@01c20e00 { @@ -978,6 +1013,16 @@ status = "disabled"; }; + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + i2c0: i2c@01c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index b68a12374b35..c6da5ad37152 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -56,9 +56,11 @@ aliases { i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart1; serial1 = &uart3; + spi0 = &spi2; }; chosen { @@ -74,6 +76,20 @@ default-state = "on"; }; }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&chip_wifi_reg_on_pin>; + reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ + }; + + onewire { + compatible = "w1-gpio"; + gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ + pinctrl-names = "default"; + pinctrl-0 = <&chip_w1_pin>; + }; }; &be0 { @@ -112,6 +128,12 @@ #include "axp209.dtsi" +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -131,10 +153,15 @@ }; }; +&mmc0_pins_a { + allwinner,pull = ; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -156,12 +183,26 @@ allwinner,pull = ; }; + chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 { + allwinner,pins = "PC19"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + chip_id_det_pin: chip_id_det_pin@0 { allwinner,pins = "PG2"; allwinner,function = "gpio_in"; allwinner,drive = ; allwinner,pull = ; }; + + chip_w1_pin: chip_w1_pin@0 { + allwinner,pins = "PD2"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; }; ®_dcdc2 { @@ -189,6 +230,28 @@ regulator-always-on; }; +/* + * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT + * Chip. + * + * If those are not enabled, the SDIO part will not enumerate, and + * since there's no way currently to pass DT infos to an SDIO device, + * we cannot really do better than this ugly hack for now. + */ +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + regulator-always-on; +}; + +®_ldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + regulator-always-on; +}; + ®_ldo5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -202,6 +265,12 @@ status = "okay"; }; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "disabled"; +}; + &tcon0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 20cc940f5f91..82f87cdcd164 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -41,6 +41,7 @@ */ #include "sunxi-reference-design-tablet.dtsi" +#include #include / { @@ -84,6 +85,23 @@ }; &i2c1 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * All other devices on this bus are also rated for 400KHz. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen { + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -125,6 +143,13 @@ allwinner,pull = ; }; + ts_power_pin: ts_power_pin { + pins = "PB3"; + function = "gpio_out"; + drive-strength = <10>; + bias-disable; + }; + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { allwinner,pins = "PG1"; allwinner,function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index e374f4fc8073..b0fca4ef4dae 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -547,7 +547,8 @@ pio: pinctrl@01c20800 { reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -574,6 +575,16 @@ allwinner,pull = ; }; + lcd_rgb565_pins: lcd_rgb565@0 { + allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -591,6 +602,20 @@ allwinner,pull = ; }; + spi2_pins_a: spi2@0 { + allwinner,pins = "PE1", "PE2", "PE3"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_a: spi2-cs0@0 { + allwinner,pins = "PE0"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart3_pins_a: uart3@0 { allwinner,pins = "PG9", "PG10"; allwinner,function = "uart3"; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 9a74637f677f..735914f6ae44 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -63,12 +63,79 @@ stdout-path = "serial0:115200n8"; }; + vga-connector { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "dumb-vga-dac"; + vdd-supply = <®_vga_3v3>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vga_dac_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vga_dac_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + reg_vga_3v3: vga_3v3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vga-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; }; +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc3>; }; @@ -245,6 +312,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_dac_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index ce1960453a0b..2b26175d55d1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -231,6 +231,11 @@ }; }; + de: display-engine { + compatible = "allwinner,sun6i-a31-display-engine"; + allwinner,pipelines = <&fe0>; + }; + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; @@ -246,6 +251,44 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + resets = <&ccu RST_AHB1_LCD0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -428,19 +471,55 @@ , , ; - clocks = <&ccu CLK_APB1_PIO>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - uart0_pins_a: uart0@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "uart0"; + gmac_pins_gmii_a: gmac_gmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + allwinner,drive = ; + allwinner,pull = ; + }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + allwinner,function = "gmac"; allwinner,drive = ; allwinner,pull = ; }; + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = ; + allwinner,pull = ; + }; + i2c0_pins_a: i2c0@0 { allwinner,pins = "PH14", "PH15"; allwinner,function = "i2c0"; @@ -462,6 +541,19 @@ allwinner,pull = ; }; + lcd0_rgb888_pins: lcd0_rgb888 { + allwinner,pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -506,47 +598,12 @@ allwinner,pull = ; }; - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - allwinner,function = "gmac"; + uart0_pins_a: uart0@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "uart0"; allwinner,drive = ; allwinner,pull = ; }; - - gmac_pins_gmii_a: gmac_gmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; - }; }; timer@01c20c00 { @@ -728,6 +785,19 @@ reset-names = "ahb"; }; + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; @@ -799,6 +869,115 @@ interrupts = ; }; + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, + <&ccu CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, + <&ccu CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE0>; + + assigned-clocks = <&ccu CLK_BE0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@01e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + assigned-clocks = <&ccu CLK_IEP_DRC0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + rtc: rtc@01f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; @@ -886,7 +1065,8 @@ reg = <0x01f02c00 0x400>; interrupts = , ; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 6ead2f5c847a..c35ec112f5a0 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -65,6 +65,14 @@ }; }; +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + &ehci0 { /* USB 2.0 4 port hub IC */ status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/sun6i-a31s.dtsi index c17a32771b98..97e2c51d0aea 100644 --- a/arch/arm/boot/dts/sun6i-a31s.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s.dtsi @@ -48,6 +48,14 @@ #include "sun6i-a31.dtsi" +&de { + compatible = "allwinner,sun6i-a31s-display-engine"; +}; + &pio { compatible = "allwinner,sun6i-a31s-pinctrl"; }; + +&tcon0 { + compatible = "allwinner,sun6i-a31s-tcon"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index ba5bca0fe997..532f1a160560 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -105,6 +105,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; @@ -132,16 +136,14 @@ status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; }; }; +#include "axp209.dtsi" + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; @@ -167,7 +169,7 @@ mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; non-removable; - enable-sdio-wakeup; + wakeup-source; status = "okay"; brcmf: bcrmf@1 { @@ -192,6 +194,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { gmac_power_pin_bpi_m1p: gmac_power_pin@0 { allwinner,pins = "PH23"; @@ -222,8 +228,54 @@ }; }; +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on usb host ports are tied to DC5V and therefore always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 23aacce4d6c7..134e0c1b129d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -88,6 +88,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &codec { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 94cf5a1c7172..f7db067b0de0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1085,7 +1085,8 @@ compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = ; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 300a1bd5a6ec..e4991a78ad73 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -266,7 +266,8 @@ /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -575,7 +576,8 @@ compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index a86cbedda34c..21bb291b9568 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -98,13 +98,6 @@ }; }; -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - &touchscreen { reg = <0x40>; compatible = "silead,gsl1680"; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index fef6abc0a703..71bb9418c5f9 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -213,6 +213,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { status = "okay"; usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts new file mode 100644 index 000000000000..ec63d104b404 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1"; + compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 3d64cafc1e90..8d2cc6e9a03f 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -40,86 +40,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include +#include "sun8i-h3-nanopi.dtsi" / { model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - leds_opc: led-pins { - allwinner,pins = "PA10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led-pins { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi new file mode 100644 index 000000000000..8038aa29a5a7 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2016 James Pettigrew + * Copyright (C) 2016 Milo Kim + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_npi>, <&leds_r_npi>; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + input-name = "k1"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_npi>; + + k1@0 { + label = "k1"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_npi: led_pins@0 { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_pio { + leds_r_npi: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + sw_r_npi: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index f4ba088b225e..6c14a6f72820 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -321,7 +321,8 @@ reg = <0x01c20800 0x400>; interrupts = , ; - clocks = <&ccu CLK_BUS_PIO>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; @@ -381,6 +382,20 @@ allwinner,pull = ; }; + spi0_pins: spi0 { + allwinner,pins = "PC0", "PC1", "PC2", "PC3"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi1_pins: spi1 { + allwinner,pins = "PA15", "PA16", "PA14", "PA13"; + allwinner,function = "spi1"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; allwinner,function = "uart0"; @@ -425,6 +440,38 @@ clocks = <&osc24M>; }; + spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c69000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c69000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + wdt0: watchdog@01c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; @@ -568,7 +615,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 08cd00143635..69bc0cd26ca7 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -209,6 +209,13 @@ status = "okay"; }; +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 439847acd41e..67b02fe7f11c 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -76,6 +76,14 @@ gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &mmc0 { @@ -88,6 +96,21 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_cubieboard4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + allwinner,pull = ; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -128,6 +151,15 @@ status = "okay"; }; +&r_pio { + wifi_en_pin_cubieboard4: wifi_en_pin@0 { + allwinner,pins = "PL2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + &r_rsb { status = "okay"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index ceb6ef15d669..7e036b2be762 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -105,6 +105,14 @@ enable-active-high; gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { @@ -130,6 +138,21 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>, <&wifi_en_pin_optimus>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_cldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc1_pins { + allwinner,pull = ; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -199,6 +222,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + wifi_en_pin_optimus: wifi_en_pin@0 { + allwinner,pins = "PL2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &r_rsb { diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 3c5214cbe4e6..979ad1aacfb1 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -678,7 +678,8 @@ , , ; - clocks = <&apb0_gates 5>; + clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -700,6 +701,14 @@ allwinner,pull = ; }; + mmc1_pins: mmc1 { + allwinner,pins = "PG0", "PG1" ,"PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc2_8bit_pins: mmc2_8bit { allwinner,pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", @@ -894,7 +903,8 @@ reg = <0x08002c00 0x400>; interrupts = , ; - clocks = <&apbs_gates 0>; + clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index e7a73db17613..0819721dda59 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1595,7 +1595,7 @@ clock-frequency = <400000>; /* SGTL5000 audio codec */ - sgtl5000: codec@0a { + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_3v3>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 271505e0715f..eabfa655a3cd 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -42,6 +42,12 @@ }; }; + gpu@0,57000000 { + status = "okay"; + + vdd-supply = <&vdd_gpu>; + }; + serial@70006000 { /* Debug connector on the bottom of the board near SD card. */ status = "okay"; @@ -214,7 +220,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2207c08e3fa3..e8807503f87c 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -376,6 +376,19 @@ status = "disabled"; }; + gmi@70009000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xd0000000 0xfffffff>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 192b95177aac..f6c7c3e958ac 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -48,6 +48,24 @@ pinctrl-0 = <&state_default>; state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis BKL1_ON */ pv2 { nvidia,pins = "pv2"; @@ -429,6 +447,15 @@ status = "okay"; clock-frequency = <100000>; + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <&sys_3v3_reg>; + VDDIO-supply = <&sys_3v3_reg>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -660,6 +687,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + /* eMMC */ sdhci@78000600 { status = "okay"; @@ -733,4 +766,20 @@ regulator-always-on; }; }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index a265534cd314..5360d638eedc 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -29,6 +29,24 @@ pinctrl-0 = <&state_default>; state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Colibri BL_ON */ pv2 { nvidia,pins = "pv2"; @@ -207,6 +225,15 @@ status = "okay"; clock-frequency = <100000>; + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <&sys_3v3_reg>; + VDDIO-supply = <&sys_3v3_reg>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -396,6 +423,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + /* eMMC */ sdhci@78000600 { status = "okay"; @@ -471,4 +504,20 @@ regulator-always-on; }; }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Colibri T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5030065cbdfe..bbb1c002e7f1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -439,6 +439,19 @@ status = "disabled"; }; + gmi@70009000 { + compatible = "nvidia,tegra30-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x48000000 0x7ffffff>; + clocks = <&tegra_car TEGRA30_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi index a63272422d76..02de56b55823 100644 --- a/arch/arm/boot/dts/tps65217.dtsi +++ b/arch/arm/boot/dts/tps65217.dtsi @@ -13,6 +13,18 @@ &tps { compatible = "ti,tps65217"; + interrupt-controller; + #interrupt-cells = <1>; + + charger { + compatible = "ti,tps65217-charger"; + status = "disabled"; + }; + + pwrbutton { + compatible = "ti,tps65217-pwrbutton"; + status = "disabled"; + }; regulators { #address-cells = <1>; diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi deleted file mode 100644 index 8c8a85176b64..000000000000 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Device Tree Source commonly used by UniPhier ARM SoCs - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - #clock-cells = <1>; - }; - - mio_rst: reset { - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - #clock-cells = <1>; - }; - - peri_rst: reset { - #reset-cells = <1>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ - }; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - sys_clk: clock { - #clock-cells = <1>; - }; - - sys_rst: reset { - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 95f342c9d9c1..a7c494d7c43a 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-ld4"; @@ -61,147 +61,267 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-ld4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld4-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-ld4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld4-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-ld4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld4-reset"; + #reset-cells = <1>; + }; + }; }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; - }; -&refclk { - clock-frequency = <24576000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-ld4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-ld4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-ld4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-ld4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-ld4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-ld4-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index ba700267ad66..e960b09ff01c 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro4"; @@ -69,155 +69,279 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* i2c4 does not exist */ + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-pro4-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-pro4-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-pro4-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro4-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro4-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro4-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro4-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro4-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro4-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro4-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 5357ea9c14b1..dbc5e5333163 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pro5"; @@ -56,157 +56,355 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; }; + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@116667000 { + opp-hz = /bits/ 64 <116667000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@175000000 { + opp-hz = /bits/ 64 <175000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@233334000 { + opp-hz = /bits/ 64 <233334000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@466667000 { + opp-hz = /bits/ 64 <466667000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@933334000 { + opp-hz = /bits/ 64 <933334000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - /* i2c4 does not exist */ + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl@59810000 { + compatible = "socionext,uniphier-pro5-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + sd_clk: clock { + compatible = "socionext,uniphier-pro5-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pro5-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pro5-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pro5-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pro5-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro5-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pro5-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pro5-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pro5-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <20000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro5-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro5-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro5-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro5-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro5-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro5-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 950f07ba0337..e9e031d63c1a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-pxs2"; @@ -56,170 +56,339 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; }; + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&peri_clk 8>; - clock-frequency = <400000>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&peri_clk 8>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&peri_clk 9>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&peri_clk 10>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + sdctrl@59810000 { + compatible = "socionext,uniphier-pxs2-sdctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + sd_clk: clock { + compatible = "socionext,uniphier-pxs2-sd-clock"; + #clock-cells = <1>; + }; + + sd_rst: reset { + compatible = "socionext,uniphier-pxs2-sd-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-pxs2-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-pxs2-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-pxs2-peri-reset"; + #reset-cells = <1>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pxs2-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0xf04>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0xf04>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-pxs2-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-pxs2-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-pxs2-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pxs2-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pxs2-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pxs2-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pxs2-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pxs2-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pxs2-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 5fa96c939b5c..9fad6bd2db8a 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -135,7 +135,6 @@ reg = <0x54006800 0x40>; interrupts = <0 33 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial1: serial@54006900 { @@ -144,7 +143,6 @@ reg = <0x54006900 0x40>; interrupts = <0 35 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; serial2: serial@54006a00 { @@ -153,7 +151,6 @@ reg = <0x54006a00 0x40>; interrupts = <0 37 4>; clocks = <&sys_clk 0>; - fifo-size = <64>; }; i2c0: i2c@58400000 { @@ -225,7 +222,7 @@ }; mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", + compatible = "socionext,uniphier-sld3-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; @@ -245,6 +242,9 @@ status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -252,6 +252,9 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -259,6 +262,9 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; usb3: usb@5a830100 { @@ -266,12 +272,15 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; + clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, + <&mio_rst 15>; }; sysctrl@f1840000 { - compatible = "socionext,uniphier-sysctrl", + compatible = "socionext,uniphier-sld3-sysctrl", "simple-mfd", "syscon"; - reg = <0xf1840000 0x4000>; + reg = <0xf1840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-sld3-clock"; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index d8cf0e7e11ea..b2c980ead7f0 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "uniphier-common32.dtsi" +/include/ "skeleton.dtsi" / { compatible = "socionext,uniphier-sld8"; @@ -61,146 +61,267 @@ }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; -}; -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; + soc { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 29 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&peri_clk 4>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&peri_clk 5>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&peri_clk 6>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&peri_clk 7>; + clock-frequency = <100000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-sld8-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-sld8-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld8-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-sld8-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-sld8-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-sld8-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-sld8-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; + }; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sld8-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld8-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld8-reset"; + #reset-cells = <1>; + }; + }; }; }; -&refclk { - clock-frequency = <25000000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-sld8-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-sld8-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-sld8-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-sld8-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-sld8-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-sld8-reset"; -}; +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 102838fcc588..15f4fd3f4695 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -81,7 +81,7 @@ #address-cells = <0>; interrupt-controller; reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, + <0 0x2c002000 0 0x2000>, <0 0x2c004000 0 0x2000>, <0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 0205c97efdef..bd107c5a0226 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -39,6 +39,7 @@ reg = <0>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -47,6 +48,7 @@ reg = <1>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -55,6 +57,7 @@ reg = <0x100>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu3: cpu@3 { @@ -63,6 +66,7 @@ reg = <0x101>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu4: cpu@4 { @@ -71,6 +75,7 @@ reg = <0x102>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; idle-states { @@ -126,7 +131,7 @@ #address-cells = <0>; interrupt-controller; reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, + <0 0x2c002000 0 0x2000>, <0 0x2c004000 0 0x2000>, <0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index b7417094dc11..21bfef957b68 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -108,6 +108,10 @@ status = "okay"; }; +&edma1 { + status = "okay"; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 1552db00cc59..958b4c42d320 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -153,7 +153,8 @@ switch0phy1: switch1phy0@1 { reg = <1>; interrupt-parent = <&switch0>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; switch0phy2: switch1phy0@2 { reg = <2>; interrupt-parent = <&switch0>; @@ -538,13 +539,6 @@ }; }; -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -714,13 +708,6 @@ >; }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - VF610_PAD_PTA30__I2C3_SCL 0x37ff - VF610_PAD_PTA31__I2C3_SDA 0x37ff - >; - }; - pinctrl_leds_debug: pinctrl-leds-debug { fsl,pins = < VF610_PAD_PTD20__GPIO_74 0x31c2 diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2c13ec696ac5..e9d28474c26a 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -194,6 +194,9 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; + dmas = <&edma1 1 12>, + <&edma1 1 13>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -206,6 +209,9 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; + dmas = <&edma1 1 14>, + <&edma1 1 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -520,6 +526,12 @@ status = "disabled"; }; + ocotp: ocotp@400a5000 { + compatible = "fsl,vf610-ocotp"; + reg = <0x400a5000 0x1000>; + clocks = <&clks VF610_CLK_OCOTP>; + }; + snvs0: snvs@400a7000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x400a7000 0x2000>; @@ -561,6 +573,9 @@ clocks = <&clks VF610_CLK_DSPI2>; clock-names = "dspi"; spi-num-chipselects = <2>; + dmas = <&edma1 0 10>, + <&edma1 0 11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -573,6 +588,9 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; + dmas = <&edma1 0 12>, + <&edma1 0 13>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index f283ff08381c..f3ac9bfe580e 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -10,9 +10,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { @@ -41,14 +42,15 @@ }; }; - pmu { + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; - reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + reg = <0xf8891000 0x1000>, + <0xf8893000 0x1000>; }; - regulator_vccpint: fixedregulator@0 { + regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts new file mode 100644 index 000000000000..b9376a4904b4 --- /dev/null +++ b/arch/arm/boot/dts/zynq-microzed.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2016 Jagan Teki + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq MicroZED Development Board"; + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&pinctrl0 { + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 307ed201d658..64a6390fc501 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -28,7 +28,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e96959b2e67a..0cdad2cc8b78 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -24,7 +24,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index be6a986bbbd8..ad4bb06dba25 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -24,7 +24,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 7250c1eac7f9..325379f7983c 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -23,7 +23,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x20000000>; }; diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts index d9e0f3e70671..590ec24b8749 100644 --- a/arch/arm/boot/dts/zynq-zybo.dts +++ b/arch/arm/boot/dts/zynq-zybo.dts @@ -23,7 +23,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x20000000>; }; diff --git a/arch/arm/common/bL_switcher_dummy_if.c b/arch/arm/common/bL_switcher_dummy_if.c index 6053f64c3752..4c10c6452678 100644 --- a/arch/arm/common/bL_switcher_dummy_if.c +++ b/arch/arm/common/bL_switcher_dummy_if.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include static ssize_t bL_switcher_write(struct file *file, const char __user *buf, diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 301281645d08..75055df1cda3 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -243,7 +243,8 @@ static int needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) } static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction dir) + enum dma_data_direction dir, + unsigned long attrs) { struct dmabounce_device_info *device_info = dev->archdata.dmabounce; struct safe_buffer *buf; @@ -262,7 +263,8 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, __func__, buf->ptr, virt_to_dma(dev, buf->ptr), buf->safe, buf->safe_dma_addr); - if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) { + if ((dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) && + !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { dev_dbg(dev, "%s: copy unsafe %p to safe %p, size %d\n", __func__, ptr, buf->safe, size); memcpy(buf->safe, ptr, size); @@ -272,7 +274,8 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, } static inline void unmap_single(struct device *dev, struct safe_buffer *buf, - size_t size, enum dma_data_direction dir) + size_t size, enum dma_data_direction dir, + unsigned long attrs) { BUG_ON(buf->size != size); BUG_ON(buf->direction != dir); @@ -283,7 +286,8 @@ static inline void unmap_single(struct device *dev, struct safe_buffer *buf, DO_STATS(dev->archdata.dmabounce->bounce_count++); - if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) { + if ((dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) && + !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { void *ptr = buf->ptr; dev_dbg(dev, "%s: copy back safe %p to unsafe %p size %d\n", @@ -334,7 +338,7 @@ static dma_addr_t dmabounce_map_page(struct device *dev, struct page *page, return DMA_ERROR_CODE; } - return map_single(dev, page_address(page) + offset, size, dir); + return map_single(dev, page_address(page) + offset, size, dir, attrs); } /* @@ -357,7 +361,7 @@ static void dmabounce_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t return; } - unmap_single(dev, buf, size, dir); + unmap_single(dev, buf, size, dir, attrs); } static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr, diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index f0dea52e49c4..113a5d815060 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -55,8 +55,9 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PXA2XX=y CONFIG_BLK_DEV_LOOP=m -CONFIG_IDE=m -CONFIG_BLK_DEV_IDECS=m +CONFIG_BLK_DEV_SD=m +CONFIG_ATA=m +CONFIG_PATA_PCMCIA=m CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=m diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig index 558ecd8f66ff..ab19ff1a0b71 100644 --- a/arch/arm/configs/assabet_defconfig +++ b/arch/arm/configs/assabet_defconfig @@ -34,7 +34,6 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=y -CONFIG_IDE=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_NET_PCMCIA=y diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index d59009878312..2a604aa3195b 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -42,8 +42,6 @@ CONFIG_MTD_SA1100=y CONFIG_PARPORT=m CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m -CONFIG_IDE=m -CONFIG_BLK_DEV_IDECD=m CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 79de828e49ad..4b89f4e6e849 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -73,6 +73,8 @@ CONFIG_SPI_BCM2835=y CONFIG_SPI_BCM2835AUX=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_BCM2835_THERMAL=y CONFIG_WATCHDOG=y CONFIG_BCM2835_WDT=y CONFIG_DRM=y diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig index dce912d146b4..57a2a18690b1 100644 --- a/arch/arm/configs/cerfcube_defconfig +++ b/arch/arm/configs/cerfcube_defconfig @@ -39,7 +39,6 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=m -CONFIG_IDE=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_NET_PCI=y diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index 52dbad5619e2..a8f3c596c39c 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig @@ -43,8 +43,9 @@ CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=1024 -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_PATA_PCMCIA=y # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index c1470a00f55a..462533bd84c6 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -99,15 +99,14 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_SHARPSL=y CONFIG_BLK_DEV_LOOP=y -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m CONFIG_CHR_DEV_OSST=m CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m CONFIG_SCSI_MULTI_LUN=y +CONFIG_ATA=y +CONFIG_PATA_PCMCIA=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_USB_CATC=m diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 5e5dd6bc5ed9..8806754f7175 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -7,13 +7,13 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y +CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set @@ -34,6 +34,7 @@ CONFIG_DAVINCI_MUX_WARNINGS=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y @@ -52,10 +53,10 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set +CONFIG_DA8XX_MSTPRI=y CONFIG_MTD=m CONFIG_MTD_BLOCK=m CONFIG_MTD_CFI=m @@ -116,6 +117,8 @@ CONFIG_SPI_DAVINCI=m CONFIG_PINCTRL_SINGLE=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y CONFIG_WATCHDOG=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_MFD_DM355EVM_MSP=y @@ -123,6 +126,8 @@ CONFIG_TPS6507X=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_TPS6507X=y +CONFIG_DRM=m +CONFIG_DRM_TILCDC=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DA8XX=y @@ -153,10 +158,13 @@ CONFIG_HID_SONY=m CONFIG_HID_SUNPLUS=m CONFIG_USB=m CONFIG_USB_MON=m +CONFIG_USB_OHCI_HCD=m CONFIG_USB_STORAGE=m CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_DA8XX=m CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_TEST=m +CONFIG_NOP_USB_XCEIV=m CONFIG_USB_GADGET=m CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y @@ -167,28 +175,32 @@ CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m CONFIG_USB_CDC_COMPOSITE=m -CONFIG_MMC=m +CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_DAVINCI=m +CONFIG_MMC_DAVINCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_OMAP=m CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_MEMORY=y CONFIG_TI_AEMIF=m +CONFIG_DA8XX_DDRCTL=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_XFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_TMPFS_XATTR=y CONFIG_JFFS2_FS=m CONFIG_UBIFS_FS=m CONFIG_CRAMFS=y diff --git a/arch/arm/configs/dram_0xc0000000.config b/arch/arm/configs/dram_0xc0000000.config new file mode 100644 index 000000000000..343d5333d973 --- /dev/null +++ b/arch/arm/configs/dram_0xc0000000.config @@ -0,0 +1 @@ +CONFIG_DRAM_BASE=0xc0000000 diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index c58f6841f8aa..79c415c33f69 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -155,6 +155,7 @@ CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_DRM=y CONFIG_DRM_EXYNOS=y diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig index 0142ec37e0be..ebeca11faa48 100644 --- a/arch/arm/configs/h3600_defconfig +++ b/arch/arm/configs/h3600_defconfig @@ -39,8 +39,9 @@ CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_PATA_PCMCIA=y CONFIG_NETDEVICES=y CONFIG_PCMCIA_PCNET=y CONFIG_PPP=m diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 8ec4dbbb50b0..cbe7faf55245 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -86,6 +86,7 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_MTD=y @@ -256,6 +257,7 @@ CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_MC13783=y diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index 869faae67201..69cb8f1efcea 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig @@ -26,6 +26,7 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index cf4918a2c51f..bb910d9df6c1 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -127,16 +127,17 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_EEPROM_LEGACY=y -CONFIG_IDE=y -CONFIG_BLK_DEV_CMD64X=y -CONFIG_BLK_DEV_HPT366=y -CONFIG_BLK_DEV_PDC202XX_NEW=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_ATA=y CONFIG_SATA_VIA=y CONFIG_PATA_ARTOP=y +CONFIG_PATA_CMD64X=y +CONFIG_PATA_HPT366=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_HPT3X2N=y +CONFIG_PATA_PDC2027X=y CONFIG_PATA_IXP4XX_CF=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index ea80e7e867c2..9056284139be 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -29,8 +29,9 @@ CONFIG_SA1100_FIR=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_PATA_PCMCIA=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_NET_ETHERNET=y diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig index faa2865658ac..8fc6fd09eb6d 100644 --- a/arch/arm/configs/lart_defconfig +++ b/arch/arm/configs/lart_defconfig @@ -36,8 +36,6 @@ CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_LART=y CONFIG_BLK_DEV_RAM=y -CONFIG_IDE=m -CONFIG_BLK_DEV_IDECD=m CONFIG_NETDEVICES=y CONFIG_DUMMY=m CONFIG_NET_ETHERNET=y diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig index 04efa1b3ef25..e8d26b805be6 100644 --- a/arch/arm/configs/mainstone_defconfig +++ b/arch/arm/configs/mainstone_defconfig @@ -27,7 +27,6 @@ CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_GEOMETRY=y # CONFIG_MTD_CFI_I1 is not set CONFIG_MTD_CFI_INTELEXT=y -CONFIG_IDE=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 2658b80fa263..361686a362f1 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -150,7 +150,6 @@ CONFIG_SPI=y CONFIG_SPI_ATMEL=y CONFIG_SPI_IMX=y CONFIG_SPI_ORION=y -CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_QNAP=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 30f39acd61bd..b01a43851294 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -173,6 +173,11 @@ CONFIG_CAN_RCAR=m CONFIG_CAN_XILINXCAN=y CONFIG_CAN_MCP251X=y CONFIG_NET_DSA_BCM_SF2=m +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m CONFIG_CAN_SUN4I=y CONFIG_BT=m CONFIG_BT_MRVL=m @@ -235,6 +240,7 @@ CONFIG_HIX5HD2_GMAC=y CONFIG_SUN4I_EMAC=y CONFIG_MACB=y CONFIG_BCMGENET=m +CONFIG_BGMAC_BCMA=y CONFIG_SYSTEMPORT=m CONFIG_NET_CALXEDA_XGMAC=y CONFIG_GIANFAR=y @@ -404,7 +410,6 @@ CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y @@ -450,7 +455,6 @@ CONFIG_RCAR_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_EXYNOS_THERMAL=m -CONFIG_ST_THERMAL_SYSCFG=y CONFIG_ST_THERMAL_MEMMAP=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m @@ -467,6 +471,7 @@ CONFIG_MESON_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_BCM2835_WDT=y +CONFIG_BCM47XX_WATCHDOG=y CONFIG_BCM7038_WDT=m CONFIG_BCM_KONA_WDT=y CONFIG_MFD_ACT8945A=y @@ -561,7 +566,9 @@ CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_STI_BDISP=m +CONFIG_VIDEO_STI_HVA=m CONFIG_VIDEO_RENESAS_JPU=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_V4L_TEST_DRIVERS=y @@ -572,6 +579,7 @@ CONFIG_DRM=y CONFIG_DRM_I2C_ADV7511=m # CONFIG_DRM_I2C_CH7006 is not set # CONFIG_DRM_I2C_SIL164 is not set +CONFIG_DRM_DUMB_VGA_DAC=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_NOUVEAU=m @@ -802,6 +810,10 @@ CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y +CONFIG_BCMA=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y CONFIG_QCOM_GSBI=y CONFIG_QCOM_PM=y CONFIG_QCOM_SMEM=y @@ -868,9 +880,7 @@ CONFIG_PHY_ROCKCHIP_DP=m CONFIG_PHY_ROCKCHIP_USB=m CONFIG_PHY_QCOM_APQ8064_SATA=m CONFIG_PHY_MIPHY28LP=y -CONFIG_PHY_MIPHY365X=y CONFIG_PHY_RCAR_GEN2=m -CONFIG_PHY_STIH41X_USB=y CONFIG_PHY_STIH407_USB=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN9I_USB=y @@ -883,6 +893,8 @@ CONFIG_BCM2835_MBOX=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_EFI_VARS=m CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig index 4f3dfb21772b..f1395bbd436c 100644 --- a/arch/arm/configs/netwinder_defconfig +++ b/arch/arm/configs/netwinder_defconfig @@ -8,7 +8,7 @@ CONFIG_LEDS_CPU=y CONFIG_DEPRECATED_PARAM_STRUCT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=0x301" +CONFIG_CMDLINE="root=0x801" CONFIG_FPE_NWFPE=y CONFIG_BINFMT_AOUT=y CONFIG_NET=y @@ -27,8 +27,9 @@ CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_PC_SUPERIO=y CONFIG_BLK_DEV_LOOP=y -CONFIG_IDE=y -CONFIG_BLK_DEV_SL82C105=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_PATA_WINBOND=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_MII=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 0c8a78734536..6ffc9844542d 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -96,14 +96,14 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_IDE=m -CONFIG_BLK_DEV_IDECS=m CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y +CONFIG_ATA=m +CONFIG_PATA_PCMCIA=m CONFIG_NETDEVICES=y CONFIG_TUN=y CONFIG_PHYLIB=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 53e1a884a1ea..195c98b85568 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -1,7 +1,6 @@ CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_FHANDLE=y CONFIG_AUDIT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -40,7 +39,6 @@ CONFIG_ARCH_MULTI_V6=y CONFIG_POWER_AVS_OMAP=y CONFIG_POWER_AVS_OMAP_CLASS3=y CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX_DEBUG=y CONFIG_ARCH_OMAP2=y CONFIG_ARCH_OMAP3=y CONFIG_ARCH_OMAP4=y @@ -50,7 +48,6 @@ CONFIG_SOC_AM43XX=y CONFIG_SOC_DRA7XX=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_ERRATA_411920=y -CONFIG_ARM_ERRATA_430973=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_CMA=y @@ -62,7 +59,6 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" CONFIG_KEXEC=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -205,6 +201,7 @@ CONFIG_TOUCHSCREEN_ADS7846=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_TSC2004=m CONFIG_TOUCHSCREEN_TSC2005=m CONFIG_TOUCHSCREEN_TSC2007=m CONFIG_INPUT_MISC=y @@ -240,14 +237,14 @@ CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TWL4030=y CONFIG_W1=m CONFIG_HDQ_MASTER_OMAP=m +CONFIG_POWER_AVS=y +CONFIG_POWER_RESET=y CONFIG_BATTERY_BQ27XXX=m CONFIG_CHARGER_ISP1704=m CONFIG_CHARGER_TWL4030=m CONFIG_CHARGER_BQ2415X=m CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24735=m -CONFIG_POWER_RESET=y -CONFIG_POWER_AVS=y CONFIG_HWMON=m CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_LM75=m @@ -267,10 +264,13 @@ CONFIG_TWL4030_WATCHDOG=m CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y +CONFIG_MFD_TI_LP873X=y CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_LP872X=y +CONFIG_REGULATOR_LP873X=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PBIAS=y CONFIG_REGULATOR_TI_ABB=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 74e9cd759b99..8c3a0108a231 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -161,8 +161,8 @@ CONFIG_APQ_MMCC_8084=y CONFIG_IPQ_LCC_806X=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_LCC_8960=y -CONFIG_MSM_GCC_9615=y -CONFIG_MSM_LCC_9615=y +CONFIG_MDM_GCC_9615=y +CONFIG_MDM_LCC_9615=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y CONFIG_HWSPINLOCK_QCOM=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index bc4bfe02e611..4364040ed696 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -219,20 +219,16 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_UB=m CONFIG_BLK_DEV_RAM=y CONFIG_ATA_OVER_ETH=m -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDETAPE=m -CONFIG_BLK_DEV_PLATFORM=y -CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_PATA_PLATFORM=y CONFIG_NETDEVICES=y CONFIG_DM9000=y CONFIG_INPUT_EVDEV=y diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig index b0b96942f4bd..e52395629810 100644 --- a/arch/arm/configs/shannon_defconfig +++ b/arch/arm/configs/shannon_defconfig @@ -25,7 +25,6 @@ CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_IDE=m CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_NET_PCMCIA=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index baa07a46a88b..1b0f8ae36fb3 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -2,6 +2,7 @@ CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 9f84be5b3ac5..2e1d254e06a2 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -25,6 +25,7 @@ CONFIG_PCIE_ALTERA_MSI=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_AEABI=y +CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_VFP=y @@ -50,6 +51,10 @@ CONFIG_CAN_DEBUG_DEVICES=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_SIZE=8192 @@ -101,18 +106,28 @@ CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y CONFIG_DMATEST=m CONFIG_FPGA=y +CONFIG_FPGA_REGION=y CONFIG_FPGA_MGR_SOCFPGA=y +CONFIG_FPGA_MGR_SOCFPGA_A10=y +CONFIG_FPGA_BRIDGE=y +CONFIG_SOCFPGA_FPGA_BRIDGE=y +CONFIG_ALTERA_FREEZE_BRIDGE=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT3_FS=y +CONFIG_AUTOFS4_FS=y CONFIG_VFAT_FS=y CONFIG_NTFS_FS=y CONFIG_NTFS_RW=y CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index a1ede1966baf..d8c529332fb4 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -96,15 +96,13 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_SHARPSL=y CONFIG_BLK_DEV_LOOP=y -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m CONFIG_CHR_DEV_OSST=m CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_MULTI_LUN=y +CONFIG_ATA=y +CONFIG_PATA_PCMCIA=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_USB_CATC=m diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 1e5ec2a0e4cf..5a72d694662f 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -38,8 +38,7 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set # CONFIG_BLK_DEV is not set CONFIG_EEPROM_93CX6=y -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set +CONFIG_KEYBOARD_GPIO=y # CONFIG_VT is not set # CONFIG_UNIX98_PTYS is not set # CONFIG_LEGACY_PTYS is not set diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 714da336ec86..dfeee5c51b40 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -98,6 +98,7 @@ CONFIG_MEDIA_RC_SUPPORT=y CONFIG_RC_DEVICES=y CONFIG_IR_SUNXI=y CONFIG_DRM=y +CONFIG_DRM_DUMB_VGA_DAC=y CONFIG_DRM_SUN4I=y CONFIG_FB=y CONFIG_FB_SIMPLE=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 6012a1ec779f..844eeef5a509 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -1,16 +1,15 @@ CONFIG_SYSVIPC=y -CONFIG_FHANDLE=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y CONFIG_BLK_DEV_INITRD=y # CONFIG_ELF_CORE is not set CONFIG_EMBEDDED=y @@ -24,14 +23,10 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_TEGRA=y -CONFIG_ARCH_TEGRA_2x_SOC=y -CONFIG_ARCH_TEGRA_3x_SOC=y -CONFIG_ARCH_TEGRA_114_SOC=y -CONFIG_ARCH_TEGRA_124_SOC=y CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y CONFIG_PCI_MSI=y CONFIG_PCI_TEGRA=y -CONFIG_PCIEPORTBUS=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -41,7 +36,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y @@ -59,7 +53,6 @@ CONFIG_IP_PNP_RARP=y CONFIG_INET_ESP=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_OPTIMISTIC_DAD=y @@ -86,6 +79,7 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_TEGRA_GMI=y CONFIG_MTD=y CONFIG_MTD_M25P80=y CONFIG_MTD_SPI_NOR=y @@ -131,8 +125,8 @@ CONFIG_INPUT_MPU3050=y # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_TEGRA=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_TEGRA=y # CONFIG_HW_RANDOM is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y @@ -151,11 +145,11 @@ CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y -CONFIG_BATTERY_SBS=y -CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y +CONFIG_BATTERY_SBS=y +CONFIG_CHARGER_TPS65090=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM95245=y CONFIG_WATCHDOG=y @@ -216,6 +210,7 @@ CONFIG_SND_SOC_TEGRA_WM9712=y CONFIG_SND_SOC_TEGRA_TRIMSLICE=y CONFIG_SND_SOC_TEGRA_ALC5632=y CONFIG_SND_SOC_TEGRA_MAX98090=y +CONFIG_SND_SOC_TEGRA_SGTL5000=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_TEGRA=y @@ -262,6 +257,10 @@ CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y +CONFIG_ARCH_TEGRA_2x_SOC=y +CONFIG_ARCH_TEGRA_3x_SOC=y +CONFIG_ARCH_TEGRA_114_SOC=y +CONFIG_ARCH_TEGRA_124_SOC=y CONFIG_MEMORY=y CONFIG_IIO=y CONFIG_AK8975=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index b7b09189f1c5..e2151a7aaf49 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -4,7 +4,6 @@ CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y -CONFIG_PERF_EVENTS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set @@ -26,7 +25,6 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_U8500_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y -CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -108,18 +106,19 @@ CONFIG_DMADEVICES=y CONFIG_STE_DMA40=y CONFIG_HSEM_U8500=y CONFIG_IIO=y -CONFIG_IIO_BUFFER=y +CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_GYRO_3AXIS=y CONFIG_BH1780=y +CONFIG_AK8974=y CONFIG_IIO_ST_MAGN_3AXIS=y +CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_IIO_ST_PRESS=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y -CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig index 27ed1b1cd1d7..13f1b4c289d4 100644 --- a/arch/arm/crypto/Kconfig +++ b/arch/arm/crypto/Kconfig @@ -88,9 +88,9 @@ config CRYPTO_AES_ARM config CRYPTO_AES_ARM_BS tristate "Bit sliced AES using NEON instructions" depends on KERNEL_MODE_NEON - select CRYPTO_ALGAPI select CRYPTO_AES_ARM - select CRYPTO_ABLK_HELPER + select CRYPTO_BLKCIPHER + select CRYPTO_SIMD help Use a faster and more secure NEON based implementation of AES in CBC, CTR and XTS modes @@ -104,8 +104,8 @@ config CRYPTO_AES_ARM_BS config CRYPTO_AES_ARM_CE tristate "Accelerated AES using ARMv8 Crypto Extensions" depends on KERNEL_MODE_NEON - select CRYPTO_ALGAPI - select CRYPTO_ABLK_HELPER + select CRYPTO_BLKCIPHER + select CRYPTO_SIMD help Use an implementation of AES in CBC, CTR and XTS modes that uses ARMv8 Crypto Extensions @@ -120,4 +120,14 @@ config CRYPTO_GHASH_ARM_CE that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64) that is part of the ARMv8 Crypto Extensions +config CRYPTO_CRCT10DIF_ARM_CE + tristate "CRCT10DIF digest algorithm using PMULL instructions" + depends on KERNEL_MODE_NEON && CRC_T10DIF + select CRYPTO_HASH + +config CRYPTO_CRC32_ARM_CE + tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions" + depends on KERNEL_MODE_NEON && CRC32 + select CRYPTO_HASH + endif diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index fc5150702b64..b578a1820ab1 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -13,6 +13,8 @@ ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o +ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o +ce-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o ifneq ($(ce-obj-y)$(ce-obj-m),) ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y) @@ -36,6 +38,8 @@ sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o sha2-arm-ce-y := sha2-ce-core.o sha2-ce-glue.o aes-arm-ce-y := aes-ce-core.o aes-ce-glue.o ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o +crct10dif-arm-ce-y := crct10dif-ce-core.o crct10dif-ce-glue.o +crc32-arm-ce-y:= crc32-ce-core.o crc32-ce-glue.o quiet_cmd_perl = PERL $@ cmd_perl = $(PERL) $(<) > $(@) diff --git a/arch/arm/crypto/aes-ce-glue.c b/arch/arm/crypto/aes-ce-glue.c index aef022a87c53..8857531915bf 100644 --- a/arch/arm/crypto/aes-ce-glue.c +++ b/arch/arm/crypto/aes-ce-glue.c @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include #include @@ -88,8 +88,13 @@ static int ce_aes_expandkey(struct crypto_aes_ctx *ctx, const u8 *in_key, u32 *rki = ctx->key_enc + (i * kwords); u32 *rko = rki + kwords; +#ifndef CONFIG_CPU_BIG_ENDIAN rko[0] = ror32(ce_aes_sub(rki[kwords - 1]), 8); rko[0] = rko[0] ^ rki[0] ^ rcon[i]; +#else + rko[0] = rol32(ce_aes_sub(rki[kwords - 1]), 8); + rko[0] = rko[0] ^ rki[0] ^ (rcon[i] << 24); +#endif rko[1] = rko[0] ^ rki[1]; rko[2] = rko[1] ^ rki[2]; rko[3] = rko[2] ^ rki[3]; @@ -128,17 +133,17 @@ static int ce_aes_expandkey(struct crypto_aes_ctx *ctx, const u8 *in_key, return 0; } -static int ce_aes_setkey(struct crypto_tfm *tfm, const u8 *in_key, +static int ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len) { - struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); int ret; ret = ce_aes_expandkey(ctx, in_key, key_len); if (!ret) return 0; - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } @@ -147,13 +152,13 @@ struct crypto_aes_xts_ctx { struct crypto_aes_ctx __aligned(8) key2; }; -static int xts_set_key(struct crypto_tfm *tfm, const u8 *in_key, +static int xts_set_key(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len) { - struct crypto_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_aes_xts_ctx *ctx = crypto_skcipher_ctx(tfm); int ret; - ret = xts_check_key(tfm, in_key, key_len); + ret = xts_verify_key(tfm, in_key, key_len); if (ret) return ret; @@ -164,130 +169,113 @@ static int xts_set_key(struct crypto_tfm *tfm, const u8 *in_key, if (!ret) return 0; - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } -static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int ecb_encrypt(struct skcipher_request *req) { - struct crypto_aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; unsigned int blocks; int err; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) { ce_aes_ecb_encrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key_enc, num_rounds(ctx), blocks); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int ecb_decrypt(struct skcipher_request *req) { - struct crypto_aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; unsigned int blocks; int err; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) { ce_aes_ecb_decrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key_dec, num_rounds(ctx), blocks); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int cbc_encrypt(struct skcipher_request *req) { - struct crypto_aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; unsigned int blocks; int err; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) { ce_aes_cbc_encrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key_enc, num_rounds(ctx), blocks, walk.iv); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int cbc_decrypt(struct skcipher_request *req) { - struct crypto_aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; unsigned int blocks; int err; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) { ce_aes_cbc_decrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key_dec, num_rounds(ctx), blocks, walk.iv); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static int ctr_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int ctr_encrypt(struct skcipher_request *req) { - struct crypto_aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; int err, blocks; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); while ((blocks = (walk.nbytes / AES_BLOCK_SIZE))) { ce_aes_ctr_encrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key_enc, num_rounds(ctx), blocks, walk.iv); - nbytes -= blocks * AES_BLOCK_SIZE; - if (nbytes && nbytes == walk.nbytes % AES_BLOCK_SIZE) - break; - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } - if (walk.nbytes % AES_BLOCK_SIZE) { - u8 *tdst = walk.dst.virt.addr + blocks * AES_BLOCK_SIZE; - u8 *tsrc = walk.src.virt.addr + blocks * AES_BLOCK_SIZE; + if (walk.nbytes) { u8 __aligned(8) tail[AES_BLOCK_SIZE]; + unsigned int nbytes = walk.nbytes; + u8 *tdst = walk.dst.virt.addr; + u8 *tsrc = walk.src.virt.addr; /* * Minimum alignment is 8 bytes, so if nbytes is <= 8, we need @@ -298,231 +286,172 @@ static int ctr_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, ce_aes_ctr_encrypt(tail, tsrc, (u8 *)ctx->key_enc, num_rounds(ctx), blocks, walk.iv); memcpy(tdst, tail, nbytes); - err = blkcipher_walk_done(desc, &walk, 0); + err = skcipher_walk_done(&walk, 0); } kernel_neon_end(); return err; } -static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int xts_encrypt(struct skcipher_request *req) { - struct crypto_aes_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_xts_ctx *ctx = crypto_skcipher_ctx(tfm); int err, first, rounds = num_rounds(&ctx->key1); - struct blkcipher_walk walk; + struct skcipher_walk walk; unsigned int blocks; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) { ce_aes_xts_encrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key1.key_enc, rounds, blocks, walk.iv, (u8 *)ctx->key2.key_enc, first); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int xts_decrypt(struct skcipher_request *req) { - struct crypto_aes_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct crypto_aes_xts_ctx *ctx = crypto_skcipher_ctx(tfm); int err, first, rounds = num_rounds(&ctx->key1); - struct blkcipher_walk walk; + struct skcipher_walk walk; unsigned int blocks; - desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); + err = skcipher_walk_virt(&walk, req, true); kernel_neon_begin(); for (first = 1; (blocks = (walk.nbytes / AES_BLOCK_SIZE)); first = 0) { ce_aes_xts_decrypt(walk.dst.virt.addr, walk.src.virt.addr, (u8 *)ctx->key1.key_dec, rounds, blocks, walk.iv, (u8 *)ctx->key2.key_enc, first); - err = blkcipher_walk_done(desc, &walk, - walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } kernel_neon_end(); return err; } -static struct crypto_alg aes_algs[] = { { - .cra_name = "__ecb-aes-ce", - .cra_driver_name = "__driver-ecb-aes-ce", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct crypto_aes_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = 0, - .setkey = ce_aes_setkey, - .encrypt = ecb_encrypt, - .decrypt = ecb_decrypt, +static struct skcipher_alg aes_algs[] = { { + .base = { + .cra_name = "__ecb(aes)", + .cra_driver_name = "__ecb-aes-ce", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct crypto_aes_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = ce_aes_setkey, + .encrypt = ecb_encrypt, + .decrypt = ecb_decrypt, }, { - .cra_name = "__cbc-aes-ce", - .cra_driver_name = "__driver-cbc-aes-ce", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct crypto_aes_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ce_aes_setkey, - .encrypt = cbc_encrypt, - .decrypt = cbc_decrypt, + .base = { + .cra_name = "__cbc(aes)", + .cra_driver_name = "__cbc-aes-ce", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct crypto_aes_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = ce_aes_setkey, + .encrypt = cbc_encrypt, + .decrypt = cbc_decrypt, }, { - .cra_name = "__ctr-aes-ce", - .cra_driver_name = "__driver-ctr-aes-ce", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct crypto_aes_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ce_aes_setkey, - .encrypt = ctr_encrypt, - .decrypt = ctr_encrypt, + .base = { + .cra_name = "__ctr(aes)", + .cra_driver_name = "__ctr-aes-ce", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct crypto_aes_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .chunksize = AES_BLOCK_SIZE, + .setkey = ce_aes_setkey, + .encrypt = ctr_encrypt, + .decrypt = ctr_encrypt, }, { - .cra_name = "__xts-aes-ce", - .cra_driver_name = "__driver-xts-aes-ce", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct crypto_aes_xts_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = xts_set_key, - .encrypt = xts_encrypt, - .decrypt = xts_decrypt, + .base = { + .cra_name = "__xts(aes)", + .cra_driver_name = "__xts-aes-ce", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct crypto_aes_xts_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, -}, { - .cra_name = "ecb(aes)", - .cra_driver_name = "ecb-aes-ce", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = 0, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "cbc(aes)", - .cra_driver_name = "cbc-aes-ce", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "ctr(aes)", - .cra_driver_name = "ctr-aes-ce", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "xts(aes)", - .cra_driver_name = "xts-aes-ce", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } + .min_keysize = 2 * AES_MIN_KEY_SIZE, + .max_keysize = 2 * AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = xts_set_key, + .encrypt = xts_encrypt, + .decrypt = xts_decrypt, } }; +static struct simd_skcipher_alg *aes_simd_algs[ARRAY_SIZE(aes_algs)]; + +static void aes_exit(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aes_simd_algs) && aes_simd_algs[i]; i++) + simd_skcipher_free(aes_simd_algs[i]); + + crypto_unregister_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); +} + static int __init aes_init(void) { + struct simd_skcipher_alg *simd; + const char *basename; + const char *algname; + const char *drvname; + int err; + int i; + if (!(elf_hwcap2 & HWCAP2_AES)) return -ENODEV; - return crypto_register_algs(aes_algs, ARRAY_SIZE(aes_algs)); -} -static void __exit aes_exit(void) -{ - crypto_unregister_algs(aes_algs, ARRAY_SIZE(aes_algs)); + err = crypto_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs)); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(aes_algs); i++) { + algname = aes_algs[i].base.cra_name + 2; + drvname = aes_algs[i].base.cra_driver_name + 2; + basename = aes_algs[i].base.cra_driver_name; + simd = simd_skcipher_create_compat(algname, drvname, basename); + err = PTR_ERR(simd); + if (IS_ERR(simd)) + goto unregister_simds; + + aes_simd_algs[i] = simd; + } + + return 0; + +unregister_simds: + aes_exit(); + return err; } module_init(aes_init); diff --git a/arch/arm/crypto/aesbs-glue.c b/arch/arm/crypto/aesbs-glue.c index 0511a6cafe24..d8e06de72ef3 100644 --- a/arch/arm/crypto/aesbs-glue.c +++ b/arch/arm/crypto/aesbs-glue.c @@ -10,8 +10,9 @@ #include #include -#include -#include +#include +#include +#include #include #include @@ -55,14 +56,14 @@ struct aesbs_xts_ctx { struct AES_KEY twkey; }; -static int aesbs_cbc_set_key(struct crypto_tfm *tfm, const u8 *in_key, +static int aesbs_cbc_set_key(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len) { - struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm); + struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); int bits = key_len * 8; if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } ctx->dec.rk = ctx->enc; @@ -71,33 +72,33 @@ static int aesbs_cbc_set_key(struct crypto_tfm *tfm, const u8 *in_key, return 0; } -static int aesbs_ctr_set_key(struct crypto_tfm *tfm, const u8 *in_key, +static int aesbs_ctr_set_key(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len) { - struct aesbs_ctr_ctx *ctx = crypto_tfm_ctx(tfm); + struct aesbs_ctr_ctx *ctx = crypto_skcipher_ctx(tfm); int bits = key_len * 8; if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc.rk)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } ctx->enc.converted = 0; return 0; } -static int aesbs_xts_set_key(struct crypto_tfm *tfm, const u8 *in_key, +static int aesbs_xts_set_key(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len) { - struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm); + struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm); int bits = key_len * 4; int err; - err = xts_check_key(tfm, in_key, key_len); + err = xts_verify_key(tfm, in_key, key_len); if (err) return err; if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc.rk)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } ctx->dec.rk = ctx->enc.rk; @@ -107,88 +108,52 @@ static int aesbs_xts_set_key(struct crypto_tfm *tfm, const u8 *in_key, return 0; } -static int aesbs_cbc_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static inline void aesbs_encrypt_one(struct crypto_skcipher *tfm, + const u8 *src, u8 *dst) { - struct aesbs_cbc_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - int err; + struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); - - while (walk.nbytes) { - u32 blocks = walk.nbytes / AES_BLOCK_SIZE; - u8 *src = walk.src.virt.addr; - - if (walk.dst.virt.addr == walk.src.virt.addr) { - u8 *iv = walk.iv; - - do { - crypto_xor(src, iv, AES_BLOCK_SIZE); - AES_encrypt(src, src, &ctx->enc); - iv = src; - src += AES_BLOCK_SIZE; - } while (--blocks); - memcpy(walk.iv, iv, AES_BLOCK_SIZE); - } else { - u8 *dst = walk.dst.virt.addr; - - do { - crypto_xor(walk.iv, src, AES_BLOCK_SIZE); - AES_encrypt(walk.iv, dst, &ctx->enc); - memcpy(walk.iv, dst, AES_BLOCK_SIZE); - src += AES_BLOCK_SIZE; - dst += AES_BLOCK_SIZE; - } while (--blocks); - } - err = blkcipher_walk_done(desc, &walk, walk.nbytes % AES_BLOCK_SIZE); - } - return err; + AES_encrypt(src, dst, &ctx->enc); } -static int aesbs_cbc_decrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int aesbs_cbc_encrypt(struct skcipher_request *req) { - struct aesbs_cbc_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + return crypto_cbc_encrypt_walk(req, aesbs_encrypt_one); +} + +static inline void aesbs_decrypt_one(struct crypto_skcipher *tfm, + const u8 *src, u8 *dst) +{ + struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); + + AES_decrypt(src, dst, &ctx->dec.rk); +} + +static int aesbs_cbc_decrypt(struct skcipher_request *req) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; + unsigned int nbytes; int err; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); - - while ((walk.nbytes / AES_BLOCK_SIZE) >= 8) { - kernel_neon_begin(); - bsaes_cbc_encrypt(walk.src.virt.addr, walk.dst.virt.addr, - walk.nbytes, &ctx->dec, walk.iv); - kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, walk.nbytes % AES_BLOCK_SIZE); - } - while (walk.nbytes) { - u32 blocks = walk.nbytes / AES_BLOCK_SIZE; + for (err = skcipher_walk_virt(&walk, req, false); + (nbytes = walk.nbytes); err = skcipher_walk_done(&walk, nbytes)) { + u32 blocks = nbytes / AES_BLOCK_SIZE; u8 *dst = walk.dst.virt.addr; u8 *src = walk.src.virt.addr; - u8 bk[2][AES_BLOCK_SIZE]; u8 *iv = walk.iv; - do { - if (walk.dst.virt.addr == walk.src.virt.addr) - memcpy(bk[blocks & 1], src, AES_BLOCK_SIZE); + if (blocks >= 8) { + kernel_neon_begin(); + bsaes_cbc_encrypt(src, dst, nbytes, &ctx->dec, iv); + kernel_neon_end(); + nbytes %= AES_BLOCK_SIZE; + continue; + } - AES_decrypt(src, dst, &ctx->dec.rk); - crypto_xor(dst, iv, AES_BLOCK_SIZE); - - if (walk.dst.virt.addr == walk.src.virt.addr) - iv = bk[blocks & 1]; - else - iv = src; - - dst += AES_BLOCK_SIZE; - src += AES_BLOCK_SIZE; - } while (--blocks); - err = blkcipher_walk_done(desc, &walk, walk.nbytes % AES_BLOCK_SIZE); + nbytes = crypto_cbc_decrypt_blocks(&walk, tfm, + aesbs_decrypt_one); } return err; } @@ -206,17 +171,15 @@ static void inc_be128_ctr(__be32 ctr[], u32 addend) } } -static int aesbs_ctr_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes) +static int aesbs_ctr_encrypt(struct skcipher_request *req) { - struct aesbs_ctr_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct aesbs_ctr_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; u32 blocks; int err; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); + err = skcipher_walk_virt(&walk, req, false); while ((blocks = walk.nbytes / AES_BLOCK_SIZE)) { u32 tail = walk.nbytes % AES_BLOCK_SIZE; @@ -235,11 +198,7 @@ static int aesbs_ctr_encrypt(struct blkcipher_desc *desc, kernel_neon_end(); inc_be128_ctr(ctr, blocks); - nbytes -= blocks * AES_BLOCK_SIZE; - if (nbytes && nbytes == tail && nbytes <= AES_BLOCK_SIZE) - break; - - err = blkcipher_walk_done(desc, &walk, tail); + err = skcipher_walk_done(&walk, tail); } if (walk.nbytes) { u8 *tdst = walk.dst.virt.addr + blocks * AES_BLOCK_SIZE; @@ -248,23 +207,21 @@ static int aesbs_ctr_encrypt(struct blkcipher_desc *desc, AES_encrypt(walk.iv, ks, &ctx->enc.rk); if (tdst != tsrc) - memcpy(tdst, tsrc, nbytes); - crypto_xor(tdst, ks, nbytes); - err = blkcipher_walk_done(desc, &walk, 0); + memcpy(tdst, tsrc, walk.nbytes); + crypto_xor(tdst, ks, walk.nbytes); + err = skcipher_walk_done(&walk, 0); } return err; } -static int aesbs_xts_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int aesbs_xts_encrypt(struct skcipher_request *req) { - struct aesbs_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; int err; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); + err = skcipher_walk_virt(&walk, req, false); /* generate the initial tweak */ AES_encrypt(walk.iv, walk.iv, &ctx->twkey); @@ -274,21 +231,19 @@ static int aesbs_xts_encrypt(struct blkcipher_desc *desc, bsaes_xts_encrypt(walk.src.virt.addr, walk.dst.virt.addr, walk.nbytes, &ctx->enc, walk.iv); kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } return err; } -static int aesbs_xts_decrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) +static int aesbs_xts_decrypt(struct skcipher_request *req) { - struct aesbs_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_walk walk; int err; - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); + err = skcipher_walk_virt(&walk, req, false); /* generate the initial tweak */ AES_encrypt(walk.iv, walk.iv, &ctx->twkey); @@ -298,141 +253,110 @@ static int aesbs_xts_decrypt(struct blkcipher_desc *desc, bsaes_xts_decrypt(walk.src.virt.addr, walk.dst.virt.addr, walk.nbytes, &ctx->dec, walk.iv); kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, walk.nbytes % AES_BLOCK_SIZE); + err = skcipher_walk_done(&walk, walk.nbytes % AES_BLOCK_SIZE); } return err; } -static struct crypto_alg aesbs_algs[] = { { - .cra_name = "__cbc-aes-neonbs", - .cra_driver_name = "__driver-cbc-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct aesbs_cbc_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_cbc_set_key, - .encrypt = aesbs_cbc_encrypt, - .decrypt = aesbs_cbc_decrypt, +static struct skcipher_alg aesbs_algs[] = { { + .base = { + .cra_name = "__cbc(aes)", + .cra_driver_name = "__cbc-aes-neonbs", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct aesbs_cbc_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = aesbs_cbc_set_key, + .encrypt = aesbs_cbc_encrypt, + .decrypt = aesbs_cbc_decrypt, }, { - .cra_name = "__ctr-aes-neonbs", - .cra_driver_name = "__driver-ctr-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct aesbs_ctr_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_ctr_set_key, - .encrypt = aesbs_ctr_encrypt, - .decrypt = aesbs_ctr_encrypt, + .base = { + .cra_name = "__ctr(aes)", + .cra_driver_name = "__ctr-aes-neonbs", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct aesbs_ctr_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .chunksize = AES_BLOCK_SIZE, + .setkey = aesbs_ctr_set_key, + .encrypt = aesbs_ctr_encrypt, + .decrypt = aesbs_ctr_encrypt, }, { - .cra_name = "__xts-aes-neonbs", - .cra_driver_name = "__driver-xts-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_INTERNAL, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct aesbs_xts_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_xts_set_key, - .encrypt = aesbs_xts_encrypt, - .decrypt = aesbs_xts_decrypt, + .base = { + .cra_name = "__xts(aes)", + .cra_driver_name = "__xts-aes-neonbs", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_INTERNAL, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct aesbs_xts_ctx), + .cra_alignmask = 7, + .cra_module = THIS_MODULE, }, -}, { - .cra_name = "cbc(aes)", - .cra_driver_name = "cbc-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = __ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "ctr(aes)", - .cra_driver_name = "ctr-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "xts(aes)", - .cra_driver_name = "xts-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } + .min_keysize = 2 * AES_MIN_KEY_SIZE, + .max_keysize = 2 * AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = aesbs_xts_set_key, + .encrypt = aesbs_xts_encrypt, + .decrypt = aesbs_xts_decrypt, } }; +struct simd_skcipher_alg *aesbs_simd_algs[ARRAY_SIZE(aesbs_algs)]; + +static void aesbs_mod_exit(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aesbs_simd_algs) && aesbs_simd_algs[i]; i++) + simd_skcipher_free(aesbs_simd_algs[i]); + + crypto_unregister_skciphers(aesbs_algs, ARRAY_SIZE(aesbs_algs)); +} + static int __init aesbs_mod_init(void) { + struct simd_skcipher_alg *simd; + const char *basename; + const char *algname; + const char *drvname; + int err; + int i; + if (!cpu_has_neon()) return -ENODEV; - return crypto_register_algs(aesbs_algs, ARRAY_SIZE(aesbs_algs)); -} + err = crypto_register_skciphers(aesbs_algs, ARRAY_SIZE(aesbs_algs)); + if (err) + return err; -static void __exit aesbs_mod_exit(void) -{ - crypto_unregister_algs(aesbs_algs, ARRAY_SIZE(aesbs_algs)); + for (i = 0; i < ARRAY_SIZE(aesbs_algs); i++) { + algname = aesbs_algs[i].base.cra_name + 2; + drvname = aesbs_algs[i].base.cra_driver_name + 2; + basename = aesbs_algs[i].base.cra_driver_name; + simd = simd_skcipher_create_compat(algname, drvname, basename); + err = PTR_ERR(simd); + if (IS_ERR(simd)) + goto unregister_simds; + + aesbs_simd_algs[i] = simd; + } + + return 0; + +unregister_simds: + aesbs_mod_exit(); + return err; } module_init(aesbs_mod_init); diff --git a/arch/arm/crypto/crc32-ce-core.S b/arch/arm/crypto/crc32-ce-core.S new file mode 100644 index 000000000000..e63d400dc5c1 --- /dev/null +++ b/arch/arm/crypto/crc32-ce-core.S @@ -0,0 +1,306 @@ +/* + * Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions instructions + * + * Copyright (C) 2016 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* GPL HEADER START + * + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 only, + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 for more details (a copy is included + * in the LICENSE file that accompanied this code). + * + * You should have received a copy of the GNU General Public License + * version 2 along with this program; If not, see http://www.gnu.org/licenses + * + * Please visit http://www.xyratex.com/contact if you need additional + * information or have any questions. + * + * GPL HEADER END + */ + +/* + * Copyright 2012 Xyratex Technology Limited + * + * Using hardware provided PCLMULQDQ instruction to accelerate the CRC32 + * calculation. + * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE) + * PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found + * at: + * http://www.intel.com/products/processor/manuals/ + * Intel(R) 64 and IA-32 Architectures Software Developer's Manual + * Volume 2B: Instruction Set Reference, N-Z + * + * Authors: Gregory Prestas + * Alexander Boyko + */ + +#include +#include + + .text + .align 6 + .arch armv8-a + .arch_extension crc + .fpu crypto-neon-fp-armv8 + +.Lcrc32_constants: + /* + * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4 + * #define CONSTANT_R1 0x154442bd4LL + * + * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596 + * #define CONSTANT_R2 0x1c6e41596LL + */ + .quad 0x0000000154442bd4 + .quad 0x00000001c6e41596 + + /* + * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0 + * #define CONSTANT_R3 0x1751997d0LL + * + * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e + * #define CONSTANT_R4 0x0ccaa009eLL + */ + .quad 0x00000001751997d0 + .quad 0x00000000ccaa009e + + /* + * [(x64 mod P(x) << 32)]' << 1 = 0x163cd6124 + * #define CONSTANT_R5 0x163cd6124LL + */ + .quad 0x0000000163cd6124 + .quad 0x00000000FFFFFFFF + + /* + * #define CRCPOLY_TRUE_LE_FULL 0x1DB710641LL + * + * Barrett Reduction constant (u64`) = u` = (x**64 / P(x))` + * = 0x1F7011641LL + * #define CONSTANT_RU 0x1F7011641LL + */ + .quad 0x00000001DB710641 + .quad 0x00000001F7011641 + +.Lcrc32c_constants: + .quad 0x00000000740eef02 + .quad 0x000000009e4addf8 + .quad 0x00000000f20c0dfe + .quad 0x000000014cd00bd6 + .quad 0x00000000dd45aab8 + .quad 0x00000000FFFFFFFF + .quad 0x0000000105ec76f0 + .quad 0x00000000dea713f1 + + dCONSTANTl .req d0 + dCONSTANTh .req d1 + qCONSTANT .req q0 + + BUF .req r0 + LEN .req r1 + CRC .req r2 + + qzr .req q9 + + /** + * Calculate crc32 + * BUF - buffer + * LEN - sizeof buffer (multiple of 16 bytes), LEN should be > 63 + * CRC - initial crc32 + * return %eax crc32 + * uint crc32_pmull_le(unsigned char const *buffer, + * size_t len, uint crc32) + */ +ENTRY(crc32_pmull_le) + adr r3, .Lcrc32_constants + b 0f + +ENTRY(crc32c_pmull_le) + adr r3, .Lcrc32c_constants + +0: bic LEN, LEN, #15 + vld1.8 {q1-q2}, [BUF, :128]! + vld1.8 {q3-q4}, [BUF, :128]! + vmov.i8 qzr, #0 + vmov.i8 qCONSTANT, #0 + vmov dCONSTANTl[0], CRC + veor.8 d2, d2, dCONSTANTl + sub LEN, LEN, #0x40 + cmp LEN, #0x40 + blt less_64 + + vld1.64 {qCONSTANT}, [r3] + +loop_64: /* 64 bytes Full cache line folding */ + sub LEN, LEN, #0x40 + + vmull.p64 q5, d3, dCONSTANTh + vmull.p64 q6, d5, dCONSTANTh + vmull.p64 q7, d7, dCONSTANTh + vmull.p64 q8, d9, dCONSTANTh + + vmull.p64 q1, d2, dCONSTANTl + vmull.p64 q2, d4, dCONSTANTl + vmull.p64 q3, d6, dCONSTANTl + vmull.p64 q4, d8, dCONSTANTl + + veor.8 q1, q1, q5 + vld1.8 {q5}, [BUF, :128]! + veor.8 q2, q2, q6 + vld1.8 {q6}, [BUF, :128]! + veor.8 q3, q3, q7 + vld1.8 {q7}, [BUF, :128]! + veor.8 q4, q4, q8 + vld1.8 {q8}, [BUF, :128]! + + veor.8 q1, q1, q5 + veor.8 q2, q2, q6 + veor.8 q3, q3, q7 + veor.8 q4, q4, q8 + + cmp LEN, #0x40 + bge loop_64 + +less_64: /* Folding cache line into 128bit */ + vldr dCONSTANTl, [r3, #16] + vldr dCONSTANTh, [r3, #24] + + vmull.p64 q5, d3, dCONSTANTh + vmull.p64 q1, d2, dCONSTANTl + veor.8 q1, q1, q5 + veor.8 q1, q1, q2 + + vmull.p64 q5, d3, dCONSTANTh + vmull.p64 q1, d2, dCONSTANTl + veor.8 q1, q1, q5 + veor.8 q1, q1, q3 + + vmull.p64 q5, d3, dCONSTANTh + vmull.p64 q1, d2, dCONSTANTl + veor.8 q1, q1, q5 + veor.8 q1, q1, q4 + + teq LEN, #0 + beq fold_64 + +loop_16: /* Folding rest buffer into 128bit */ + subs LEN, LEN, #0x10 + + vld1.8 {q2}, [BUF, :128]! + vmull.p64 q5, d3, dCONSTANTh + vmull.p64 q1, d2, dCONSTANTl + veor.8 q1, q1, q5 + veor.8 q1, q1, q2 + + bne loop_16 + +fold_64: + /* perform the last 64 bit fold, also adds 32 zeroes + * to the input stream */ + vmull.p64 q2, d2, dCONSTANTh + vext.8 q1, q1, qzr, #8 + veor.8 q1, q1, q2 + + /* final 32-bit fold */ + vldr dCONSTANTl, [r3, #32] + vldr d6, [r3, #40] + vmov.i8 d7, #0 + + vext.8 q2, q1, qzr, #4 + vand.8 d2, d2, d6 + vmull.p64 q1, d2, dCONSTANTl + veor.8 q1, q1, q2 + + /* Finish up with the bit-reversed barrett reduction 64 ==> 32 bits */ + vldr dCONSTANTl, [r3, #48] + vldr dCONSTANTh, [r3, #56] + + vand.8 q2, q1, q3 + vext.8 q2, qzr, q2, #8 + vmull.p64 q2, d5, dCONSTANTh + vand.8 q2, q2, q3 + vmull.p64 q2, d4, dCONSTANTl + veor.8 q1, q1, q2 + vmov r0, s5 + + bx lr +ENDPROC(crc32_pmull_le) +ENDPROC(crc32c_pmull_le) + + .macro __crc32, c + subs ip, r2, #8 + bmi .Ltail\c + + tst r1, #3 + bne .Lunaligned\c + + teq ip, #0 +.Laligned8\c: + ldrd r2, r3, [r1], #8 +ARM_BE8(rev r2, r2 ) +ARM_BE8(rev r3, r3 ) + crc32\c\()w r0, r0, r2 + crc32\c\()w r0, r0, r3 + bxeq lr + subs ip, ip, #8 + bpl .Laligned8\c + +.Ltail\c: + tst ip, #4 + beq 2f + ldr r3, [r1], #4 +ARM_BE8(rev r3, r3 ) + crc32\c\()w r0, r0, r3 + +2: tst ip, #2 + beq 1f + ldrh r3, [r1], #2 +ARM_BE8(rev16 r3, r3 ) + crc32\c\()h r0, r0, r3 + +1: tst ip, #1 + bxeq lr + ldrb r3, [r1] + crc32\c\()b r0, r0, r3 + bx lr + +.Lunaligned\c: + tst r1, #1 + beq 2f + ldrb r3, [r1], #1 + subs r2, r2, #1 + crc32\c\()b r0, r0, r3 + + tst r1, #2 + beq 0f +2: ldrh r3, [r1], #2 + subs r2, r2, #2 +ARM_BE8(rev16 r3, r3 ) + crc32\c\()h r0, r0, r3 + +0: subs ip, r2, #8 + bpl .Laligned8\c + b .Ltail\c + .endm + + .align 5 +ENTRY(crc32_armv8_le) + __crc32 +ENDPROC(crc32_armv8_le) + + .align 5 +ENTRY(crc32c_armv8_le) + __crc32 c +ENDPROC(crc32c_armv8_le) diff --git a/arch/arm/crypto/crc32-ce-glue.c b/arch/arm/crypto/crc32-ce-glue.c new file mode 100644 index 000000000000..e1566bec1016 --- /dev/null +++ b/arch/arm/crypto/crc32-ce-glue.c @@ -0,0 +1,242 @@ +/* + * Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions instructions + * + * Copyright (C) 2016 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define PMULL_MIN_LEN 64L /* minimum size of buffer + * for crc32_pmull_le_16 */ +#define SCALE_F 16L /* size of NEON register */ + +asmlinkage u32 crc32_pmull_le(const u8 buf[], u32 len, u32 init_crc); +asmlinkage u32 crc32_armv8_le(u32 init_crc, const u8 buf[], u32 len); + +asmlinkage u32 crc32c_pmull_le(const u8 buf[], u32 len, u32 init_crc); +asmlinkage u32 crc32c_armv8_le(u32 init_crc, const u8 buf[], u32 len); + +static u32 (*fallback_crc32)(u32 init_crc, const u8 buf[], u32 len); +static u32 (*fallback_crc32c)(u32 init_crc, const u8 buf[], u32 len); + +static int crc32_cra_init(struct crypto_tfm *tfm) +{ + u32 *key = crypto_tfm_ctx(tfm); + + *key = 0; + return 0; +} + +static int crc32c_cra_init(struct crypto_tfm *tfm) +{ + u32 *key = crypto_tfm_ctx(tfm); + + *key = ~0; + return 0; +} + +static int crc32_setkey(struct crypto_shash *hash, const u8 *key, + unsigned int keylen) +{ + u32 *mctx = crypto_shash_ctx(hash); + + if (keylen != sizeof(u32)) { + crypto_shash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + } + *mctx = le32_to_cpup((__le32 *)key); + return 0; +} + +static int crc32_init(struct shash_desc *desc) +{ + u32 *mctx = crypto_shash_ctx(desc->tfm); + u32 *crc = shash_desc_ctx(desc); + + *crc = *mctx; + return 0; +} + +static int crc32_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u32 *crc = shash_desc_ctx(desc); + + *crc = crc32_armv8_le(*crc, data, length); + return 0; +} + +static int crc32c_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u32 *crc = shash_desc_ctx(desc); + + *crc = crc32c_armv8_le(*crc, data, length); + return 0; +} + +static int crc32_final(struct shash_desc *desc, u8 *out) +{ + u32 *crc = shash_desc_ctx(desc); + + put_unaligned_le32(*crc, out); + return 0; +} + +static int crc32c_final(struct shash_desc *desc, u8 *out) +{ + u32 *crc = shash_desc_ctx(desc); + + put_unaligned_le32(~*crc, out); + return 0; +} + +static int crc32_pmull_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u32 *crc = shash_desc_ctx(desc); + unsigned int l; + + if (may_use_simd()) { + if ((u32)data % SCALE_F) { + l = min_t(u32, length, SCALE_F - ((u32)data % SCALE_F)); + + *crc = fallback_crc32(*crc, data, l); + + data += l; + length -= l; + } + + if (length >= PMULL_MIN_LEN) { + l = round_down(length, SCALE_F); + + kernel_neon_begin(); + *crc = crc32_pmull_le(data, l, *crc); + kernel_neon_end(); + + data += l; + length -= l; + } + } + + if (length > 0) + *crc = fallback_crc32(*crc, data, length); + + return 0; +} + +static int crc32c_pmull_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u32 *crc = shash_desc_ctx(desc); + unsigned int l; + + if (may_use_simd()) { + if ((u32)data % SCALE_F) { + l = min_t(u32, length, SCALE_F - ((u32)data % SCALE_F)); + + *crc = fallback_crc32c(*crc, data, l); + + data += l; + length -= l; + } + + if (length >= PMULL_MIN_LEN) { + l = round_down(length, SCALE_F); + + kernel_neon_begin(); + *crc = crc32c_pmull_le(data, l, *crc); + kernel_neon_end(); + + data += l; + length -= l; + } + } + + if (length > 0) + *crc = fallback_crc32c(*crc, data, length); + + return 0; +} + +static struct shash_alg crc32_pmull_algs[] = { { + .setkey = crc32_setkey, + .init = crc32_init, + .update = crc32_update, + .final = crc32_final, + .descsize = sizeof(u32), + .digestsize = sizeof(u32), + + .base.cra_ctxsize = sizeof(u32), + .base.cra_init = crc32_cra_init, + .base.cra_name = "crc32", + .base.cra_driver_name = "crc32-arm-ce", + .base.cra_priority = 200, + .base.cra_blocksize = 1, + .base.cra_module = THIS_MODULE, +}, { + .setkey = crc32_setkey, + .init = crc32_init, + .update = crc32c_update, + .final = crc32c_final, + .descsize = sizeof(u32), + .digestsize = sizeof(u32), + + .base.cra_ctxsize = sizeof(u32), + .base.cra_init = crc32c_cra_init, + .base.cra_name = "crc32c", + .base.cra_driver_name = "crc32c-arm-ce", + .base.cra_priority = 200, + .base.cra_blocksize = 1, + .base.cra_module = THIS_MODULE, +} }; + +static int __init crc32_pmull_mod_init(void) +{ + if (elf_hwcap2 & HWCAP2_PMULL) { + crc32_pmull_algs[0].update = crc32_pmull_update; + crc32_pmull_algs[1].update = crc32c_pmull_update; + + if (elf_hwcap2 & HWCAP2_CRC32) { + fallback_crc32 = crc32_armv8_le; + fallback_crc32c = crc32c_armv8_le; + } else { + fallback_crc32 = crc32_le; + fallback_crc32c = __crc32c_le; + } + } else if (!(elf_hwcap2 & HWCAP2_CRC32)) { + return -ENODEV; + } + + return crypto_register_shashes(crc32_pmull_algs, + ARRAY_SIZE(crc32_pmull_algs)); +} + +static void __exit crc32_pmull_mod_exit(void) +{ + crypto_unregister_shashes(crc32_pmull_algs, + ARRAY_SIZE(crc32_pmull_algs)); +} + +module_init(crc32_pmull_mod_init); +module_exit(crc32_pmull_mod_exit); + +MODULE_AUTHOR("Ard Biesheuvel "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS_CRYPTO("crc32"); +MODULE_ALIAS_CRYPTO("crc32c"); diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/crypto/crct10dif-ce-core.S new file mode 100644 index 000000000000..ce45ba0c0687 --- /dev/null +++ b/arch/arm/crypto/crct10dif-ce-core.S @@ -0,0 +1,427 @@ +// +// Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions +// +// Copyright (C) 2016 Linaro Ltd +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation. +// + +// +// Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions +// +// Copyright (c) 2013, Intel Corporation +// +// Authors: +// Erdinc Ozturk +// Vinodh Gopal +// James Guilford +// Tim Chen +// +// This software is available to you under a choice of one of two +// licenses. You may choose to be licensed under the terms of the GNU +// General Public License (GPL) Version 2, available from the file +// COPYING in the main directory of this source tree, or the +// OpenIB.org BSD license below: +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// * Neither the name of the Intel Corporation nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// +// THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY +// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Function API: +// UINT16 crc_t10dif_pcl( +// UINT16 init_crc, //initial CRC value, 16 bits +// const unsigned char *buf, //buffer pointer to calculate CRC on +// UINT64 len //buffer length in bytes (64-bit data) +// ); +// +// Reference paper titled "Fast CRC Computation for Generic +// Polynomials Using PCLMULQDQ Instruction" +// URL: http://www.intel.com/content/dam/www/public/us/en/documents +// /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf +// +// + +#include +#include + +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define CPU_LE(code...) +#else +#define CPU_LE(code...) code +#endif + + .text + .fpu crypto-neon-fp-armv8 + + arg1_low32 .req r0 + arg2 .req r1 + arg3 .req r2 + + qzr .req q13 + + q0l .req d0 + q0h .req d1 + q1l .req d2 + q1h .req d3 + q2l .req d4 + q2h .req d5 + q3l .req d6 + q3h .req d7 + q4l .req d8 + q4h .req d9 + q5l .req d10 + q5h .req d11 + q6l .req d12 + q6h .req d13 + q7l .req d14 + q7h .req d15 + +ENTRY(crc_t10dif_pmull) + vmov.i8 qzr, #0 // init zero register + + // adjust the 16-bit initial_crc value, scale it to 32 bits + lsl arg1_low32, arg1_low32, #16 + + // check if smaller than 256 + cmp arg3, #256 + + // for sizes less than 128, we can't fold 64B at a time... + blt _less_than_128 + + // load the initial crc value + // crc value does not need to be byte-reflected, but it needs + // to be moved to the high part of the register. + // because data will be byte-reflected and will align with + // initial crc at correct place. + vmov s0, arg1_low32 // initial crc + vext.8 q10, qzr, q0, #4 + + // receive the initial 64B data, xor the initial crc value + vld1.64 {q0-q1}, [arg2, :128]! + vld1.64 {q2-q3}, [arg2, :128]! + vld1.64 {q4-q5}, [arg2, :128]! + vld1.64 {q6-q7}, [arg2, :128]! +CPU_LE( vrev64.8 q0, q0 ) +CPU_LE( vrev64.8 q1, q1 ) +CPU_LE( vrev64.8 q2, q2 ) +CPU_LE( vrev64.8 q3, q3 ) +CPU_LE( vrev64.8 q4, q4 ) +CPU_LE( vrev64.8 q5, q5 ) +CPU_LE( vrev64.8 q6, q6 ) +CPU_LE( vrev64.8 q7, q7 ) + + vswp d0, d1 + vswp d2, d3 + vswp d4, d5 + vswp d6, d7 + vswp d8, d9 + vswp d10, d11 + vswp d12, d13 + vswp d14, d15 + + // XOR the initial_crc value + veor.8 q0, q0, q10 + + adr ip, rk3 + vld1.64 {q10}, [ip, :128] // xmm10 has rk3 and rk4 + + // + // we subtract 256 instead of 128 to save one instruction from the loop + // + sub arg3, arg3, #256 + + // at this section of the code, there is 64*x+y (0<=y<64) bytes of + // buffer. The _fold_64_B_loop will fold 64B at a time + // until we have 64+y Bytes of buffer + + + // fold 64B at a time. This section of the code folds 4 vector + // registers in parallel +_fold_64_B_loop: + + .macro fold64, reg1, reg2 + vld1.64 {q11-q12}, [arg2, :128]! + + vmull.p64 q8, \reg1\()h, d21 + vmull.p64 \reg1, \reg1\()l, d20 + vmull.p64 q9, \reg2\()h, d21 + vmull.p64 \reg2, \reg2\()l, d20 + +CPU_LE( vrev64.8 q11, q11 ) +CPU_LE( vrev64.8 q12, q12 ) + vswp d22, d23 + vswp d24, d25 + + veor.8 \reg1, \reg1, q8 + veor.8 \reg2, \reg2, q9 + veor.8 \reg1, \reg1, q11 + veor.8 \reg2, \reg2, q12 + .endm + + fold64 q0, q1 + fold64 q2, q3 + fold64 q4, q5 + fold64 q6, q7 + + subs arg3, arg3, #128 + + // check if there is another 64B in the buffer to be able to fold + bge _fold_64_B_loop + + // at this point, the buffer pointer is pointing at the last y Bytes + // of the buffer the 64B of folded data is in 4 of the vector + // registers: v0, v1, v2, v3 + + // fold the 8 vector registers to 1 vector register with different + // constants + + adr ip, rk9 + vld1.64 {q10}, [ip, :128]! + + .macro fold16, reg, rk + vmull.p64 q8, \reg\()l, d20 + vmull.p64 \reg, \reg\()h, d21 + .ifnb \rk + vld1.64 {q10}, [ip, :128]! + .endif + veor.8 q7, q7, q8 + veor.8 q7, q7, \reg + .endm + + fold16 q0, rk11 + fold16 q1, rk13 + fold16 q2, rk15 + fold16 q3, rk17 + fold16 q4, rk19 + fold16 q5, rk1 + fold16 q6 + + // instead of 64, we add 48 to the loop counter to save 1 instruction + // from the loop instead of a cmp instruction, we use the negative + // flag with the jl instruction + adds arg3, arg3, #(128-16) + blt _final_reduction_for_128 + + // now we have 16+y bytes left to reduce. 16 Bytes is in register v7 + // and the rest is in memory. We can fold 16 bytes at a time if y>=16 + // continue folding 16B at a time + +_16B_reduction_loop: + vmull.p64 q8, d14, d20 + vmull.p64 q7, d15, d21 + veor.8 q7, q7, q8 + + vld1.64 {q0}, [arg2, :128]! +CPU_LE( vrev64.8 q0, q0 ) + vswp d0, d1 + veor.8 q7, q7, q0 + subs arg3, arg3, #16 + + // instead of a cmp instruction, we utilize the flags with the + // jge instruction equivalent of: cmp arg3, 16-16 + // check if there is any more 16B in the buffer to be able to fold + bge _16B_reduction_loop + + // now we have 16+z bytes left to reduce, where 0<= z < 16. + // first, we reduce the data in the xmm7 register + +_final_reduction_for_128: + // check if any more data to fold. If not, compute the CRC of + // the final 128 bits + adds arg3, arg3, #16 + beq _128_done + + // here we are getting data that is less than 16 bytes. + // since we know that there was data before the pointer, we can + // offset the input pointer before the actual point, to receive + // exactly 16 bytes. after that the registers need to be adjusted. +_get_last_two_regs: + add arg2, arg2, arg3 + sub arg2, arg2, #16 + vld1.64 {q1}, [arg2] +CPU_LE( vrev64.8 q1, q1 ) + vswp d2, d3 + + // get rid of the extra data that was loaded before + // load the shift constant + adr ip, tbl_shf_table + 16 + sub ip, ip, arg3 + vld1.8 {q0}, [ip] + + // shift v2 to the left by arg3 bytes + vtbl.8 d4, {d14-d15}, d0 + vtbl.8 d5, {d14-d15}, d1 + + // shift v7 to the right by 16-arg3 bytes + vmov.i8 q9, #0x80 + veor.8 q0, q0, q9 + vtbl.8 d18, {d14-d15}, d0 + vtbl.8 d19, {d14-d15}, d1 + + // blend + vshr.s8 q0, q0, #7 // convert to 8-bit mask + vbsl.8 q0, q2, q1 + + // fold 16 Bytes + vmull.p64 q8, d18, d20 + vmull.p64 q7, d19, d21 + veor.8 q7, q7, q8 + veor.8 q7, q7, q0 + +_128_done: + // compute crc of a 128-bit value + vldr d20, rk5 + vldr d21, rk6 // rk5 and rk6 in xmm10 + + // 64b fold + vext.8 q0, qzr, q7, #8 + vmull.p64 q7, d15, d20 + veor.8 q7, q7, q0 + + // 32b fold + vext.8 q0, q7, qzr, #12 + vmov s31, s3 + vmull.p64 q0, d0, d21 + veor.8 q7, q0, q7 + + // barrett reduction +_barrett: + vldr d20, rk7 + vldr d21, rk8 + + vmull.p64 q0, d15, d20 + vext.8 q0, qzr, q0, #12 + vmull.p64 q0, d1, d21 + vext.8 q0, qzr, q0, #12 + veor.8 q7, q7, q0 + vmov r0, s29 + +_cleanup: + // scale the result back to 16 bits + lsr r0, r0, #16 + bx lr + +_less_than_128: + teq arg3, #0 + beq _cleanup + + vmov.i8 q0, #0 + vmov s3, arg1_low32 // get the initial crc value + + vld1.64 {q7}, [arg2, :128]! +CPU_LE( vrev64.8 q7, q7 ) + vswp d14, d15 + veor.8 q7, q7, q0 + + cmp arg3, #16 + beq _128_done // exactly 16 left + blt _less_than_16_left + + // now if there is, load the constants + vldr d20, rk1 + vldr d21, rk2 // rk1 and rk2 in xmm10 + + // check if there is enough buffer to be able to fold 16B at a time + subs arg3, arg3, #32 + addlt arg3, arg3, #16 + blt _get_last_two_regs + b _16B_reduction_loop + +_less_than_16_left: + // shl r9, 4 + adr ip, tbl_shf_table + 16 + sub ip, ip, arg3 + vld1.8 {q0}, [ip] + vmov.i8 q9, #0x80 + veor.8 q0, q0, q9 + vtbl.8 d18, {d14-d15}, d0 + vtbl.8 d15, {d14-d15}, d1 + vmov d14, d18 + b _128_done +ENDPROC(crc_t10dif_pmull) + +// precomputed constants +// these constants are precomputed from the poly: +// 0x8bb70000 (0x8bb7 scaled to 32 bits) + .align 4 +// Q = 0x18BB70000 +// rk1 = 2^(32*3) mod Q << 32 +// rk2 = 2^(32*5) mod Q << 32 +// rk3 = 2^(32*15) mod Q << 32 +// rk4 = 2^(32*17) mod Q << 32 +// rk5 = 2^(32*3) mod Q << 32 +// rk6 = 2^(32*2) mod Q << 32 +// rk7 = floor(2^64/Q) +// rk8 = Q + +rk3: .quad 0x9d9d000000000000 +rk4: .quad 0x7cf5000000000000 +rk5: .quad 0x2d56000000000000 +rk6: .quad 0x1368000000000000 +rk7: .quad 0x00000001f65a57f8 +rk8: .quad 0x000000018bb70000 +rk9: .quad 0xceae000000000000 +rk10: .quad 0xbfd6000000000000 +rk11: .quad 0x1e16000000000000 +rk12: .quad 0x713c000000000000 +rk13: .quad 0xf7f9000000000000 +rk14: .quad 0x80a6000000000000 +rk15: .quad 0x044c000000000000 +rk16: .quad 0xe658000000000000 +rk17: .quad 0xad18000000000000 +rk18: .quad 0xa497000000000000 +rk19: .quad 0x6ee3000000000000 +rk20: .quad 0xe7b5000000000000 +rk1: .quad 0x2d56000000000000 +rk2: .quad 0x06df000000000000 + +tbl_shf_table: +// use these values for shift constants for the tbl/tbx instruction +// different alignments result in values as shown: +// DDQ 0x008f8e8d8c8b8a898887868584838281 # shl 15 (16-1) / shr1 +// DDQ 0x01008f8e8d8c8b8a8988878685848382 # shl 14 (16-3) / shr2 +// DDQ 0x0201008f8e8d8c8b8a89888786858483 # shl 13 (16-4) / shr3 +// DDQ 0x030201008f8e8d8c8b8a898887868584 # shl 12 (16-4) / shr4 +// DDQ 0x04030201008f8e8d8c8b8a8988878685 # shl 11 (16-5) / shr5 +// DDQ 0x0504030201008f8e8d8c8b8a89888786 # shl 10 (16-6) / shr6 +// DDQ 0x060504030201008f8e8d8c8b8a898887 # shl 9 (16-7) / shr7 +// DDQ 0x07060504030201008f8e8d8c8b8a8988 # shl 8 (16-8) / shr8 +// DDQ 0x0807060504030201008f8e8d8c8b8a89 # shl 7 (16-9) / shr9 +// DDQ 0x090807060504030201008f8e8d8c8b8a # shl 6 (16-10) / shr10 +// DDQ 0x0a090807060504030201008f8e8d8c8b # shl 5 (16-11) / shr11 +// DDQ 0x0b0a090807060504030201008f8e8d8c # shl 4 (16-12) / shr12 +// DDQ 0x0c0b0a090807060504030201008f8e8d # shl 3 (16-13) / shr13 +// DDQ 0x0d0c0b0a090807060504030201008f8e # shl 2 (16-14) / shr14 +// DDQ 0x0e0d0c0b0a090807060504030201008f # shl 1 (16-15) / shr15 + + .byte 0x0, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87 + .byte 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f + .byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 + .byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe , 0x0 diff --git a/arch/arm/crypto/crct10dif-ce-glue.c b/arch/arm/crypto/crct10dif-ce-glue.c new file mode 100644 index 000000000000..d428355cf38d --- /dev/null +++ b/arch/arm/crypto/crct10dif-ce-glue.c @@ -0,0 +1,101 @@ +/* + * Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions + * + * Copyright (C) 2016 Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#define CRC_T10DIF_PMULL_CHUNK_SIZE 16U + +asmlinkage u16 crc_t10dif_pmull(u16 init_crc, const u8 buf[], u32 len); + +static int crct10dif_init(struct shash_desc *desc) +{ + u16 *crc = shash_desc_ctx(desc); + + *crc = 0; + return 0; +} + +static int crct10dif_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + u16 *crc = shash_desc_ctx(desc); + unsigned int l; + + if (!may_use_simd()) { + *crc = crc_t10dif_generic(*crc, data, length); + } else { + if (unlikely((u32)data % CRC_T10DIF_PMULL_CHUNK_SIZE)) { + l = min_t(u32, length, CRC_T10DIF_PMULL_CHUNK_SIZE - + ((u32)data % CRC_T10DIF_PMULL_CHUNK_SIZE)); + + *crc = crc_t10dif_generic(*crc, data, l); + + length -= l; + data += l; + } + if (length > 0) { + kernel_neon_begin(); + *crc = crc_t10dif_pmull(*crc, data, length); + kernel_neon_end(); + } + } + return 0; +} + +static int crct10dif_final(struct shash_desc *desc, u8 *out) +{ + u16 *crc = shash_desc_ctx(desc); + + *(u16 *)out = *crc; + return 0; +} + +static struct shash_alg crc_t10dif_alg = { + .digestsize = CRC_T10DIF_DIGEST_SIZE, + .init = crct10dif_init, + .update = crct10dif_update, + .final = crct10dif_final, + .descsize = CRC_T10DIF_DIGEST_SIZE, + + .base.cra_name = "crct10dif", + .base.cra_driver_name = "crct10dif-arm-ce", + .base.cra_priority = 200, + .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, + .base.cra_module = THIS_MODULE, +}; + +static int __init crc_t10dif_mod_init(void) +{ + if (!(elf_hwcap2 & HWCAP2_PMULL)) + return -ENODEV; + + return crypto_register_shash(&crc_t10dif_alg); +} + +static void __exit crc_t10dif_mod_exit(void) +{ + crypto_unregister_shash(&crc_t10dif_alg); +} + +module_init(crc_t10dif_mod_init); +module_exit(crc_t10dif_mod_exit); + +MODULE_AUTHOR("Ard Biesheuvel "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS_CRYPTO("crct10dif"); diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 55e0e3ea9cb6..efb21757d41f 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -38,3 +38,6 @@ generic-y += termios.h generic-y += timex.h generic-y += trace_clock.h generic-y += unaligned.h + +generated-y += mach-types.h +generated-y += unistd-nr.h diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 522b5feb4eaa..b62eaeb147aa 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -94,6 +94,9 @@ #define ARM_CPU_XSCALE_ARCH_V2 0x4000 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 +/* Qualcomm implemented cores */ +#define ARM_CPU_PART_SCORPION 0x510002d0 + extern unsigned int processor_id; #ifdef CONFIG_CPU_CP15 diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h index b1ce037e4380..e986b7f717c4 100644 --- a/arch/arm/include/asm/delay.h +++ b/arch/arm/include/asm/delay.h @@ -9,6 +9,33 @@ #include #include /* HZ */ +/* + * Loop (or tick) based delay: + * + * loops = loops_per_jiffy * jiffies_per_sec * delay_us / us_per_sec + * + * where: + * + * jiffies_per_sec = HZ + * us_per_sec = 1000000 + * + * Therefore the constant part is HZ / 1000000 which is a small + * fractional number. To make this usable with integer math, we + * scale up this constant by 2^31, perform the actual multiplication, + * and scale the result back down by 2^31 with a simple shift: + * + * loops = (loops_per_jiffy * delay_us * UDELAY_MULT) >> 31 + * + * where: + * + * UDELAY_MULT = 2^31 * HZ / 1000000 + * = (2^31 / 1000000) * HZ + * = 2147.483648 * HZ + * = 2147 * HZ + 483648 * HZ / 1000000 + * + * 31 is the biggest scale shift value that won't overflow 32 bits for + * delay_us * UDELAY_MULT assuming HZ <= 1000 and delay_us <= 2000. + */ #define MAX_UDELAY_MS 2 #define UDELAY_MULT UL(2147 * HZ + 483648 * HZ / 1000000) #define UDELAY_SHIFT 31 diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index bfe2a2f5a644..22b73112b75f 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -54,6 +54,24 @@ static inline void *return_address(unsigned int level) #define ftrace_return_address(n) return_address(n) +#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME + +static inline bool arch_syscall_match_sym_name(const char *sym, + const char *name) +{ + if (!strcmp(sym, "sys_mmap2")) + sym = "sys_mmap_pgoff"; + else if (!strcmp(sym, "sys_statfs64_wrapper")) + sym = "sys_statfs64"; + else if (!strcmp(sym, "sys_fstatfs64_wrapper")) + sym = "sys_fstatfs64"; + else if (!strcmp(sym, "sys_arm_fadvise64_64")) + sym = "sys_fadvise64_64"; + + /* Ignore case since sym may start with "SyS" instead of "sys" */ + return !strcasecmp(sym, name); +} + #endif /* ifndef __ASSEMBLY__ */ #endif /* _ASM_ARM_FTRACE */ diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h deleted file mode 100644 index 948178cc6ba8..000000000000 --- a/arch/arm/include/asm/mach-types.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index ada0d29a660f..076090d2dbf5 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -14,12 +14,7 @@ #define __ASM_ARM_UNISTD_H #include - -/* - * This may need to be greater than __NR_last_syscall+1 in order to - * account for the padding in the syscall table - */ -#define __NR_syscalls (400) +#include #define __ARCH_WANT_STAT64 #define __ARCH_WANT_SYS_GETHOSTNAME @@ -52,4 +47,23 @@ #define __IGNORE_fadvise64_64 #define __IGNORE_migrate_pages +#ifdef __ARM_EABI__ +/* + * The following syscalls are obsolete and no longer available for EABI: + * __NR_time + * __NR_umount + * __NR_stime + * __NR_alarm + * __NR_utime + * __NR_getrlimit + * __NR_select + * __NR_readdir + * __NR_mmap + * __NR_socketcall + * __NR_syscall + * __NR_ipc + */ +#define __IGNORE_getrlimit +#endif + #endif /* __ASM_ARM_UNISTD_H */ diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index a1c05f93d920..46a76cd6acb6 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -18,3 +18,6 @@ header-y += stat.h header-y += statfs.h header-y += swab.h header-y += unistd.h +genhdr-y += unistd-common.h +genhdr-y += unistd-oabi.h +genhdr-y += unistd-eabi.h diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/uapi/asm/types.h similarity index 94% rename from arch/arm/include/asm/types.h rename to arch/arm/include/uapi/asm/types.h index a53cdb8f068c..9435a42f575e 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/uapi/asm/types.h @@ -1,5 +1,5 @@ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H +#ifndef _UAPI_ASM_TYPES_H +#define _UAPI_ASM_TYPES_H #include @@ -37,4 +37,4 @@ #define __UINTPTR_TYPE__ unsigned long #endif -#endif /* _ASM_TYPES_H */ +#endif /* _UAPI_ASM_TYPES_H */ diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h index 314100a06ccb..28bd456494a3 100644 --- a/arch/arm/include/uapi/asm/unistd.h +++ b/arch/arm/include/uapi/asm/unistd.h @@ -17,412 +17,14 @@ #if defined(__thumb__) || defined(__ARM_EABI__) #define __NR_SYSCALL_BASE 0 +#include #else #define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE +#include #endif -/* - * This file contains the system call numbers. - */ - -#define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) -#define __NR_exit (__NR_SYSCALL_BASE+ 1) -#define __NR_fork (__NR_SYSCALL_BASE+ 2) -#define __NR_read (__NR_SYSCALL_BASE+ 3) -#define __NR_write (__NR_SYSCALL_BASE+ 4) -#define __NR_open (__NR_SYSCALL_BASE+ 5) -#define __NR_close (__NR_SYSCALL_BASE+ 6) - /* 7 was sys_waitpid */ -#define __NR_creat (__NR_SYSCALL_BASE+ 8) -#define __NR_link (__NR_SYSCALL_BASE+ 9) -#define __NR_unlink (__NR_SYSCALL_BASE+ 10) -#define __NR_execve (__NR_SYSCALL_BASE+ 11) -#define __NR_chdir (__NR_SYSCALL_BASE+ 12) -#define __NR_time (__NR_SYSCALL_BASE+ 13) -#define __NR_mknod (__NR_SYSCALL_BASE+ 14) -#define __NR_chmod (__NR_SYSCALL_BASE+ 15) -#define __NR_lchown (__NR_SYSCALL_BASE+ 16) - /* 17 was sys_break */ - /* 18 was sys_stat */ -#define __NR_lseek (__NR_SYSCALL_BASE+ 19) -#define __NR_getpid (__NR_SYSCALL_BASE+ 20) -#define __NR_mount (__NR_SYSCALL_BASE+ 21) -#define __NR_umount (__NR_SYSCALL_BASE+ 22) -#define __NR_setuid (__NR_SYSCALL_BASE+ 23) -#define __NR_getuid (__NR_SYSCALL_BASE+ 24) -#define __NR_stime (__NR_SYSCALL_BASE+ 25) -#define __NR_ptrace (__NR_SYSCALL_BASE+ 26) -#define __NR_alarm (__NR_SYSCALL_BASE+ 27) - /* 28 was sys_fstat */ -#define __NR_pause (__NR_SYSCALL_BASE+ 29) -#define __NR_utime (__NR_SYSCALL_BASE+ 30) - /* 31 was sys_stty */ - /* 32 was sys_gtty */ -#define __NR_access (__NR_SYSCALL_BASE+ 33) -#define __NR_nice (__NR_SYSCALL_BASE+ 34) - /* 35 was sys_ftime */ -#define __NR_sync (__NR_SYSCALL_BASE+ 36) -#define __NR_kill (__NR_SYSCALL_BASE+ 37) -#define __NR_rename (__NR_SYSCALL_BASE+ 38) -#define __NR_mkdir (__NR_SYSCALL_BASE+ 39) -#define __NR_rmdir (__NR_SYSCALL_BASE+ 40) -#define __NR_dup (__NR_SYSCALL_BASE+ 41) -#define __NR_pipe (__NR_SYSCALL_BASE+ 42) -#define __NR_times (__NR_SYSCALL_BASE+ 43) - /* 44 was sys_prof */ -#define __NR_brk (__NR_SYSCALL_BASE+ 45) -#define __NR_setgid (__NR_SYSCALL_BASE+ 46) -#define __NR_getgid (__NR_SYSCALL_BASE+ 47) - /* 48 was sys_signal */ -#define __NR_geteuid (__NR_SYSCALL_BASE+ 49) -#define __NR_getegid (__NR_SYSCALL_BASE+ 50) -#define __NR_acct (__NR_SYSCALL_BASE+ 51) -#define __NR_umount2 (__NR_SYSCALL_BASE+ 52) - /* 53 was sys_lock */ -#define __NR_ioctl (__NR_SYSCALL_BASE+ 54) -#define __NR_fcntl (__NR_SYSCALL_BASE+ 55) - /* 56 was sys_mpx */ -#define __NR_setpgid (__NR_SYSCALL_BASE+ 57) - /* 58 was sys_ulimit */ - /* 59 was sys_olduname */ -#define __NR_umask (__NR_SYSCALL_BASE+ 60) -#define __NR_chroot (__NR_SYSCALL_BASE+ 61) -#define __NR_ustat (__NR_SYSCALL_BASE+ 62) -#define __NR_dup2 (__NR_SYSCALL_BASE+ 63) -#define __NR_getppid (__NR_SYSCALL_BASE+ 64) -#define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) -#define __NR_setsid (__NR_SYSCALL_BASE+ 66) -#define __NR_sigaction (__NR_SYSCALL_BASE+ 67) - /* 68 was sys_sgetmask */ - /* 69 was sys_ssetmask */ -#define __NR_setreuid (__NR_SYSCALL_BASE+ 70) -#define __NR_setregid (__NR_SYSCALL_BASE+ 71) -#define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) -#define __NR_sigpending (__NR_SYSCALL_BASE+ 73) -#define __NR_sethostname (__NR_SYSCALL_BASE+ 74) -#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) -#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ -#define __NR_getrusage (__NR_SYSCALL_BASE+ 77) -#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) -#define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) -#define __NR_getgroups (__NR_SYSCALL_BASE+ 80) -#define __NR_setgroups (__NR_SYSCALL_BASE+ 81) -#define __NR_select (__NR_SYSCALL_BASE+ 82) -#define __NR_symlink (__NR_SYSCALL_BASE+ 83) - /* 84 was sys_lstat */ -#define __NR_readlink (__NR_SYSCALL_BASE+ 85) -#define __NR_uselib (__NR_SYSCALL_BASE+ 86) -#define __NR_swapon (__NR_SYSCALL_BASE+ 87) -#define __NR_reboot (__NR_SYSCALL_BASE+ 88) -#define __NR_readdir (__NR_SYSCALL_BASE+ 89) -#define __NR_mmap (__NR_SYSCALL_BASE+ 90) -#define __NR_munmap (__NR_SYSCALL_BASE+ 91) -#define __NR_truncate (__NR_SYSCALL_BASE+ 92) -#define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) -#define __NR_fchmod (__NR_SYSCALL_BASE+ 94) -#define __NR_fchown (__NR_SYSCALL_BASE+ 95) -#define __NR_getpriority (__NR_SYSCALL_BASE+ 96) -#define __NR_setpriority (__NR_SYSCALL_BASE+ 97) - /* 98 was sys_profil */ -#define __NR_statfs (__NR_SYSCALL_BASE+ 99) -#define __NR_fstatfs (__NR_SYSCALL_BASE+100) - /* 101 was sys_ioperm */ -#define __NR_socketcall (__NR_SYSCALL_BASE+102) -#define __NR_syslog (__NR_SYSCALL_BASE+103) -#define __NR_setitimer (__NR_SYSCALL_BASE+104) -#define __NR_getitimer (__NR_SYSCALL_BASE+105) -#define __NR_stat (__NR_SYSCALL_BASE+106) -#define __NR_lstat (__NR_SYSCALL_BASE+107) -#define __NR_fstat (__NR_SYSCALL_BASE+108) - /* 109 was sys_uname */ - /* 110 was sys_iopl */ -#define __NR_vhangup (__NR_SYSCALL_BASE+111) - /* 112 was sys_idle */ -#define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ -#define __NR_wait4 (__NR_SYSCALL_BASE+114) -#define __NR_swapoff (__NR_SYSCALL_BASE+115) -#define __NR_sysinfo (__NR_SYSCALL_BASE+116) -#define __NR_ipc (__NR_SYSCALL_BASE+117) -#define __NR_fsync (__NR_SYSCALL_BASE+118) -#define __NR_sigreturn (__NR_SYSCALL_BASE+119) -#define __NR_clone (__NR_SYSCALL_BASE+120) -#define __NR_setdomainname (__NR_SYSCALL_BASE+121) -#define __NR_uname (__NR_SYSCALL_BASE+122) - /* 123 was sys_modify_ldt */ -#define __NR_adjtimex (__NR_SYSCALL_BASE+124) -#define __NR_mprotect (__NR_SYSCALL_BASE+125) -#define __NR_sigprocmask (__NR_SYSCALL_BASE+126) - /* 127 was sys_create_module */ -#define __NR_init_module (__NR_SYSCALL_BASE+128) -#define __NR_delete_module (__NR_SYSCALL_BASE+129) - /* 130 was sys_get_kernel_syms */ -#define __NR_quotactl (__NR_SYSCALL_BASE+131) -#define __NR_getpgid (__NR_SYSCALL_BASE+132) -#define __NR_fchdir (__NR_SYSCALL_BASE+133) -#define __NR_bdflush (__NR_SYSCALL_BASE+134) -#define __NR_sysfs (__NR_SYSCALL_BASE+135) -#define __NR_personality (__NR_SYSCALL_BASE+136) - /* 137 was sys_afs_syscall */ -#define __NR_setfsuid (__NR_SYSCALL_BASE+138) -#define __NR_setfsgid (__NR_SYSCALL_BASE+139) -#define __NR__llseek (__NR_SYSCALL_BASE+140) -#define __NR_getdents (__NR_SYSCALL_BASE+141) -#define __NR__newselect (__NR_SYSCALL_BASE+142) -#define __NR_flock (__NR_SYSCALL_BASE+143) -#define __NR_msync (__NR_SYSCALL_BASE+144) -#define __NR_readv (__NR_SYSCALL_BASE+145) -#define __NR_writev (__NR_SYSCALL_BASE+146) -#define __NR_getsid (__NR_SYSCALL_BASE+147) -#define __NR_fdatasync (__NR_SYSCALL_BASE+148) -#define __NR__sysctl (__NR_SYSCALL_BASE+149) -#define __NR_mlock (__NR_SYSCALL_BASE+150) -#define __NR_munlock (__NR_SYSCALL_BASE+151) -#define __NR_mlockall (__NR_SYSCALL_BASE+152) -#define __NR_munlockall (__NR_SYSCALL_BASE+153) -#define __NR_sched_setparam (__NR_SYSCALL_BASE+154) -#define __NR_sched_getparam (__NR_SYSCALL_BASE+155) -#define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) -#define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) -#define __NR_sched_yield (__NR_SYSCALL_BASE+158) -#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) -#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) -#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) -#define __NR_nanosleep (__NR_SYSCALL_BASE+162) -#define __NR_mremap (__NR_SYSCALL_BASE+163) -#define __NR_setresuid (__NR_SYSCALL_BASE+164) -#define __NR_getresuid (__NR_SYSCALL_BASE+165) - /* 166 was sys_vm86 */ - /* 167 was sys_query_module */ -#define __NR_poll (__NR_SYSCALL_BASE+168) -#define __NR_nfsservctl (__NR_SYSCALL_BASE+169) -#define __NR_setresgid (__NR_SYSCALL_BASE+170) -#define __NR_getresgid (__NR_SYSCALL_BASE+171) -#define __NR_prctl (__NR_SYSCALL_BASE+172) -#define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) -#define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) -#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) -#define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) -#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) -#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) -#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) -#define __NR_pread64 (__NR_SYSCALL_BASE+180) -#define __NR_pwrite64 (__NR_SYSCALL_BASE+181) -#define __NR_chown (__NR_SYSCALL_BASE+182) -#define __NR_getcwd (__NR_SYSCALL_BASE+183) -#define __NR_capget (__NR_SYSCALL_BASE+184) -#define __NR_capset (__NR_SYSCALL_BASE+185) -#define __NR_sigaltstack (__NR_SYSCALL_BASE+186) -#define __NR_sendfile (__NR_SYSCALL_BASE+187) - /* 188 reserved */ - /* 189 reserved */ -#define __NR_vfork (__NR_SYSCALL_BASE+190) -#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ -#define __NR_mmap2 (__NR_SYSCALL_BASE+192) -#define __NR_truncate64 (__NR_SYSCALL_BASE+193) -#define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) -#define __NR_stat64 (__NR_SYSCALL_BASE+195) -#define __NR_lstat64 (__NR_SYSCALL_BASE+196) -#define __NR_fstat64 (__NR_SYSCALL_BASE+197) -#define __NR_lchown32 (__NR_SYSCALL_BASE+198) -#define __NR_getuid32 (__NR_SYSCALL_BASE+199) -#define __NR_getgid32 (__NR_SYSCALL_BASE+200) -#define __NR_geteuid32 (__NR_SYSCALL_BASE+201) -#define __NR_getegid32 (__NR_SYSCALL_BASE+202) -#define __NR_setreuid32 (__NR_SYSCALL_BASE+203) -#define __NR_setregid32 (__NR_SYSCALL_BASE+204) -#define __NR_getgroups32 (__NR_SYSCALL_BASE+205) -#define __NR_setgroups32 (__NR_SYSCALL_BASE+206) -#define __NR_fchown32 (__NR_SYSCALL_BASE+207) -#define __NR_setresuid32 (__NR_SYSCALL_BASE+208) -#define __NR_getresuid32 (__NR_SYSCALL_BASE+209) -#define __NR_setresgid32 (__NR_SYSCALL_BASE+210) -#define __NR_getresgid32 (__NR_SYSCALL_BASE+211) -#define __NR_chown32 (__NR_SYSCALL_BASE+212) -#define __NR_setuid32 (__NR_SYSCALL_BASE+213) -#define __NR_setgid32 (__NR_SYSCALL_BASE+214) -#define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) -#define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) -#define __NR_getdents64 (__NR_SYSCALL_BASE+217) -#define __NR_pivot_root (__NR_SYSCALL_BASE+218) -#define __NR_mincore (__NR_SYSCALL_BASE+219) -#define __NR_madvise (__NR_SYSCALL_BASE+220) -#define __NR_fcntl64 (__NR_SYSCALL_BASE+221) - /* 222 for tux */ - /* 223 is unused */ -#define __NR_gettid (__NR_SYSCALL_BASE+224) -#define __NR_readahead (__NR_SYSCALL_BASE+225) -#define __NR_setxattr (__NR_SYSCALL_BASE+226) -#define __NR_lsetxattr (__NR_SYSCALL_BASE+227) -#define __NR_fsetxattr (__NR_SYSCALL_BASE+228) -#define __NR_getxattr (__NR_SYSCALL_BASE+229) -#define __NR_lgetxattr (__NR_SYSCALL_BASE+230) -#define __NR_fgetxattr (__NR_SYSCALL_BASE+231) -#define __NR_listxattr (__NR_SYSCALL_BASE+232) -#define __NR_llistxattr (__NR_SYSCALL_BASE+233) -#define __NR_flistxattr (__NR_SYSCALL_BASE+234) -#define __NR_removexattr (__NR_SYSCALL_BASE+235) -#define __NR_lremovexattr (__NR_SYSCALL_BASE+236) -#define __NR_fremovexattr (__NR_SYSCALL_BASE+237) -#define __NR_tkill (__NR_SYSCALL_BASE+238) -#define __NR_sendfile64 (__NR_SYSCALL_BASE+239) -#define __NR_futex (__NR_SYSCALL_BASE+240) -#define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) -#define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) -#define __NR_io_setup (__NR_SYSCALL_BASE+243) -#define __NR_io_destroy (__NR_SYSCALL_BASE+244) -#define __NR_io_getevents (__NR_SYSCALL_BASE+245) -#define __NR_io_submit (__NR_SYSCALL_BASE+246) -#define __NR_io_cancel (__NR_SYSCALL_BASE+247) -#define __NR_exit_group (__NR_SYSCALL_BASE+248) -#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) -#define __NR_epoll_create (__NR_SYSCALL_BASE+250) -#define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) -#define __NR_epoll_wait (__NR_SYSCALL_BASE+252) -#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) - /* 254 for set_thread_area */ - /* 255 for get_thread_area */ -#define __NR_set_tid_address (__NR_SYSCALL_BASE+256) -#define __NR_timer_create (__NR_SYSCALL_BASE+257) -#define __NR_timer_settime (__NR_SYSCALL_BASE+258) -#define __NR_timer_gettime (__NR_SYSCALL_BASE+259) -#define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) -#define __NR_timer_delete (__NR_SYSCALL_BASE+261) -#define __NR_clock_settime (__NR_SYSCALL_BASE+262) -#define __NR_clock_gettime (__NR_SYSCALL_BASE+263) -#define __NR_clock_getres (__NR_SYSCALL_BASE+264) -#define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) -#define __NR_statfs64 (__NR_SYSCALL_BASE+266) -#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) -#define __NR_tgkill (__NR_SYSCALL_BASE+268) -#define __NR_utimes (__NR_SYSCALL_BASE+269) -#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) -#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) -#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) -#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) -#define __NR_mq_open (__NR_SYSCALL_BASE+274) -#define __NR_mq_unlink (__NR_SYSCALL_BASE+275) -#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) -#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) -#define __NR_mq_notify (__NR_SYSCALL_BASE+278) -#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) -#define __NR_waitid (__NR_SYSCALL_BASE+280) -#define __NR_socket (__NR_SYSCALL_BASE+281) -#define __NR_bind (__NR_SYSCALL_BASE+282) -#define __NR_connect (__NR_SYSCALL_BASE+283) -#define __NR_listen (__NR_SYSCALL_BASE+284) -#define __NR_accept (__NR_SYSCALL_BASE+285) -#define __NR_getsockname (__NR_SYSCALL_BASE+286) -#define __NR_getpeername (__NR_SYSCALL_BASE+287) -#define __NR_socketpair (__NR_SYSCALL_BASE+288) -#define __NR_send (__NR_SYSCALL_BASE+289) -#define __NR_sendto (__NR_SYSCALL_BASE+290) -#define __NR_recv (__NR_SYSCALL_BASE+291) -#define __NR_recvfrom (__NR_SYSCALL_BASE+292) -#define __NR_shutdown (__NR_SYSCALL_BASE+293) -#define __NR_setsockopt (__NR_SYSCALL_BASE+294) -#define __NR_getsockopt (__NR_SYSCALL_BASE+295) -#define __NR_sendmsg (__NR_SYSCALL_BASE+296) -#define __NR_recvmsg (__NR_SYSCALL_BASE+297) -#define __NR_semop (__NR_SYSCALL_BASE+298) -#define __NR_semget (__NR_SYSCALL_BASE+299) -#define __NR_semctl (__NR_SYSCALL_BASE+300) -#define __NR_msgsnd (__NR_SYSCALL_BASE+301) -#define __NR_msgrcv (__NR_SYSCALL_BASE+302) -#define __NR_msgget (__NR_SYSCALL_BASE+303) -#define __NR_msgctl (__NR_SYSCALL_BASE+304) -#define __NR_shmat (__NR_SYSCALL_BASE+305) -#define __NR_shmdt (__NR_SYSCALL_BASE+306) -#define __NR_shmget (__NR_SYSCALL_BASE+307) -#define __NR_shmctl (__NR_SYSCALL_BASE+308) -#define __NR_add_key (__NR_SYSCALL_BASE+309) -#define __NR_request_key (__NR_SYSCALL_BASE+310) -#define __NR_keyctl (__NR_SYSCALL_BASE+311) -#define __NR_semtimedop (__NR_SYSCALL_BASE+312) -#define __NR_vserver (__NR_SYSCALL_BASE+313) -#define __NR_ioprio_set (__NR_SYSCALL_BASE+314) -#define __NR_ioprio_get (__NR_SYSCALL_BASE+315) -#define __NR_inotify_init (__NR_SYSCALL_BASE+316) -#define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) -#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) -#define __NR_mbind (__NR_SYSCALL_BASE+319) -#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) -#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) -#define __NR_openat (__NR_SYSCALL_BASE+322) -#define __NR_mkdirat (__NR_SYSCALL_BASE+323) -#define __NR_mknodat (__NR_SYSCALL_BASE+324) -#define __NR_fchownat (__NR_SYSCALL_BASE+325) -#define __NR_futimesat (__NR_SYSCALL_BASE+326) -#define __NR_fstatat64 (__NR_SYSCALL_BASE+327) -#define __NR_unlinkat (__NR_SYSCALL_BASE+328) -#define __NR_renameat (__NR_SYSCALL_BASE+329) -#define __NR_linkat (__NR_SYSCALL_BASE+330) -#define __NR_symlinkat (__NR_SYSCALL_BASE+331) -#define __NR_readlinkat (__NR_SYSCALL_BASE+332) -#define __NR_fchmodat (__NR_SYSCALL_BASE+333) -#define __NR_faccessat (__NR_SYSCALL_BASE+334) -#define __NR_pselect6 (__NR_SYSCALL_BASE+335) -#define __NR_ppoll (__NR_SYSCALL_BASE+336) -#define __NR_unshare (__NR_SYSCALL_BASE+337) -#define __NR_set_robust_list (__NR_SYSCALL_BASE+338) -#define __NR_get_robust_list (__NR_SYSCALL_BASE+339) -#define __NR_splice (__NR_SYSCALL_BASE+340) -#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) +#include #define __NR_sync_file_range2 __NR_arm_sync_file_range -#define __NR_tee (__NR_SYSCALL_BASE+342) -#define __NR_vmsplice (__NR_SYSCALL_BASE+343) -#define __NR_move_pages (__NR_SYSCALL_BASE+344) -#define __NR_getcpu (__NR_SYSCALL_BASE+345) -#define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) -#define __NR_kexec_load (__NR_SYSCALL_BASE+347) -#define __NR_utimensat (__NR_SYSCALL_BASE+348) -#define __NR_signalfd (__NR_SYSCALL_BASE+349) -#define __NR_timerfd_create (__NR_SYSCALL_BASE+350) -#define __NR_eventfd (__NR_SYSCALL_BASE+351) -#define __NR_fallocate (__NR_SYSCALL_BASE+352) -#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) -#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) -#define __NR_signalfd4 (__NR_SYSCALL_BASE+355) -#define __NR_eventfd2 (__NR_SYSCALL_BASE+356) -#define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) -#define __NR_dup3 (__NR_SYSCALL_BASE+358) -#define __NR_pipe2 (__NR_SYSCALL_BASE+359) -#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) -#define __NR_preadv (__NR_SYSCALL_BASE+361) -#define __NR_pwritev (__NR_SYSCALL_BASE+362) -#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) -#define __NR_perf_event_open (__NR_SYSCALL_BASE+364) -#define __NR_recvmmsg (__NR_SYSCALL_BASE+365) -#define __NR_accept4 (__NR_SYSCALL_BASE+366) -#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) -#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) -#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) -#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) -#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) -#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) -#define __NR_syncfs (__NR_SYSCALL_BASE+373) -#define __NR_sendmmsg (__NR_SYSCALL_BASE+374) -#define __NR_setns (__NR_SYSCALL_BASE+375) -#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) -#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) -#define __NR_kcmp (__NR_SYSCALL_BASE+378) -#define __NR_finit_module (__NR_SYSCALL_BASE+379) -#define __NR_sched_setattr (__NR_SYSCALL_BASE+380) -#define __NR_sched_getattr (__NR_SYSCALL_BASE+381) -#define __NR_renameat2 (__NR_SYSCALL_BASE+382) -#define __NR_seccomp (__NR_SYSCALL_BASE+383) -#define __NR_getrandom (__NR_SYSCALL_BASE+384) -#define __NR_memfd_create (__NR_SYSCALL_BASE+385) -#define __NR_bpf (__NR_SYSCALL_BASE+386) -#define __NR_execveat (__NR_SYSCALL_BASE+387) -#define __NR_userfaultfd (__NR_SYSCALL_BASE+388) -#define __NR_membarrier (__NR_SYSCALL_BASE+389) -#define __NR_mlock2 (__NR_SYSCALL_BASE+390) -#define __NR_copy_file_range (__NR_SYSCALL_BASE+391) -#define __NR_preadv2 (__NR_SYSCALL_BASE+392) -#define __NR_pwritev2 (__NR_SYSCALL_BASE+393) -#define __NR_pkey_mprotect (__NR_SYSCALL_BASE+394) -#define __NR_pkey_alloc (__NR_SYSCALL_BASE+395) -#define __NR_pkey_free (__NR_SYSCALL_BASE+396) /* * The following SWIs are ARM private. @@ -434,24 +36,4 @@ #define __ARM_NR_usr32 (__ARM_NR_BASE+4) #define __ARM_NR_set_tls (__ARM_NR_BASE+5) -/* - * The following syscalls are obsolete and no longer available for EABI. - */ -#if !defined(__KERNEL__) -#if defined(__ARM_EABI__) -#undef __NR_time -#undef __NR_umount -#undef __NR_stime -#undef __NR_alarm -#undef __NR_utime -#undef __NR_getrlimit -#undef __NR_select -#undef __NR_readdir -#undef __NR_mmap -#undef __NR_socketcall -#undef __NR_syscall -#undef __NR_ipc -#endif -#endif - #endif /* _UAPI__ASM_ARM_UNISTD_H */ diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S deleted file mode 100644 index 08030b18f10a..000000000000 --- a/arch/arm/kernel/calls.S +++ /dev/null @@ -1,415 +0,0 @@ -/* - * linux/arch/arm/kernel/calls.S - * - * Copyright (C) 1995-2005 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file is included thrice in entry-common.S - */ -/* 0 */ CALL(sys_restart_syscall) - CALL(sys_exit) - CALL(sys_fork) - CALL(sys_read) - CALL(sys_write) -/* 5 */ CALL(sys_open) - CALL(sys_close) - CALL(sys_ni_syscall) /* was sys_waitpid */ - CALL(sys_creat) - CALL(sys_link) -/* 10 */ CALL(sys_unlink) - CALL(sys_execve) - CALL(sys_chdir) - CALL(OBSOLETE(sys_time)) /* used by libc4 */ - CALL(sys_mknod) -/* 15 */ CALL(sys_chmod) - CALL(sys_lchown16) - CALL(sys_ni_syscall) /* was sys_break */ - CALL(sys_ni_syscall) /* was sys_stat */ - CALL(sys_lseek) -/* 20 */ CALL(sys_getpid) - CALL(sys_mount) - CALL(OBSOLETE(sys_oldumount)) /* used by libc4 */ - CALL(sys_setuid16) - CALL(sys_getuid16) -/* 25 */ CALL(OBSOLETE(sys_stime)) - CALL(sys_ptrace) - CALL(OBSOLETE(sys_alarm)) /* used by libc4 */ - CALL(sys_ni_syscall) /* was sys_fstat */ - CALL(sys_pause) -/* 30 */ CALL(OBSOLETE(sys_utime)) /* used by libc4 */ - CALL(sys_ni_syscall) /* was sys_stty */ - CALL(sys_ni_syscall) /* was sys_getty */ - CALL(sys_access) - CALL(sys_nice) -/* 35 */ CALL(sys_ni_syscall) /* was sys_ftime */ - CALL(sys_sync) - CALL(sys_kill) - CALL(sys_rename) - CALL(sys_mkdir) -/* 40 */ CALL(sys_rmdir) - CALL(sys_dup) - CALL(sys_pipe) - CALL(sys_times) - CALL(sys_ni_syscall) /* was sys_prof */ -/* 45 */ CALL(sys_brk) - CALL(sys_setgid16) - CALL(sys_getgid16) - CALL(sys_ni_syscall) /* was sys_signal */ - CALL(sys_geteuid16) -/* 50 */ CALL(sys_getegid16) - CALL(sys_acct) - CALL(sys_umount) - CALL(sys_ni_syscall) /* was sys_lock */ - CALL(sys_ioctl) -/* 55 */ CALL(sys_fcntl) - CALL(sys_ni_syscall) /* was sys_mpx */ - CALL(sys_setpgid) - CALL(sys_ni_syscall) /* was sys_ulimit */ - CALL(sys_ni_syscall) /* was sys_olduname */ -/* 60 */ CALL(sys_umask) - CALL(sys_chroot) - CALL(sys_ustat) - CALL(sys_dup2) - CALL(sys_getppid) -/* 65 */ CALL(sys_getpgrp) - CALL(sys_setsid) - CALL(sys_sigaction) - CALL(sys_ni_syscall) /* was sys_sgetmask */ - CALL(sys_ni_syscall) /* was sys_ssetmask */ -/* 70 */ CALL(sys_setreuid16) - CALL(sys_setregid16) - CALL(sys_sigsuspend) - CALL(sys_sigpending) - CALL(sys_sethostname) -/* 75 */ CALL(sys_setrlimit) - CALL(OBSOLETE(sys_old_getrlimit)) /* used by libc4 */ - CALL(sys_getrusage) - CALL(sys_gettimeofday) - CALL(sys_settimeofday) -/* 80 */ CALL(sys_getgroups16) - CALL(sys_setgroups16) - CALL(OBSOLETE(sys_old_select)) /* used by libc4 */ - CALL(sys_symlink) - CALL(sys_ni_syscall) /* was sys_lstat */ -/* 85 */ CALL(sys_readlink) - CALL(sys_uselib) - CALL(sys_swapon) - CALL(sys_reboot) - CALL(OBSOLETE(sys_old_readdir)) /* used by libc4 */ -/* 90 */ CALL(OBSOLETE(sys_old_mmap)) /* used by libc4 */ - CALL(sys_munmap) - CALL(sys_truncate) - CALL(sys_ftruncate) - CALL(sys_fchmod) -/* 95 */ CALL(sys_fchown16) - CALL(sys_getpriority) - CALL(sys_setpriority) - CALL(sys_ni_syscall) /* was sys_profil */ - CALL(sys_statfs) -/* 100 */ CALL(sys_fstatfs) - CALL(sys_ni_syscall) /* sys_ioperm */ - CALL(OBSOLETE(ABI(sys_socketcall, sys_oabi_socketcall))) - CALL(sys_syslog) - CALL(sys_setitimer) -/* 105 */ CALL(sys_getitimer) - CALL(sys_newstat) - CALL(sys_newlstat) - CALL(sys_newfstat) - CALL(sys_ni_syscall) /* was sys_uname */ -/* 110 */ CALL(sys_ni_syscall) /* was sys_iopl */ - CALL(sys_vhangup) - CALL(sys_ni_syscall) - CALL(OBSOLETE(sys_syscall)) /* call a syscall */ - CALL(sys_wait4) -/* 115 */ CALL(sys_swapoff) - CALL(sys_sysinfo) - CALL(OBSOLETE(ABI(sys_ipc, sys_oabi_ipc))) - CALL(sys_fsync) - CALL(sys_sigreturn_wrapper) -/* 120 */ CALL(sys_clone) - CALL(sys_setdomainname) - CALL(sys_newuname) - CALL(sys_ni_syscall) /* modify_ldt */ - CALL(sys_adjtimex) -/* 125 */ CALL(sys_mprotect) - CALL(sys_sigprocmask) - CALL(sys_ni_syscall) /* was sys_create_module */ - CALL(sys_init_module) - CALL(sys_delete_module) -/* 130 */ CALL(sys_ni_syscall) /* was sys_get_kernel_syms */ - CALL(sys_quotactl) - CALL(sys_getpgid) - CALL(sys_fchdir) - CALL(sys_bdflush) -/* 135 */ CALL(sys_sysfs) - CALL(sys_personality) - CALL(sys_ni_syscall) /* reserved for afs_syscall */ - CALL(sys_setfsuid16) - CALL(sys_setfsgid16) -/* 140 */ CALL(sys_llseek) - CALL(sys_getdents) - CALL(sys_select) - CALL(sys_flock) - CALL(sys_msync) -/* 145 */ CALL(sys_readv) - CALL(sys_writev) - CALL(sys_getsid) - CALL(sys_fdatasync) - CALL(sys_sysctl) -/* 150 */ CALL(sys_mlock) - CALL(sys_munlock) - CALL(sys_mlockall) - CALL(sys_munlockall) - CALL(sys_sched_setparam) -/* 155 */ CALL(sys_sched_getparam) - CALL(sys_sched_setscheduler) - CALL(sys_sched_getscheduler) - CALL(sys_sched_yield) - CALL(sys_sched_get_priority_max) -/* 160 */ CALL(sys_sched_get_priority_min) - CALL(sys_sched_rr_get_interval) - CALL(sys_nanosleep) - CALL(sys_mremap) - CALL(sys_setresuid16) -/* 165 */ CALL(sys_getresuid16) - CALL(sys_ni_syscall) /* vm86 */ - CALL(sys_ni_syscall) /* was sys_query_module */ - CALL(sys_poll) - CALL(sys_ni_syscall) /* was nfsservctl */ -/* 170 */ CALL(sys_setresgid16) - CALL(sys_getresgid16) - CALL(sys_prctl) - CALL(sys_rt_sigreturn_wrapper) - CALL(sys_rt_sigaction) -/* 175 */ CALL(sys_rt_sigprocmask) - CALL(sys_rt_sigpending) - CALL(sys_rt_sigtimedwait) - CALL(sys_rt_sigqueueinfo) - CALL(sys_rt_sigsuspend) -/* 180 */ CALL(ABI(sys_pread64, sys_oabi_pread64)) - CALL(ABI(sys_pwrite64, sys_oabi_pwrite64)) - CALL(sys_chown16) - CALL(sys_getcwd) - CALL(sys_capget) -/* 185 */ CALL(sys_capset) - CALL(sys_sigaltstack) - CALL(sys_sendfile) - CALL(sys_ni_syscall) /* getpmsg */ - CALL(sys_ni_syscall) /* putpmsg */ -/* 190 */ CALL(sys_vfork) - CALL(sys_getrlimit) - CALL(sys_mmap2) - CALL(ABI(sys_truncate64, sys_oabi_truncate64)) - CALL(ABI(sys_ftruncate64, sys_oabi_ftruncate64)) -/* 195 */ CALL(ABI(sys_stat64, sys_oabi_stat64)) - CALL(ABI(sys_lstat64, sys_oabi_lstat64)) - CALL(ABI(sys_fstat64, sys_oabi_fstat64)) - CALL(sys_lchown) - CALL(sys_getuid) -/* 200 */ CALL(sys_getgid) - CALL(sys_geteuid) - CALL(sys_getegid) - CALL(sys_setreuid) - CALL(sys_setregid) -/* 205 */ CALL(sys_getgroups) - CALL(sys_setgroups) - CALL(sys_fchown) - CALL(sys_setresuid) - CALL(sys_getresuid) -/* 210 */ CALL(sys_setresgid) - CALL(sys_getresgid) - CALL(sys_chown) - CALL(sys_setuid) - CALL(sys_setgid) -/* 215 */ CALL(sys_setfsuid) - CALL(sys_setfsgid) - CALL(sys_getdents64) - CALL(sys_pivot_root) - CALL(sys_mincore) -/* 220 */ CALL(sys_madvise) - CALL(ABI(sys_fcntl64, sys_oabi_fcntl64)) - CALL(sys_ni_syscall) /* TUX */ - CALL(sys_ni_syscall) - CALL(sys_gettid) -/* 225 */ CALL(ABI(sys_readahead, sys_oabi_readahead)) - CALL(sys_setxattr) - CALL(sys_lsetxattr) - CALL(sys_fsetxattr) - CALL(sys_getxattr) -/* 230 */ CALL(sys_lgetxattr) - CALL(sys_fgetxattr) - CALL(sys_listxattr) - CALL(sys_llistxattr) - CALL(sys_flistxattr) -/* 235 */ CALL(sys_removexattr) - CALL(sys_lremovexattr) - CALL(sys_fremovexattr) - CALL(sys_tkill) - CALL(sys_sendfile64) -/* 240 */ CALL(sys_futex) - CALL(sys_sched_setaffinity) - CALL(sys_sched_getaffinity) - CALL(sys_io_setup) - CALL(sys_io_destroy) -/* 245 */ CALL(sys_io_getevents) - CALL(sys_io_submit) - CALL(sys_io_cancel) - CALL(sys_exit_group) - CALL(sys_lookup_dcookie) -/* 250 */ CALL(sys_epoll_create) - CALL(ABI(sys_epoll_ctl, sys_oabi_epoll_ctl)) - CALL(ABI(sys_epoll_wait, sys_oabi_epoll_wait)) - CALL(sys_remap_file_pages) - CALL(sys_ni_syscall) /* sys_set_thread_area */ -/* 255 */ CALL(sys_ni_syscall) /* sys_get_thread_area */ - CALL(sys_set_tid_address) - CALL(sys_timer_create) - CALL(sys_timer_settime) - CALL(sys_timer_gettime) -/* 260 */ CALL(sys_timer_getoverrun) - CALL(sys_timer_delete) - CALL(sys_clock_settime) - CALL(sys_clock_gettime) - CALL(sys_clock_getres) -/* 265 */ CALL(sys_clock_nanosleep) - CALL(sys_statfs64_wrapper) - CALL(sys_fstatfs64_wrapper) - CALL(sys_tgkill) - CALL(sys_utimes) -/* 270 */ CALL(sys_arm_fadvise64_64) - CALL(sys_pciconfig_iobase) - CALL(sys_pciconfig_read) - CALL(sys_pciconfig_write) - CALL(sys_mq_open) -/* 275 */ CALL(sys_mq_unlink) - CALL(sys_mq_timedsend) - CALL(sys_mq_timedreceive) - CALL(sys_mq_notify) - CALL(sys_mq_getsetattr) -/* 280 */ CALL(sys_waitid) - CALL(sys_socket) - CALL(ABI(sys_bind, sys_oabi_bind)) - CALL(ABI(sys_connect, sys_oabi_connect)) - CALL(sys_listen) -/* 285 */ CALL(sys_accept) - CALL(sys_getsockname) - CALL(sys_getpeername) - CALL(sys_socketpair) - CALL(sys_send) -/* 290 */ CALL(ABI(sys_sendto, sys_oabi_sendto)) - CALL(sys_recv) - CALL(sys_recvfrom) - CALL(sys_shutdown) - CALL(sys_setsockopt) -/* 295 */ CALL(sys_getsockopt) - CALL(ABI(sys_sendmsg, sys_oabi_sendmsg)) - CALL(sys_recvmsg) - CALL(ABI(sys_semop, sys_oabi_semop)) - CALL(sys_semget) -/* 300 */ CALL(sys_semctl) - CALL(sys_msgsnd) - CALL(sys_msgrcv) - CALL(sys_msgget) - CALL(sys_msgctl) -/* 305 */ CALL(sys_shmat) - CALL(sys_shmdt) - CALL(sys_shmget) - CALL(sys_shmctl) - CALL(sys_add_key) -/* 310 */ CALL(sys_request_key) - CALL(sys_keyctl) - CALL(ABI(sys_semtimedop, sys_oabi_semtimedop)) -/* vserver */ CALL(sys_ni_syscall) - CALL(sys_ioprio_set) -/* 315 */ CALL(sys_ioprio_get) - CALL(sys_inotify_init) - CALL(sys_inotify_add_watch) - CALL(sys_inotify_rm_watch) - CALL(sys_mbind) -/* 320 */ CALL(sys_get_mempolicy) - CALL(sys_set_mempolicy) - CALL(sys_openat) - CALL(sys_mkdirat) - CALL(sys_mknodat) -/* 325 */ CALL(sys_fchownat) - CALL(sys_futimesat) - CALL(ABI(sys_fstatat64, sys_oabi_fstatat64)) - CALL(sys_unlinkat) - CALL(sys_renameat) -/* 330 */ CALL(sys_linkat) - CALL(sys_symlinkat) - CALL(sys_readlinkat) - CALL(sys_fchmodat) - CALL(sys_faccessat) -/* 335 */ CALL(sys_pselect6) - CALL(sys_ppoll) - CALL(sys_unshare) - CALL(sys_set_robust_list) - CALL(sys_get_robust_list) -/* 340 */ CALL(sys_splice) - CALL(sys_sync_file_range2) - CALL(sys_tee) - CALL(sys_vmsplice) - CALL(sys_move_pages) -/* 345 */ CALL(sys_getcpu) - CALL(sys_epoll_pwait) - CALL(sys_kexec_load) - CALL(sys_utimensat) - CALL(sys_signalfd) -/* 350 */ CALL(sys_timerfd_create) - CALL(sys_eventfd) - CALL(sys_fallocate) - CALL(sys_timerfd_settime) - CALL(sys_timerfd_gettime) -/* 355 */ CALL(sys_signalfd4) - CALL(sys_eventfd2) - CALL(sys_epoll_create1) - CALL(sys_dup3) - CALL(sys_pipe2) -/* 360 */ CALL(sys_inotify_init1) - CALL(sys_preadv) - CALL(sys_pwritev) - CALL(sys_rt_tgsigqueueinfo) - CALL(sys_perf_event_open) -/* 365 */ CALL(sys_recvmmsg) - CALL(sys_accept4) - CALL(sys_fanotify_init) - CALL(sys_fanotify_mark) - CALL(sys_prlimit64) -/* 370 */ CALL(sys_name_to_handle_at) - CALL(sys_open_by_handle_at) - CALL(sys_clock_adjtime) - CALL(sys_syncfs) - CALL(sys_sendmmsg) -/* 375 */ CALL(sys_setns) - CALL(sys_process_vm_readv) - CALL(sys_process_vm_writev) - CALL(sys_kcmp) - CALL(sys_finit_module) -/* 380 */ CALL(sys_sched_setattr) - CALL(sys_sched_getattr) - CALL(sys_renameat2) - CALL(sys_seccomp) - CALL(sys_getrandom) -/* 385 */ CALL(sys_memfd_create) - CALL(sys_bpf) - CALL(sys_execveat) - CALL(sys_userfaultfd) - CALL(sys_membarrier) -/* 390 */ CALL(sys_mlock2) - CALL(sys_copy_file_range) - CALL(sys_preadv2) - CALL(sys_pwritev2) - CALL(sys_pkey_mprotect) -/* 395 */ CALL(sys_pkey_alloc) - CALL(sys_pkey_free) -#ifndef syscalls_counted -.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls -#define syscalls_counted -#endif -.rept syscalls_padding - CALL(sys_ni_syscall) -.endr diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 10c3283d6c19..eb5cd77bf1d8 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -12,6 +12,11 @@ #include #include #include +#ifdef CONFIG_AEABI +#include +#endif + + .equ NR_syscalls, __NR_syscalls #ifdef CONFIG_NEED_RET_TO_USER #include @@ -120,21 +125,6 @@ ENTRY(ret_from_fork) b ret_slow_syscall ENDPROC(ret_from_fork) - .equ NR_syscalls,0 -#define CALL(x) .equ NR_syscalls,NR_syscalls+1 -#include "calls.S" - -/* - * Ensure that the system call table is equal to __NR_syscalls, - * which is the value the rest of the system sees - */ -.ifne NR_syscalls - __NR_syscalls -.error "__NR_syscalls is not equal to the size of the syscall table" -.endif - -#undef CALL -#define CALL(x) .long x - /*============================================================================= * SWI handler *----------------------------------------------------------------------------- @@ -291,22 +281,48 @@ __cr_alignment: #endif .ltorg + .macro syscall_table_start, sym + .equ __sys_nr, 0 + .type \sym, #object +ENTRY(\sym) + .endm + + .macro syscall, nr, func + .ifgt __sys_nr - \nr + .error "Duplicated/unorded system call entry" + .endif + .rept \nr - __sys_nr + .long sys_ni_syscall + .endr + .long \func + .equ __sys_nr, \nr + 1 + .endm + + .macro syscall_table_end, sym + .ifgt __sys_nr - __NR_syscalls + .error "System call table too big" + .endif + .rept __NR_syscalls - __sys_nr + .long sys_ni_syscall + .endr + .size \sym, . - \sym + .endm + +#define NATIVE(nr, func) syscall nr, func + /* * This is the syscall table declaration for native ABI syscalls. * With EABI a couple syscalls are obsolete and defined as sys_ni_syscall. */ -#define ABI(native, compat) native + syscall_table_start sys_call_table +#define COMPAT(nr, native, compat) syscall nr, native #ifdef CONFIG_AEABI -#define OBSOLETE(syscall) sys_ni_syscall +#include #else -#define OBSOLETE(syscall) syscall +#include #endif - - .type sys_call_table, #object -ENTRY(sys_call_table) -#include "calls.S" -#undef ABI -#undef OBSOLETE +#undef COMPAT + syscall_table_end sys_call_table /*============================================================================ * Special system call wrappers @@ -407,14 +423,10 @@ ENDPROC(sys_oabi_readahead) * Let's declare a second syscall table for old ABI binaries * using the compatibility syscall entries. */ -#define ABI(native, compat) compat -#define OBSOLETE(syscall) syscall - - .type sys_oabi_call_table, #object -ENTRY(sys_oabi_call_table) -#include "calls.S" -#undef ABI -#undef OBSOLETE + syscall_table_start sys_oabi_call_table +#define COMPAT(nr, native, compat) syscall nr, compat +#include + syscall_table_end sys_oabi_call_table #endif diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 188180b5523d..be3b3fbd382f 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1063,6 +1063,22 @@ static int __init arch_hw_breakpoint_init(void) return 0; } + /* + * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD + * whenever a WFI is issued, even if the core is not powered down, in + * violation of the architecture. When DBGPRSR.SPD is set, accesses to + * breakpoint and watchpoint registers are treated as undefined, so + * this results in boot time and runtime failures when these are + * accessed and we unexpectedly take a trap. + * + * It's not clear if/how this can be worked around, so we blacklist + * Scorpion CPUs to avoid these issues. + */ + if (read_cpuid_part() == ARM_CPU_PART_SCORPION) { + pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n"); + return 0; + } + has_ossr = core_has_os_save_restore(); /* Determine how many BRPs/WRPs are available. */ diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index 22313cb53362..9af0701f7094 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -9,6 +9,7 @@ */ #include #include +#include #include #include @@ -40,8 +41,11 @@ static inline void ipi_flush_tlb_mm(void *arg) static inline void ipi_flush_tlb_page(void *arg) { struct tlb_args *ta = (struct tlb_args *)arg; + unsigned int __ua_flags = uaccess_save_and_enable(); local_flush_tlb_page(ta->ta_vma, ta->ta_start); + + uaccess_restore(__ua_flags); } static inline void ipi_flush_tlb_kernel_page(void *arg) @@ -54,8 +58,11 @@ static inline void ipi_flush_tlb_kernel_page(void *arg) static inline void ipi_flush_tlb_range(void *arg) { struct tlb_args *ta = (struct tlb_args *)arg; + unsigned int __ua_flags = uaccess_save_and_enable(); local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end); + + uaccess_restore(__ua_flags); } static inline void ipi_flush_tlb_kernel_range(void *arg) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 02d5e5e8d44c..895ae5197159 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -339,7 +339,7 @@ static int __init twd_local_timer_common_register(struct device_node *np) } cpuhp_setup_state_nocalls(CPUHP_AP_ARM_TWD_STARTING, - "AP_ARM_TWD_STARTING", + "arm/timer/twd:starting", twd_timer_starting_cpu, twd_timer_dying_cpu); twd_get_clock(np); diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index c3fe769d7558..853221f81104 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include /* * Error-checking SWP macros implemented using ldrex{b}/strex{b} diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index ec279d161b32..ebf47d91b804 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include @@ -21,7 +22,9 @@ #include #include #include +#include +#include #include #include @@ -41,6 +44,7 @@ * updated during this sequence. */ static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE; +static DEFINE_MUTEX(cpu_scale_mutex); unsigned long arch_scale_cpu_capacity(struct sched_domain *sd, int cpu) { @@ -52,6 +56,65 @@ static void set_capacity_scale(unsigned int cpu, unsigned long capacity) per_cpu(cpu_scale, cpu) = capacity; } +#ifdef CONFIG_PROC_SYSCTL +static ssize_t cpu_capacity_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + + return sprintf(buf, "%lu\n", + arch_scale_cpu_capacity(NULL, cpu->dev.id)); +} + +static ssize_t cpu_capacity_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + int this_cpu = cpu->dev.id, i; + unsigned long new_capacity; + ssize_t ret; + + if (count) { + ret = kstrtoul(buf, 0, &new_capacity); + if (ret) + return ret; + if (new_capacity > SCHED_CAPACITY_SCALE) + return -EINVAL; + + mutex_lock(&cpu_scale_mutex); + for_each_cpu(i, &cpu_topology[this_cpu].core_sibling) + set_capacity_scale(i, new_capacity); + mutex_unlock(&cpu_scale_mutex); + } + + return count; +} + +static DEVICE_ATTR_RW(cpu_capacity); + +static int register_cpu_capacity_sysctl(void) +{ + int i; + struct device *cpu; + + for_each_possible_cpu(i) { + cpu = get_cpu_device(i); + if (!cpu) { + pr_err("%s: too early to get CPU%d device!\n", + __func__, i); + continue; + } + device_create_file(cpu, &dev_attr_cpu_capacity); + } + + return 0; +} +subsys_initcall(register_cpu_capacity_sysctl); +#endif + #ifdef CONFIG_OF struct cpu_efficiency { const char *compatible; @@ -78,6 +141,146 @@ static unsigned long *__cpu_capacity; #define cpu_capacity(cpu) __cpu_capacity[cpu] static unsigned long middle_capacity = 1; +static bool cap_from_dt = true; +static u32 *raw_capacity; +static bool cap_parsing_failed; +static u32 capacity_scale; + +static int __init parse_cpu_capacity(struct device_node *cpu_node, int cpu) +{ + int ret = 1; + u32 cpu_capacity; + + if (cap_parsing_failed) + return !ret; + + ret = of_property_read_u32(cpu_node, + "capacity-dmips-mhz", + &cpu_capacity); + if (!ret) { + if (!raw_capacity) { + raw_capacity = kcalloc(num_possible_cpus(), + sizeof(*raw_capacity), + GFP_KERNEL); + if (!raw_capacity) { + pr_err("cpu_capacity: failed to allocate memory for raw capacities\n"); + cap_parsing_failed = true; + return !ret; + } + } + capacity_scale = max(cpu_capacity, capacity_scale); + raw_capacity[cpu] = cpu_capacity; + pr_debug("cpu_capacity: %s cpu_capacity=%u (raw)\n", + cpu_node->full_name, raw_capacity[cpu]); + } else { + if (raw_capacity) { + pr_err("cpu_capacity: missing %s raw capacity\n", + cpu_node->full_name); + pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n"); + } + cap_parsing_failed = true; + kfree(raw_capacity); + } + + return !ret; +} + +static void normalize_cpu_capacity(void) +{ + u64 capacity; + int cpu; + + if (!raw_capacity || cap_parsing_failed) + return; + + pr_debug("cpu_capacity: capacity_scale=%u\n", capacity_scale); + mutex_lock(&cpu_scale_mutex); + for_each_possible_cpu(cpu) { + capacity = (raw_capacity[cpu] << SCHED_CAPACITY_SHIFT) + / capacity_scale; + set_capacity_scale(cpu, capacity); + pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n", + cpu, arch_scale_cpu_capacity(NULL, cpu)); + } + mutex_unlock(&cpu_scale_mutex); +} + +#ifdef CONFIG_CPU_FREQ +static cpumask_var_t cpus_to_visit; +static bool cap_parsing_done; +static void parsing_done_workfn(struct work_struct *work); +static DECLARE_WORK(parsing_done_work, parsing_done_workfn); + +static int +init_cpu_capacity_callback(struct notifier_block *nb, + unsigned long val, + void *data) +{ + struct cpufreq_policy *policy = data; + int cpu; + + if (cap_parsing_failed || cap_parsing_done) + return 0; + + switch (val) { + case CPUFREQ_NOTIFY: + pr_debug("cpu_capacity: init cpu capacity for CPUs [%*pbl] (to_visit=%*pbl)\n", + cpumask_pr_args(policy->related_cpus), + cpumask_pr_args(cpus_to_visit)); + cpumask_andnot(cpus_to_visit, + cpus_to_visit, + policy->related_cpus); + for_each_cpu(cpu, policy->related_cpus) { + raw_capacity[cpu] = arch_scale_cpu_capacity(NULL, cpu) * + policy->cpuinfo.max_freq / 1000UL; + capacity_scale = max(raw_capacity[cpu], capacity_scale); + } + if (cpumask_empty(cpus_to_visit)) { + normalize_cpu_capacity(); + kfree(raw_capacity); + pr_debug("cpu_capacity: parsing done\n"); + cap_parsing_done = true; + schedule_work(&parsing_done_work); + } + } + return 0; +} + +static struct notifier_block init_cpu_capacity_notifier = { + .notifier_call = init_cpu_capacity_callback, +}; + +static int __init register_cpufreq_notifier(void) +{ + if (cap_parsing_failed) + return -EINVAL; + + if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL)) { + pr_err("cpu_capacity: failed to allocate memory for cpus_to_visit\n"); + return -ENOMEM; + } + cpumask_copy(cpus_to_visit, cpu_possible_mask); + + return cpufreq_register_notifier(&init_cpu_capacity_notifier, + CPUFREQ_POLICY_NOTIFIER); +} +core_initcall(register_cpufreq_notifier); + +static void parsing_done_workfn(struct work_struct *work) +{ + cpufreq_unregister_notifier(&init_cpu_capacity_notifier, + CPUFREQ_POLICY_NOTIFIER); +} + +#else +static int __init free_raw_capacity(void) +{ + kfree(raw_capacity); + + return 0; +} +core_initcall(free_raw_capacity); +#endif /* * Iterate all CPUs' descriptor in DT and compute the efficiency @@ -99,6 +302,12 @@ static void __init parse_dt_topology(void) __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity), GFP_NOWAIT); + cn = of_find_node_by_path("/cpus"); + if (!cn) { + pr_err("No CPU information found in DT\n"); + return; + } + for_each_possible_cpu(cpu) { const u32 *rate; int len; @@ -110,6 +319,13 @@ static void __init parse_dt_topology(void) continue; } + if (parse_cpu_capacity(cn, cpu)) { + of_node_put(cn); + continue; + } + + cap_from_dt = false; + for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++) if (of_device_is_compatible(cn, cpu_eff->compatible)) break; @@ -151,6 +367,8 @@ static void __init parse_dt_topology(void) middle_capacity = ((max_capacity / 3) >> (SCHED_CAPACITY_SHIFT-1)) + 1; + if (cap_from_dt && !cap_parsing_failed) + normalize_cpu_capacity(); } /* @@ -160,7 +378,7 @@ static void __init parse_dt_topology(void) */ static void update_cpu_capacity(unsigned int cpu) { - if (!cpu_capacity(cpu)) + if (!cpu_capacity(cpu) || cap_from_dt) return; set_capacity_scale(cpu, cpu_capacity(cpu) / middle_capacity); diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 8f92efa8460e..11676787ad49 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -33,7 +33,7 @@ #define CREATE_TRACE_POINTS #include "trace.h" -#include +#include #include #include #include diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index 9aca92074f85..fa6182a40941 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S index 792c59d885bc..c766694e929c 100644 --- a/arch/arm/lib/delay-loop.S +++ b/arch/arm/lib/delay-loop.S @@ -17,24 +17,23 @@ .LC1: .word UDELAY_MULT /* + * loops = r0 * HZ * loops_per_jiffy / 1000000 + * * r0 <= 2000 * HZ <= 1000 */ ENTRY(__loop_udelay) ldr r2, .LC1 - mul r0, r2, r0 -ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06 + mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT +ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0 ldr r2, .LC0 ldr r2, [r2] - umull r1, r0, r2, r0 - adds r1, r1, #0xffffffff - adcs r0, r0, r0 + umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy + adds r1, r1, #0xffffffff @ rounding up ... + adcs r0, r0, r0 @ and right shift by 31 reteq lr -/* - * loops = r0 * HZ * loops_per_jiffy / 1000000 - */ .align 3 @ Delay routine diff --git a/arch/arm/mach-artpec/Kconfig b/arch/arm/mach-artpec/Kconfig index 6cbe5a2eabab..85a962abb77f 100644 --- a/arch/arm/mach-artpec/Kconfig +++ b/arch/arm/mach-artpec/Kconfig @@ -14,6 +14,7 @@ config MACH_ARTPEC6 select HAVE_ARM_ARCH_TIMER select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP + select MFD_SYSCON help Support for Axis ARTPEC-6 ARM Cortex A9 Platform diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c index c8830a2b0d60..fe067f6cebb6 100644 --- a/arch/arm/mach-bcm/bcm_5301x.c +++ b/arch/arm/mach-bcm/bcm_5301x.c @@ -9,14 +9,42 @@ #include #include +#include +#include + +#define FSR_EXTERNAL (1 << 12) +#define FSR_READ (0 << 10) +#define FSR_IMPRECISE 0x0406 static const char *const bcm5301x_dt_compat[] __initconst = { "brcm,bcm4708", NULL, }; +static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + /* + * We want to ignore aborts forwarded from the PCIe bus that are + * expected and shouldn't really be passed by the PCIe controller. + * The biggest disadvantage is the same FSR code may be reported when + * reading non-existing APB register and we shouldn't ignore that. + */ + if (fsr == (FSR_EXTERNAL | FSR_READ | FSR_IMPRECISE)) + return 0; + + return 1; +} + +static void __init bcm5301x_init_early(void) +{ + hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, + "imprecise external abort"); +} + DT_MACHINE_START(BCM5301X, "BCM5301X") .l2c_aux_val = 0, .l2c_aux_mask = ~0, .dt_compat = bcm5301x_dt_compat, + .init_early = bcm5301x_init_early, MACHINE_END diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index da4c336b4637..0a2e6da45f28 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -36,5 +36,7 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o # Power Management obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_HAVE_CLK) += pm_domain.o +ifeq ($(CONFIG_SUSPEND),y) +obj-$(CONFIG_ARCH_DAVINCI_DA850) += pm.o sleep.o +endif diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 3d8cf8cbd98a..58075627c6df 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include @@ -106,43 +108,24 @@ static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id) static __init void da830_evm_usb_init(void) { - u32 cfgchip2; int ret; - /* - * Set up USB clock/mode in the CFGCHIP2 register. - * FYI: CFGCHIP2 is 0x0000ef00 initially. - */ - cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - /* USB2.0 PHY reference clock is 24 MHz */ - cfgchip2 &= ~CFGCHIP2_REFFREQ; - cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; - - /* - * Select internal reference clock for USB 2.0 PHY - * and use it as a clock source for USB 1.1 PHY - * (this is the default setting anyway). - */ - cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX; - cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX; - - /* - * We have to override VBUS/ID signals when MUSB is configured into the - * host-only mode -- ID pin will float if no cable is connected, so the - * controller won't be able to drive VBUS thinking that it's a B-device. - * Otherwise, we want to use the OTG mode and enable VBUS comparators. - */ - cfgchip2 &= ~CFGCHIP2_OTGMODE; -#ifdef CONFIG_USB_MUSB_HOST - cfgchip2 |= CFGCHIP2_FORCE_HOST; -#else - cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN; -#endif - - __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - /* USB_REFCLKIN is not used. */ + ret = da8xx_register_usb20_phy_clk(false); + if (ret) + pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n", + __func__, ret); + + ret = da8xx_register_usb11_phy_clk(false); + if (ret) + pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n", + __func__, ret); + + ret = da8xx_register_usb_phy(); + if (ret) + pr_warn("%s: USB PHY registration failed: %d\n", + __func__, ret); + ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); if (ret) pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret); @@ -222,22 +205,16 @@ static const short da830_evm_mmc_sd_pins[] = { -1 }; -#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) -#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2) - -static int da830_evm_mmc_get_ro(int index) -{ - return gpio_get_value(DA830_MMCSD_WP_PIN); -} - -static int da830_evm_mmc_get_cd(int index) -{ - return !gpio_get_value(DA830_MMCSD_CD_PIN); -} +static struct gpiod_lookup_table mmc_gpios_table = { + .dev_id = "da830-mmc.0", + .table = { + /* gpio chip 1 contains gpio range 32-63 */ + GPIO_LOOKUP("davinci_gpio.1", 2, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("davinci_gpio.1", 1, "wp", GPIO_ACTIVE_LOW), + }, +}; static struct davinci_mmc_config da830_evm_mmc_config = { - .get_ro = da830_evm_mmc_get_ro, - .get_cd = da830_evm_mmc_get_cd, .wires = 8, .max_freq = 50000000, .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, @@ -253,26 +230,12 @@ static inline void da830_evm_init_mmc(void) return; } - ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP"); - if (ret) { - pr_warn("%s: can not open GPIO %d\n", - __func__, DA830_MMCSD_WP_PIN); - return; - } - gpio_direction_input(DA830_MMCSD_WP_PIN); - - ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n"); - if (ret) { - pr_warn("%s: can not open GPIO %d\n", - __func__, DA830_MMCSD_CD_PIN); - return; - } - gpio_direction_input(DA830_MMCSD_CD_PIN); + gpiod_add_lookup_table(&mmc_gpios_table); ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); if (ret) { pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret); - gpio_free(DA830_MMCSD_WP_PIN); + gpiod_remove_lookup_table(&mmc_gpios_table); } } @@ -588,6 +551,10 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; + ret = da8xx_register_cfgchip(); + if (ret) + pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); + ret = da830_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); @@ -647,6 +614,8 @@ static __init void da830_evm_init(void) ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); if (ret) pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret); + + regulator_has_full_constraints(); } #ifdef CONFIG_SERIAL_8250_CONSOLE diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 8e4539f69fdc..aac3ab1a044f 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -56,9 +57,6 @@ #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) -#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) -#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) - #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) static struct mtd_partition da850evm_spiflash_part[] = { @@ -196,18 +194,6 @@ static struct platform_device da850_evm_norflash_device = { .resource = da850_evm_norflash_resource, }; -static struct davinci_pm_config da850_pm_pdata = { - .sleepcount = 128, -}; - -static struct platform_device da850_pm_device = { - .name = "pm-davinci", - .dev = { - .platform_data = &da850_pm_pdata, - }, - .id = -1, -}; - /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash * (128K blocks). It may be used instead of the (default) SPI flash * to boot, using TI's tools to install the secondary boot loader @@ -776,19 +762,16 @@ static const short da850_evm_mcasp_pins[] __initconst = { -1 }; -static int da850_evm_mmc_get_ro(int index) -{ - return gpio_get_value(DA850_MMCSD_WP_PIN); -} - -static int da850_evm_mmc_get_cd(int index) -{ - return !gpio_get_value(DA850_MMCSD_CD_PIN); -} +static struct gpiod_lookup_table mmc_gpios_table = { + .dev_id = "da830-mmc.0", + .table = { + /* gpio chip 2 contains gpio range 64-95 */ + GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW), + }, +}; static struct davinci_mmc_config da850_mmc_config = { - .get_ro = da850_evm_mmc_get_ro, - .get_cd = da850_evm_mmc_get_cd, .wires = 4, .max_freq = 50000000, .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, @@ -1345,6 +1328,10 @@ static __init void da850_evm_init(void) { int ret; + ret = da8xx_register_cfgchip(); + if (ret) + pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); + ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); @@ -1379,17 +1366,7 @@ static __init void da850_evm_init(void) pr_warn("%s: MMCSD0 mux setup failed: %d\n", __func__, ret); - ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); - if (ret) - pr_warn("%s: can not open GPIO %d\n", - __func__, DA850_MMCSD_CD_PIN); - gpio_direction_input(DA850_MMCSD_CD_PIN); - - ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); - if (ret) - pr_warn("%s: can not open GPIO %d\n", - __func__, DA850_MMCSD_WP_PIN); - gpio_direction_input(DA850_MMCSD_WP_PIN); + gpiod_add_lookup_table(&mmc_gpios_table); ret = da8xx_register_mmcsd0(&da850_mmc_config); if (ret) @@ -1453,10 +1430,7 @@ static __init void da850_evm_init(void) if (ret) pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret); - ret = da850_register_pm(&da850_pm_device); - if (ret) - pr_warn("%s: suspend registration failed: %d\n", __func__, ret); - + davinci_pm_init(); da850_vpif_init(); ret = spi_register_board_info(da850evm_spi_info, diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index bc4e63fa9808..b73ce7bae81f 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -498,22 +498,14 @@ static void __init mityomapl138_config_emac(void) pr_warn("emac registration failed: %d\n", ret); } -static struct davinci_pm_config da850_pm_pdata = { - .sleepcount = 128, -}; - -static struct platform_device da850_pm_device = { - .name = "pm-davinci", - .dev = { - .platform_data = &da850_pm_pdata, - }, - .id = -1, -}; - static void __init mityomapl138_init(void) { int ret; + ret = da8xx_register_cfgchip(); + if (ret) + pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); + /* for now, no special EDMA channels are reserved */ ret = da850_register_edma(NULL); if (ret) @@ -555,9 +547,7 @@ static void __init mityomapl138_init(void) if (ret) pr_warn("cpuidle registration failed: %d\n", ret); - ret = da850_register_pm(&da850_pm_device); - if (ret) - pr_warn("suspend registration failed: %d\n", ret); + davinci_pm_init(); } #ifdef CONFIG_SERIAL_8250_CONSOLE diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index ee624861ca66..41d5500996b2 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include #include @@ -24,8 +26,6 @@ #include #define HAWKBOARD_PHY_ID "davinci_mdio-0:07" -#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) -#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) #define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4) #define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13) @@ -122,19 +122,16 @@ static const short hawk_mmcsd0_pins[] = { -1 }; -static int da850_hawk_mmc_get_ro(int index) -{ - return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN); -} - -static int da850_hawk_mmc_get_cd(int index) -{ - return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN); -} +static struct gpiod_lookup_table mmc_gpios_table = { + .dev_id = "da830-mmc.0", + .table = { + /* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/ + GPIO_LOOKUP("davinci_gpio.1", 28, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("davinci_gpio.1", 29, "wp", GPIO_ACTIVE_LOW), + }, +}; static struct davinci_mmc_config da850_mmc_config = { - .get_ro = da850_hawk_mmc_get_ro, - .get_cd = da850_hawk_mmc_get_cd, .wires = 4, .max_freq = 50000000, .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, @@ -150,21 +147,7 @@ static __init void omapl138_hawk_mmc_init(void) return; } - ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN, - GPIOF_DIR_IN, "MMC CD"); - if (ret < 0) { - pr_warn("%s: can not open GPIO %d\n", - __func__, DA850_HAWK_MMCSD_CD_PIN); - return; - } - - ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN, - GPIOF_DIR_IN, "MMC WP"); - if (ret < 0) { - pr_warn("%s: can not open GPIO %d\n", - __func__, DA850_HAWK_MMCSD_WP_PIN); - goto mmc_setup_wp_fail; - } + gpiod_add_lookup_table(&mmc_gpios_table); ret = da8xx_register_mmcsd0(&da850_mmc_config); if (ret) { @@ -175,9 +158,7 @@ static __init void omapl138_hawk_mmc_init(void) return; mmc_setup_mmcsd_fail: - gpio_free(DA850_HAWK_MMCSD_WP_PIN); -mmc_setup_wp_fail: - gpio_free(DA850_HAWK_MMCSD_CD_PIN); + gpiod_remove_lookup_table(&mmc_gpios_table); } static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id); @@ -243,7 +224,6 @@ static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id) static __init void omapl138_hawk_usb_init(void) { int ret; - u32 cfgchip2; ret = davinci_cfg_reg_list(da850_hawk_usb11_pins); if (ret) { @@ -251,12 +231,20 @@ static __init void omapl138_hawk_usb_init(void) return; } - /* Setup the Ref. clock frequency for the HAWK at 24 MHz. */ + ret = da8xx_register_usb20_phy_clk(false); + if (ret) + pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n", + __func__, ret); - cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - cfgchip2 &= ~CFGCHIP2_REFFREQ; - cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; - __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + ret = da8xx_register_usb11_phy_clk(false); + if (ret) + pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n", + __func__, ret); + + ret = da8xx_register_usb_phy(); + if (ret) + pr_warn("%s: USB PHY registration failed: %d\n", + __func__, ret); ret = gpio_request_one(DA850_USB1_VBUS_PIN, GPIOF_DIR_OUT, "USB1 VBUS"); @@ -292,6 +280,10 @@ static __init void omapl138_hawk_init(void) { int ret; + ret = da8xx_register_cfgchip(); + if (ret) + pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); + ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); @@ -317,6 +309,8 @@ static __init void omapl138_hawk_init(void) if (ret) pr_warn("%s: dsp/rproc registration failed: %d\n", __func__, ret); + + regulator_has_full_constraints(); } #ifdef CONFIG_SERIAL_8250_CONSOLE diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index df42c93a93d6..f5dce9b4e617 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -31,10 +31,10 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); -static void __clk_enable(struct clk *clk) +void davinci_clk_enable(struct clk *clk) { if (clk->parent) - __clk_enable(clk->parent); + davinci_clk_enable(clk->parent); if (clk->usecount++ == 0) { if (clk->flags & CLK_PSC) davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, @@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk) } } -static void __clk_disable(struct clk *clk) +void davinci_clk_disable(struct clk *clk) { if (WARN_ON(clk->usecount == 0)) return; @@ -56,7 +56,7 @@ static void __clk_disable(struct clk *clk) clk->clk_disable(clk); } if (clk->parent) - __clk_disable(clk->parent); + davinci_clk_disable(clk->parent); } int davinci_clk_reset(struct clk *clk, bool reset) @@ -103,7 +103,7 @@ int clk_enable(struct clk *clk) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); - __clk_enable(clk); + davinci_clk_enable(clk); spin_unlock_irqrestore(&clockfw_lock, flags); return 0; @@ -118,7 +118,7 @@ void clk_disable(struct clk *clk) return; spin_lock_irqsave(&clockfw_lock, flags); - __clk_disable(clk); + davinci_clk_disable(clk); spin_unlock_irqrestore(&clockfw_lock, flags); } EXPORT_SYMBOL(clk_disable); diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index e2a5437a1aee..fa2b83752e03 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -132,6 +132,8 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); int davinci_set_refclk_rate(unsigned long rate); int davinci_simple_set_rate(struct clk *clk, unsigned long rate); int davinci_clk_reset(struct clk *clk, bool reset); +void davinci_clk_enable(struct clk *clk); +void davinci_clk_disable(struct clk *clk); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index 049025f6d531..9f9fbfa6da0d 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -118,6 +118,5 @@ err: void __init davinci_init_late(void) { davinci_cpufreq_init(); - davinci_pm_init(); davinci_clk_disable_unused(); } diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 426fd7477357..073c458d0c67 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -412,7 +412,7 @@ static struct clk_lookup da830_clks[] = { CLK("davinci-mcasp.0", NULL, &mcasp0_clk), CLK("davinci-mcasp.1", NULL, &mcasp1_clk), CLK("davinci-mcasp.2", NULL, &mcasp2_clk), - CLK(NULL, "usb20", &usb20_clk), + CLK("musb-da8xx", "usb20", &usb20_clk), CLK(NULL, "aemif", &aemif_clk), CLK(NULL, "aintc", &aintc_clk), CLK(NULL, "secu_mgr", &secu_mgr_clk), @@ -420,7 +420,7 @@ static struct clk_lookup da830_clks[] = { CLK("davinci_mdio.0", "fck", &emac_clk), CLK(NULL, "gpio", &gpio_clk), CLK("i2c_davinci.2", NULL, &i2c1_clk), - CLK(NULL, "usb11", &usb11_clk), + CLK("ohci-da8xx", "usb11", &usb11_clk), CLK(NULL, "emif3", &emif3_clk), CLK(NULL, "arm", &arm_clk), CLK(NULL, "rmii", &rmii_clk), diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index ed3d0e9f72ac..1d873d15b545 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -319,6 +319,16 @@ static struct clk emac_clk = { .gpsc = 1, }; +/* + * In order to avoid adding the emac_clk to the clock lookup table twice (and + * screwing up the linked list in the process) create a separate clock for + * mdio inheriting the rate from emac_clk. + */ +static struct clk mdio_clk = { + .name = "mdio", + .parent = &emac_clk, +}; + static struct clk mcasp_clk = { .name = "mcasp", .parent = &async3_clk, @@ -367,6 +377,16 @@ static struct clk aemif_clk = { .flags = ALWAYS_ENABLED, }; +/* + * In order to avoid adding the aemif_clk to the clock lookup table twice (and + * screwing up the linked list in the process) create a separate clock for + * nand inheriting the rate from aemif_clk. + */ +static struct clk aemif_nand_clk = { + .name = "nand", + .parent = &aemif_clk, +}; + static struct clk usb11_clk = { .name = "usb11", .parent = &pll0_sysclk4, @@ -424,6 +444,16 @@ static struct clk ehrpwm_clk = { .gpsc = 1, }; +static struct clk ehrpwm0_clk = { + .name = "ehrpwm0", + .parent = &ehrpwm_clk, +}; + +static struct clk ehrpwm1_clk = { + .name = "ehrpwm1", + .parent = &ehrpwm_clk, +}; + #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) static void ehrpwm_tblck_enable(struct clk *clk) @@ -451,6 +481,16 @@ static struct clk ehrpwm_tbclk = { .clk_disable = ehrpwm_tblck_disable, }; +static struct clk ehrpwm0_tbclk = { + .name = "ehrpwm0_tbclk", + .parent = &ehrpwm_tbclk, +}; + +static struct clk ehrpwm1_tbclk = { + .name = "ehrpwm1_tbclk", + .parent = &ehrpwm_tbclk, +}; + static struct clk ecap_clk = { .name = "ecap", .parent = &async3_clk, @@ -458,6 +498,21 @@ static struct clk ecap_clk = { .gpsc = 1, }; +static struct clk ecap0_clk = { + .name = "ecap0_clk", + .parent = &ecap_clk, +}; + +static struct clk ecap1_clk = { + .name = "ecap1_clk", + .parent = &ecap_clk, +}; + +static struct clk ecap2_clk = { + .name = "ecap2_clk", + .parent = &ecap_clk, +}; + static struct clk_lookup da850_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "pll0", &pll0_clk), @@ -494,7 +549,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "arm", &arm_clk), CLK(NULL, "rmii", &rmii_clk), CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), + CLK("davinci_mdio.0", "fck", &mdio_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk), CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk), @@ -502,17 +557,32 @@ static struct clk_lookup da850_clks[] = { CLK("da830-mmc.0", NULL, &mmcsd0_clk), CLK("da830-mmc.1", NULL, &mmcsd1_clk), CLK("ti-aemif", NULL, &aemif_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "usb11", &usb11_clk), - CLK(NULL, "usb20", &usb20_clk), + /* + * The only user of this clock is davinci_nand and it get's it through + * con_id. The nand node itself is created from within the aemif + * driver to guarantee that it's probed after the aemif timing + * parameters are configured. of_dev_auxdata is not accessible from + * the aemif driver and can't be passed to of_platform_populate(). For + * that reason we're leaving the dev_id here as NULL. + */ + CLK(NULL, "aemif", &aemif_nand_clk), + CLK("ohci-da8xx", "usb11", &usb11_clk), + CLK("musb-da8xx", "usb20", &usb20_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), CLK("vpif", NULL, &vpif_clk), CLK("ahci_da850", NULL, &sata_clk), CLK("davinci-rproc.0", NULL, &dsp_clk), - CLK("ehrpwm", "fck", &ehrpwm_clk), - CLK("ehrpwm", "tbclk", &ehrpwm_tbclk), - CLK("ecap", "fck", &ecap_clk), + CLK(NULL, NULL, &ehrpwm_clk), + CLK("ehrpwm.0", "fck", &ehrpwm0_clk), + CLK("ehrpwm.1", "fck", &ehrpwm1_clk), + CLK(NULL, NULL, &ehrpwm_tbclk), + CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk), + CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk), + CLK(NULL, NULL, &ecap_clk), + CLK("ecap.0", "fck", &ecap0_clk), + CLK("ecap.1", "fck", &ecap1_clk), + CLK("ecap.2", "fck", &ecap2_clk), CLK(NULL, NULL, NULL), }; @@ -1172,44 +1242,6 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate) } #endif -int __init da850_register_pm(struct platform_device *pdev) -{ - int ret; - struct davinci_pm_config *pdata = pdev->dev.platform_data; - - ret = davinci_cfg_reg(DA850_RTC_ALARM); - if (ret) - return ret; - - pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr(); - pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); - pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C; - - pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); - if (!pdata->cpupll_reg_base) - return -ENOMEM; - - pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); - if (!pdata->ddrpll_reg_base) { - ret = -ENOMEM; - goto no_ddrpll_mem; - } - - pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); - if (!pdata->ddrpsc_reg_base) { - ret = -ENOMEM; - goto no_ddrpsc_mem; - } - - return platform_device_register(pdev); - -no_ddrpsc_mem: - iounmap(pdata->ddrpll_reg_base); -no_ddrpll_mem: - iounmap(pdata->cpupll_reg_base); - return ret; -} - /* VPIF resource, platform data */ static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index c9f7e9274aa8..9ee44da6eb7b 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -23,11 +23,11 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL), OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL), OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), - OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL), - OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), + OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm.0", NULL), + OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm.1", NULL), + OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap.0", NULL), + OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap.1", NULL), + OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap.2", NULL), OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL), OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL), @@ -38,6 +38,10 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { NULL), OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL), OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL), + OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL), + OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL), + OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL), + OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL), {} }; @@ -45,7 +49,19 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { static void __init da850_init_machine(void) { + int ret; + + ret = da8xx_register_usb20_phy_clk(false); + if (ret) + pr_warn("%s: registering USB 2.0 PHY clock failed: %d", + __func__, ret); + ret = da8xx_register_usb11_phy_clk(false); + if (ret) + pr_warn("%s: registering USB 1.1 PHY clock failed: %d", + __func__, ret); + of_platform_default_populate(NULL, da850_auxdata_lookup, NULL); + davinci_pm_init(); } static const char *const da850_boards_compat[] __initconst = { diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index add3771d38f6..c2457b3fdb5f 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -11,6 +11,7 @@ * (at your option) any later version. */ #include +#include #include #include #include @@ -57,15 +58,6 @@ #define DA8XX_EMAC_RAM_OFFSET 0x0000 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K -#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) -#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) -#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) -#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) -#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) -#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) -#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) -#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) - void __iomem *da8xx_syscfg0_base; void __iomem *da8xx_syscfg1_base; @@ -964,16 +956,6 @@ static struct resource da8xx_spi0_resources[] = { .end = IRQ_DA8XX_SPINT0, .flags = IORESOURCE_IRQ, }, - [2] = { - .start = DA8XX_DMA_SPI0_RX, - .end = DA8XX_DMA_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DA8XX_DMA_SPI0_TX, - .end = DA8XX_DMA_SPI0_TX, - .flags = IORESOURCE_DMA, - }, }; static struct resource da8xx_spi1_resources[] = { @@ -987,16 +969,6 @@ static struct resource da8xx_spi1_resources[] = { .end = IRQ_DA8XX_SPINT1, .flags = IORESOURCE_IRQ, }, - [2] = { - .start = DA8XX_DMA_SPI1_RX, - .end = DA8XX_DMA_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DA8XX_DMA_SPI1_TX, - .end = DA8XX_DMA_SPI1_TX, - .flags = IORESOURCE_DMA, - }, }; static struct davinci_spi_platform_data da8xx_spi_pdata[] = { @@ -1089,3 +1061,30 @@ int __init da850_register_sata(unsigned long refclkpn) return platform_device_register(&da850_sata_device); } #endif + +static struct syscon_platform_data da8xx_cfgchip_platform_data = { + .label = "cfgchip", +}; + +static struct resource da8xx_cfgchip_resources[] = { + { + .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG, + .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da8xx_cfgchip_device = { + .name = "syscon", + .id = -1, + .dev = { + .platform_data = &da8xx_cfgchip_platform_data, + }, + .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources), + .resource = da8xx_cfgchip_resources, +}; + +int __init da8xx_register_cfgchip(void) +{ + return platform_device_register(&da8xx_cfgchip_device); +} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 67d26c5bda0b..3ae70f2909b0 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -36,9 +36,6 @@ #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD1_BASE 0x01D00000 -#define DAVINCI_DMA_MMCRXEVT 26 -#define DAVINCI_DMA_MMCTXEVT 27 - void __iomem *davinci_sysmod_base; void davinci_map_sysmod(void) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index d33322ddedab..bd50367f654e 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -397,14 +397,6 @@ static struct resource dm355_spi0_resources[] = { .start = IRQ_DM355_SPINT0_0, .flags = IORESOURCE_IRQ, }, - { - .start = 17, - .flags = IORESOURCE_DMA, - }, - { - .start = 16, - .flags = IORESOURCE_DMA, - }, }; static struct davinci_spi_platform_data dm355_spi0_pdata = { diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index ef3add999263..8be04ec95adf 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -660,14 +660,6 @@ static struct resource dm365_spi0_resources[] = { .start = IRQ_DM365_SPIINT0_0, .flags = IORESOURCE_IRQ, }, - { - .start = 17, - .flags = IORESOURCE_DMA, - }, - { - .start = 16, - .flags = IORESOURCE_DMA, - }, }; static struct platform_device dm365_spi0_device = { diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index f9f9713aacdd..85ff2183b6db 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -61,6 +61,7 @@ extern unsigned int da850_max_speed; #define DA8XX_CFGCHIP1_REG 0x180 #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 +#define DA8XX_CFGCHIP4_REG 0x18c #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) @@ -88,8 +89,12 @@ int da850_register_edma(struct edma_rsv_info *rsv[2]); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_spi_bus(int instance, unsigned num_chipselect); int da8xx_register_watchdog(void); +int da8xx_register_usb_phy(void); int da8xx_register_usb20(unsigned mA, unsigned potpgt); int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); +int da8xx_register_usb_refclkin(int rate); +int da8xx_register_usb20_phy_clk(bool use_usb_refclkin); +int da8xx_register_usb11_phy_clk(bool use_usb_refclkin); int da8xx_register_emac(void); int da8xx_register_uio_pruss(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); @@ -101,7 +106,6 @@ int da8xx_register_gpio(void *pdata); int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem *da8xx_get_mem_ctlr(void); -int da850_register_pm(struct platform_device *pdev); int da850_register_sata(unsigned long refclkpn); int da850_register_vpif(void); int da850_register_vpif_display @@ -113,6 +117,7 @@ void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); int da850_register_gpio(void); int da830_register_gpio(void); +int da8xx_register_cfgchip(void); extern struct platform_device da8xx_serial_device[]; extern struct emac_platform_data da8xx_emac_pdata; diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c index 8929569b1f8a..0afd201ab980 100644 --- a/arch/arm/mach-davinci/pm.c +++ b/arch/arm/mach-davinci/pm.c @@ -21,15 +21,22 @@ #include #include -#include "sram.h" +#include #include #include "clock.h" +#include "psc.h" +#include "sram.h" +#define DA850_PLL1_BASE 0x01e1a000 #define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF +#define DEEPSLEEP_SLEEPCOUNT 128 static void (*davinci_sram_suspend) (struct davinci_pm_config *); -static struct davinci_pm_config *pdata; +static struct davinci_pm_config pm_config = { + .sleepcount = DEEPSLEEP_SLEEPCOUNT, + .ddrpsc_num = DA8XX_LPSC1_EMIF3C, +}; static void davinci_sram_push(void *dest, void *src, unsigned int size) { @@ -41,58 +48,58 @@ static void davinci_pm_suspend(void) { unsigned val; - if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) { + if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { /* Switch CPU PLL to bypass mode */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); udelay(PLL_BYPASS_TIME); /* Powerdown CPU PLL */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val |= PLLCTL_PLLPWRDN; - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); } /* Configure sleep count in deep sleep register */ - val = __raw_readl(pdata->deepsleep_reg); + val = __raw_readl(pm_config.deepsleep_reg); val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, - val |= pdata->sleepcount; - __raw_writel(val, pdata->deepsleep_reg); + val |= pm_config.sleepcount; + __raw_writel(val, pm_config.deepsleep_reg); /* System goes to sleep in this call */ - davinci_sram_suspend(pdata); + davinci_sram_suspend(&pm_config); - if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) { + if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { /* put CPU PLL in reset */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val &= ~PLLCTL_PLLRST; - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); /* put CPU PLL in power down */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val &= ~PLLCTL_PLLPWRDN; - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); /* wait for CPU PLL reset */ udelay(PLL_RESET_TIME); /* bring CPU PLL out of reset */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val |= PLLCTL_PLLRST; - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); /* Wait for CPU PLL to lock */ udelay(PLL_LOCK_TIME); /* Remove CPU PLL from bypass mode */ - val = __raw_readl(pdata->cpupll_reg_base + PLLCTL); + val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); val &= ~PLLCTL_PLLENSRC; val |= PLLCTL_PLLEN; - __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); + __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); } } @@ -117,17 +124,36 @@ static const struct platform_suspend_ops davinci_pm_ops = { .valid = suspend_valid_only_mem, }; -static int __init davinci_pm_probe(struct platform_device *pdev) +int __init davinci_pm_init(void) { - pdata = pdev->dev.platform_data; - if (!pdata) { - dev_err(&pdev->dev, "cannot get platform data\n"); - return -ENOENT; + int ret; + + ret = davinci_cfg_reg(DA850_RTC_ALARM); + if (ret) + return ret; + + pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr(); + pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); + + pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); + if (!pm_config.cpupll_reg_base) + return -ENOMEM; + + pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); + if (!pm_config.ddrpll_reg_base) { + ret = -ENOMEM; + goto no_ddrpll_mem; + } + + pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); + if (!pm_config.ddrpsc_reg_base) { + ret = -ENOMEM; + goto no_ddrpsc_mem; } davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL); if (!davinci_sram_suspend) { - dev_err(&pdev->dev, "cannot allocate SRAM memory\n"); + pr_err("PM: cannot allocate SRAM memory\n"); return -ENOMEM; } @@ -136,23 +162,9 @@ static int __init davinci_pm_probe(struct platform_device *pdev) suspend_set_ops(&davinci_pm_ops); - return 0; -} - -static int __exit davinci_pm_remove(struct platform_device *pdev) -{ - sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz); - return 0; -} - -static struct platform_driver davinci_pm_driver = { - .driver = { - .name = "pm-davinci", - }, - .remove = __exit_p(davinci_pm_remove), -}; - -int __init davinci_pm_init(void) -{ - return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe); +no_ddrpsc_mem: + iounmap(pm_config.ddrpll_reg_base); +no_ddrpll_mem: + iounmap(pm_config.cpupll_reg_base); + return ret; } diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 6c18445a4639..034f865fe78e 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -268,7 +268,7 @@ static void __init timer_init(void) /* * clocksource */ -static cycle_t read_cycles(struct clocksource *cs) +static u64 read_cycles(struct clocksource *cs) { struct timer_s *t = &timers[TID_CLOCKSOURCE]; diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index f141f5171906..9a6af0bd5dc3 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -1,21 +1,46 @@ /* * DA8xx USB */ +#include +#include #include #include +#include +#include #include #include #include +#include #include #include #include #include +#include "clock.h" + #define DA8XX_USB0_BASE 0x01e00000 #define DA8XX_USB1_BASE 0x01e25000 -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) +static struct clk *usb20_clk; + +static struct platform_device da8xx_usb_phy = { + .name = "da8xx-usb-phy", + .id = -1, + .dev = { + /* + * Setting init_name so that clock lookup will work in + * da8xx_register_usb11_phy_clk() even if this device is not + * registered yet. + */ + .init_name = "da8xx-usb-phy", + }, +}; + +int __init da8xx_register_usb_phy(void) +{ + return platform_device_register(&da8xx_usb_phy); +} static struct musb_hdrc_config musb_config = { .multipoint = true, @@ -45,10 +70,15 @@ static struct resource da8xx_usb20_resources[] = { static u64 usb_dmamask = DMA_BIT_MASK(32); -static struct platform_device usb_dev = { +static struct platform_device da8xx_usb20_dev = { .name = "musb-da8xx", .id = -1, .dev = { + /* + * Setting init_name so that clock lookup will work in + * usb20_phy_clk_enable() even if this device is not registered. + */ + .init_name = "musb-da8xx", .platform_data = &usb_data, .dma_mask = &usb_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), @@ -62,18 +92,9 @@ int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) usb_data.power = mA > 510 ? 255 : mA / 2; usb_data.potpgt = (potpgt + 1) / 2; - return platform_device_register(&usb_dev); + return platform_device_register(&da8xx_usb20_dev); } -#else - -int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) -{ - return 0; -} - -#endif /* CONFIG_USB_MUSB_HDRC */ - static struct resource da8xx_usb11_resources[] = { [0] = { .start = DA8XX_USB1_BASE, @@ -90,8 +111,8 @@ static struct resource da8xx_usb11_resources[] = { static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); static struct platform_device da8xx_usb11_device = { - .name = "ohci", - .id = 0, + .name = "ohci-da8xx", + .id = -1, .dev = { .dma_mask = &da8xx_usb11_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), @@ -105,3 +126,230 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) da8xx_usb11_device.dev.platform_data = pdata; return platform_device_register(&da8xx_usb11_device); } + +static struct clk usb_refclkin = { + .name = "usb_refclkin", + .set_rate = davinci_simple_set_rate, +}; + +static struct clk_lookup usb_refclkin_lookup = + CLK(NULL, "usb_refclkin", &usb_refclkin); + +/** + * da8xx_register_usb_refclkin - register USB_REFCLKIN clock + * + * @rate: The clock rate in Hz + * + * This clock is only needed if the board provides an external USB_REFCLKIN + * signal, in which case it will be used as the parent of usb20_phy_clk and/or + * usb11_phy_clk. + */ +int __init da8xx_register_usb_refclkin(int rate) +{ + int ret; + + usb_refclkin.rate = rate; + ret = clk_register(&usb_refclkin); + if (ret) + return ret; + + clkdev_add(&usb_refclkin_lookup); + + return 0; +} + +static void usb20_phy_clk_enable(struct clk *clk) +{ + u32 val; + u32 timeout = 500000; /* 500 msec */ + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */ + davinci_clk_enable(usb20_clk); + + /* + * Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 + * host may use the PLL clock without USB 2.0 OTG being used. + */ + val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN); + val |= CFGCHIP2_PHY_PLLON; + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + while (--timeout) { + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + if (val & CFGCHIP2_PHYCLKGD) + goto done; + udelay(1); + } + + pr_err("Timeout waiting for USB 2.0 PHY clock good\n"); +done: + davinci_clk_disable(usb20_clk); +} + +static void usb20_phy_clk_disable(struct clk *clk) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + val |= CFGCHIP2_PHYPWRDN; + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); +} + +static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + /* Set the mux depending on the parent clock. */ + if (parent == &usb_refclkin) { + val &= ~CFGCHIP2_USB2PHYCLKMUX; + } else if (strcmp(parent->name, "pll0_aux_clk") == 0) { + val |= CFGCHIP2_USB2PHYCLKMUX; + } else { + pr_err("Bad parent on USB 2.0 PHY clock\n"); + return -EINVAL; + } + + /* reference frequency also comes from parent clock */ + val &= ~CFGCHIP2_REFFREQ_MASK; + switch (clk_get_rate(parent)) { + case 12000000: + val |= CFGCHIP2_REFFREQ_12MHZ; + break; + case 13000000: + val |= CFGCHIP2_REFFREQ_13MHZ; + break; + case 19200000: + val |= CFGCHIP2_REFFREQ_19_2MHZ; + break; + case 20000000: + val |= CFGCHIP2_REFFREQ_20MHZ; + break; + case 24000000: + val |= CFGCHIP2_REFFREQ_24MHZ; + break; + case 26000000: + val |= CFGCHIP2_REFFREQ_26MHZ; + break; + case 38400000: + val |= CFGCHIP2_REFFREQ_38_4MHZ; + break; + case 40000000: + val |= CFGCHIP2_REFFREQ_40MHZ; + break; + case 48000000: + val |= CFGCHIP2_REFFREQ_48MHZ; + break; + default: + pr_err("Bad parent clock rate on USB 2.0 PHY clock\n"); + return -EINVAL; + } + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + return 0; +} + +static struct clk usb20_phy_clk = { + .name = "usb20_phy", + .clk_enable = usb20_phy_clk_enable, + .clk_disable = usb20_phy_clk_disable, + .set_parent = usb20_phy_clk_set_parent, +}; + +static struct clk_lookup usb20_phy_clk_lookup = + CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk); + +/** + * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock + * + * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true + * or "pll0_aux" if false. + */ +int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin) +{ + struct clk *parent; + int ret; + + usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20"); + ret = PTR_ERR_OR_ZERO(usb20_clk); + if (ret) + return ret; + + parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux"); + ret = PTR_ERR_OR_ZERO(parent); + if (ret) { + clk_put(usb20_clk); + return ret; + } + + usb20_phy_clk.parent = parent; + ret = clk_register(&usb20_phy_clk); + if (!ret) + clkdev_add(&usb20_phy_clk_lookup); + + clk_put(parent); + + return ret; +} + +static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + /* Set the USB 1.1 PHY clock mux based on the parent clock. */ + if (parent == &usb20_phy_clk) { + val &= ~CFGCHIP2_USB1PHYCLKMUX; + } else if (parent == &usb_refclkin) { + val |= CFGCHIP2_USB1PHYCLKMUX; + } else { + pr_err("Bad parent on USB 1.1 PHY clock\n"); + return -EINVAL; + } + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + + return 0; +} + +static struct clk usb11_phy_clk = { + .name = "usb11_phy", + .set_parent = usb11_phy_clk_set_parent, +}; + +static struct clk_lookup usb11_phy_clk_lookup = + CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk); + +/** + * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock + * + * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true + * or "usb20_phy" if false. + */ +int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin) +{ + struct clk *parent; + int ret = 0; + + if (use_usb_refclkin) + parent = clk_get(NULL, "usb_refclkin"); + else + parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy"); + if (IS_ERR(parent)) + return PTR_ERR(parent); + + usb11_phy_clk.parent = parent; + ret = clk_register(&usb11_phy_clk); + if (!ret) + clkdev_add(&usb11_phy_clk_lookup); + + clk_put(parent); + + return ret; +} diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index e5f791145bd0..874cbc91b669 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -59,13 +59,13 @@ static u64 notrace ep93xx_read_sched_clock(void) return ret; } -cycle_t ep93xx_clocksource_read(struct clocksource *c) +u64 ep93xx_clocksource_read(struct clocksource *c) { u64 ret; ret = readl(EP93XX_TIMER4_VALUE_LOW); ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return (cycle_t) ret; + return (u64) ret; } static int ep93xx_clkevt_set_next_event(unsigned long next, diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 98ffe1e62ad5..a5d68411a037 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -385,36 +385,6 @@ fail: return pen_release != -1 ? ret : 0; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ - -static void __init exynos_smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - else - /* - * CPU Nodes are passed thru DT and set_cpu_possible - * is set by "arm_dt_init_cpu_maps". - */ - return; - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { int i; @@ -479,7 +449,6 @@ static void exynos_cpu_die(unsigned int cpu) #endif /* CONFIG_HOTPLUG_CPU */ const struct smp_operations exynos_smp_ops __initconst = { - .smp_init_cpus = exynos_smp_init_cpus, .smp_prepare_cpus = exynos_smp_prepare_cpus, .smp_secondary_init = exynos_secondary_init, .smp_boot_secondary = exynos_boot_secondary, diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 810edc78c817..75395a720e63 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -19,7 +19,7 @@ #include "common.h" -static cycle_t cksrc_dc21285_read(struct clocksource *cs) +static u64 cksrc_dc21285_read(struct clocksource *cs) { return cs->mask - *CSR_TIMER2_VALUE; } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9155b639c9aa..936c59d0e18b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -557,7 +557,6 @@ config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 select PINCTRL_VF610 - select PL310_ERRATA_769419 if CACHE_L2X0 help This enables support for Freescale Vybrid VF610 processor. diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index c4436d9c52ff..b09a2ec19267 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -43,7 +43,6 @@ int mx21_clocks_init(unsigned long lref, unsigned long fref); int mx27_clocks_init(unsigned long fref); int mx31_clocks_init(unsigned long fref); int mx35_clocks_init(void); -int mx31_clocks_init_dt(void); struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 62e6b4fb5370..668d74b72511 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -23,11 +23,6 @@ static const char * const imx31_dt_board_compat[] __initconst = { NULL }; -static void __init imx31_dt_timer_init(void) -{ - mx31_clocks_init_dt(); -} - /* FIXME: replace with DT binding */ static const struct resource imx31_rnga_res[] __initconst = { DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), @@ -43,7 +38,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, - .init_time = imx31_dt_timer_init, .init_machine = imx31_dt_mach_init, .dt_compat = imx31_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx1.c b/arch/arm/mach-imx/mach-imx1.c index de5ab8d88549..3a8406e45b65 100644 --- a/arch/arm/mach-imx/mach-imx1.c +++ b/arch/arm/mach-imx/mach-imx1.c @@ -37,7 +37,6 @@ static const char * const imx1_dt_board_compat[] __initconst = { }; DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)") - .map_io = debug_ll_io_init, .init_early = imx1_init_early, .init_irq = imx1_init_irq, .dt_compat = imx1_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 58a2b88233e6..6cb8a22b617d 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -89,6 +89,7 @@ static void __init imx6ul_init_late(void) static const char * const imx6ul_dt_compat[] __initconst = { "fsl,imx6ul", + "fsl,imx6ull", NULL, }; diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index db9621c718ec..699157759120 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -10,12 +10,16 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include +#include #include #include #include #include #include +#include +#include #include "common.h" @@ -27,8 +31,499 @@ #define BM_MMDC_MDMISC_DDR_TYPE 0x18 #define BP_MMDC_MDMISC_DDR_TYPE 0x3 +#define TOTAL_CYCLES 0x0 +#define BUSY_CYCLES 0x1 +#define READ_ACCESSES 0x2 +#define WRITE_ACCESSES 0x3 +#define READ_BYTES 0x4 +#define WRITE_BYTES 0x5 + +/* Enables, resets, freezes, overflow profiling*/ +#define DBG_DIS 0x0 +#define DBG_EN 0x1 +#define DBG_RST 0x2 +#define PRF_FRZ 0x4 +#define CYC_OVF 0x8 +#define PROFILE_SEL 0x10 + +#define MMDC_MADPCR0 0x410 +#define MMDC_MADPSR0 0x418 +#define MMDC_MADPSR1 0x41C +#define MMDC_MADPSR2 0x420 +#define MMDC_MADPSR3 0x424 +#define MMDC_MADPSR4 0x428 +#define MMDC_MADPSR5 0x42C + +#define MMDC_NUM_COUNTERS 6 + +#define MMDC_FLAG_PROFILE_SEL 0x1 + +#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) + +static enum cpuhp_state cpuhp_mmdc_state; static int ddr_type; +struct fsl_mmdc_devtype_data { + unsigned int flags; +}; + +static const struct fsl_mmdc_devtype_data imx6q_data = { +}; + +static const struct fsl_mmdc_devtype_data imx6qp_data = { + .flags = MMDC_FLAG_PROFILE_SEL, +}; + +static const struct of_device_id imx_mmdc_dt_ids[] = { + { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data}, + { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data}, + { /* sentinel */ } +}; + +#ifdef CONFIG_PERF_EVENTS + +static DEFINE_IDA(mmdc_ida); + +PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") +PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") +PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") +PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03") +PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") +PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); +PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05") +PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001"); + +struct mmdc_pmu { + struct pmu pmu; + void __iomem *mmdc_base; + cpumask_t cpu; + struct hrtimer hrtimer; + unsigned int active_events; + struct device *dev; + struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; + struct hlist_node node; + struct fsl_mmdc_devtype_data *devtype_data; +}; + +/* + * Polling period is set to one second, overflow of total-cycles (the fastest + * increasing counter) takes ten seconds so one second is safe + */ +static unsigned int mmdc_pmu_poll_period_us = 1000000; + +module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint, + S_IRUGO | S_IWUSR); + +static ktime_t mmdc_pmu_timer_period(void) +{ + return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000); +} + +static ssize_t mmdc_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev); + + return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu); +} + +static struct device_attribute mmdc_pmu_cpumask_attr = + __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL); + +static struct attribute *mmdc_pmu_cpumask_attrs[] = { + &mmdc_pmu_cpumask_attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_cpumask_attr_group = { + .attrs = mmdc_pmu_cpumask_attrs, +}; + +static struct attribute *mmdc_pmu_events_attrs[] = { + &mmdc_pmu_total_cycles.attr.attr, + &mmdc_pmu_busy_cycles.attr.attr, + &mmdc_pmu_read_accesses.attr.attr, + &mmdc_pmu_write_accesses.attr.attr, + &mmdc_pmu_read_bytes.attr.attr, + &mmdc_pmu_read_bytes_unit.attr.attr, + &mmdc_pmu_read_bytes_scale.attr.attr, + &mmdc_pmu_write_bytes.attr.attr, + &mmdc_pmu_write_bytes_unit.attr.attr, + &mmdc_pmu_write_bytes_scale.attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_events_attr_group = { + .name = "events", + .attrs = mmdc_pmu_events_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-63"); +static struct attribute *mmdc_pmu_format_attrs[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_format_attr_group = { + .name = "format", + .attrs = mmdc_pmu_format_attrs, +}; + +static const struct attribute_group *attr_groups[] = { + &mmdc_pmu_events_attr_group, + &mmdc_pmu_format_attr_group, + &mmdc_pmu_cpumask_attr_group, + NULL, +}; + +static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg) +{ + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + + switch (cfg) { + case TOTAL_CYCLES: + reg = mmdc_base + MMDC_MADPSR0; + break; + case BUSY_CYCLES: + reg = mmdc_base + MMDC_MADPSR1; + break; + case READ_ACCESSES: + reg = mmdc_base + MMDC_MADPSR2; + break; + case WRITE_ACCESSES: + reg = mmdc_base + MMDC_MADPSR3; + break; + case READ_BYTES: + reg = mmdc_base + MMDC_MADPSR4; + break; + case WRITE_BYTES: + reg = mmdc_base + MMDC_MADPSR5; + break; + default: + return WARN_ONCE(1, + "invalid configuration %d for mmdc counter", cfg); + } + return readl(reg); +} + +static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node); + int target; + + if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu)) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target); + cpumask_set_cpu(target, &pmu_mmdc->cpu); + + return 0; +} + +static bool mmdc_pmu_group_event_is_valid(struct perf_event *event, + struct pmu *pmu, + unsigned long *used_counters) +{ + int cfg = event->attr.config; + + if (is_software_event(event)) + return true; + + if (event->pmu != pmu) + return false; + + return !test_and_set_bit(cfg, used_counters); +} + +/* + * Each event has a single fixed-purpose counter, so we can only have a + * single active event for each at any point in time. Here we just check + * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW + * event numbers are valid. + */ +static bool mmdc_pmu_group_is_valid(struct perf_event *event) +{ + struct pmu *pmu = event->pmu; + struct perf_event *leader = event->group_leader; + struct perf_event *sibling; + unsigned long counter_mask = 0; + + set_bit(leader->attr.config, &counter_mask); + + if (event != leader) { + if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) + return false; + } + + list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) + return false; + } + + return true; +} + +static int mmdc_pmu_event_init(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EOPNOTSUPP; + + if (event->cpu < 0) { + dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); + return -EOPNOTSUPP; + } + + if (event->attr.exclude_user || + event->attr.exclude_kernel || + event->attr.exclude_hv || + event->attr.exclude_idle || + event->attr.exclude_host || + event->attr.exclude_guest || + event->attr.sample_period) + return -EINVAL; + + if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS) + return -EINVAL; + + if (!mmdc_pmu_group_is_valid(event)) + return -EINVAL; + + event->cpu = cpumask_first(&pmu_mmdc->cpu); + return 0; +} + +static void mmdc_pmu_event_update(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 delta, prev_raw_count, new_raw_count; + + do { + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = mmdc_pmu_read_counter(pmu_mmdc, + event->attr.config); + } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count); + + delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; + + local64_add(delta, &event->count); +} + +static void mmdc_pmu_event_start(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + void __iomem *mmdc_base, *reg; + u32 val; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + /* + * hrtimer is required because mmdc does not provide an interrupt so + * polling is necessary + */ + hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(), + HRTIMER_MODE_REL_PINNED); + + local64_set(&hwc->prev_count, 0); + + writel(DBG_RST, reg); + + val = DBG_EN; + if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) + val |= PROFILE_SEL; + + writel(val, reg); +} + +static int mmdc_pmu_event_add(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + int cfg = event->attr.config; + + if (flags & PERF_EF_START) + mmdc_pmu_event_start(event, flags); + + if (pmu_mmdc->mmdc_events[cfg] != NULL) + return -EAGAIN; + + pmu_mmdc->mmdc_events[cfg] = event; + pmu_mmdc->active_events++; + + local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg)); + + return 0; +} + +static void mmdc_pmu_event_stop(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + writel(PRF_FRZ, reg); + mmdc_pmu_event_update(event); +} + +static void mmdc_pmu_event_del(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + pmu_mmdc->mmdc_events[cfg] = NULL; + pmu_mmdc->active_events--; + + if (pmu_mmdc->active_events == 0) + hrtimer_cancel(&pmu_mmdc->hrtimer); + + mmdc_pmu_event_stop(event, PERF_EF_UPDATE); +} + +static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc) +{ + int i; + + for (i = 0; i < MMDC_NUM_COUNTERS; i++) { + struct perf_event *event = pmu_mmdc->mmdc_events[i]; + + if (event) + mmdc_pmu_event_update(event); + } +} + +static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) +{ + struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu, + hrtimer); + + mmdc_pmu_overflow_handler(pmu_mmdc); + hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period()); + + return HRTIMER_RESTART; +} + +static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, + void __iomem *mmdc_base, struct device *dev) +{ + int mmdc_num; + + *pmu_mmdc = (struct mmdc_pmu) { + .pmu = (struct pmu) { + .task_ctx_nr = perf_invalid_context, + .attr_groups = attr_groups, + .event_init = mmdc_pmu_event_init, + .add = mmdc_pmu_event_add, + .del = mmdc_pmu_event_del, + .start = mmdc_pmu_event_start, + .stop = mmdc_pmu_event_stop, + .read = mmdc_pmu_event_update, + }, + .mmdc_base = mmdc_base, + .dev = dev, + .active_events = 0, + }; + + mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); + + return mmdc_num; +} + +static int imx_mmdc_remove(struct platform_device *pdev) +{ + struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); + + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + perf_pmu_unregister(&pmu_mmdc->pmu); + kfree(pmu_mmdc); + return 0; +} + +static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base) +{ + struct mmdc_pmu *pmu_mmdc; + char *name; + int mmdc_num; + int ret; + const struct of_device_id *of_id = + of_match_device(imx_mmdc_dt_ids, &pdev->dev); + + pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL); + if (!pmu_mmdc) { + pr_err("failed to allocate PMU device!\n"); + return -ENOMEM; + } + + /* The first instance registers the hotplug state */ + if (!cpuhp_mmdc_state) { + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/arm/mmdc:online", NULL, + mmdc_pmu_offline_cpu); + if (ret < 0) { + pr_err("cpuhp_setup_state_multi failed\n"); + goto pmu_free; + } + cpuhp_mmdc_state = ret; + } + + mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (mmdc_num == 0) + name = "mmdc"; + else + name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", mmdc_num); + + pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; + + hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler; + + cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu); + + /* Register the pmu instance for cpu hotplug */ + cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + + ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1); + if (ret) + goto pmu_register_err; + + platform_set_drvdata(pdev, pmu_mmdc); + return 0; + +pmu_register_err: + pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + hrtimer_cancel(&pmu_mmdc->hrtimer); +pmu_free: + kfree(pmu_mmdc); + return ret; +} + +#else +#define imx_mmdc_remove NULL +#define imx_mmdc_perf_init(pdev, mmdc_base) 0 +#endif + static int imx_mmdc_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -62,7 +557,7 @@ static int imx_mmdc_probe(struct platform_device *pdev) return -EBUSY; } - return 0; + return imx_mmdc_perf_init(pdev, mmdc_base); } int imx_mmdc_get_ddr_type(void) @@ -70,17 +565,13 @@ int imx_mmdc_get_ddr_type(void) return ddr_type; } -static const struct of_device_id imx_mmdc_dt_ids[] = { - { .compatible = "fsl,imx6q-mmdc", }, - { /* sentinel */ } -}; - static struct platform_driver imx_mmdc_driver = { .driver = { .name = "imx-mmdc", .of_match_table = imx_mmdc_dt_ids, }, .probe = imx_mmdc_probe, + .remove = imx_mmdc_remove, }; static int __init imx_mmdc_init(void) diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 23b98fd414bf..a1af634f8709 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include @@ -37,11 +39,8 @@ #include "pci_v3.h" #include "lm.h" -/* Base address to the AP system controller */ -void __iomem *ap_syscon_base; -/* Base address to the external bus interface */ -static void __iomem *ebi_base; - +/* Regmap to the AP system controller */ +static struct regmap *ap_syscon_map; /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx @@ -125,6 +124,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, { unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; u32 phybase = dev->res.start; + int ret; if (phybase == INTEGRATOR_UART0_BASE) { /* UART0 */ @@ -146,8 +146,17 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, else ctrls |= dtr_mask; - __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); - __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); + ret = regmap_write(ap_syscon_map, + INTEGRATOR_SC_CTRLS_OFFSET, + ctrls); + if (ret) + pr_err("MODEM: unable to write PL010 UART CTRLS\n"); + + ret = regmap_write(ap_syscon_map, + INTEGRATOR_SC_CTRLC_OFFSET, + ctrlc); + if (ret) + pr_err("MODEM: unable to write PL010 UART CRTLC\n"); } struct amba_pl010_data ap_uart_data = { @@ -178,35 +187,32 @@ static const struct of_device_id ap_syscon_match[] = { { }, }; -static const struct of_device_id ebi_match[] = { - { .compatible = "arm,external-bus-interface"}, - { }, -}; - static void __init ap_init_of(void) { - unsigned long sc_dec; + u32 sc_dec; struct device_node *syscon; - struct device_node *ebi; + int ret; int i; + of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); + syscon = of_find_matching_node(NULL, ap_syscon_match); if (!syscon) return; - ebi = of_find_matching_node(NULL, ebi_match); - if (!ebi) + ap_syscon_map = syscon_node_to_regmap(syscon); + if (IS_ERR(ap_syscon_map)) { + pr_crit("could not find Integrator/AP system controller\n"); return; + } - ap_syscon_base = of_iomap(syscon, 0); - if (!ap_syscon_base) - return; - ebi_base = of_iomap(ebi, 0); - if (!ebi_base) + ret = regmap_read(ap_syscon_map, + INTEGRATOR_SC_DEC_OFFSET, + &sc_dec); + if (ret) { + pr_crit("could not read from Integrator/AP syscon\n"); return; + } - of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); - - sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); for (i = 0; i < 4; i++) { struct lm_device *lmdev; diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index c702cc4092de..bd9b43c8004e 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 26874f608ca9..846e033c56fa 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include @@ -493,7 +493,7 @@ static u64 notrace ixp4xx_read_sched_clock(void) * clocksource */ -static cycle_t ixp4xx_clocksource_read(struct clocksource *c) +static u64 ixp4xx_clocksource_read(struct clocksource *c) { return *IXP4XX_OSTS; } diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index 43ee06d3abe5..b3bd0e137f6d 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -26,7 +26,6 @@ #include #include #include -#include #include diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h deleted file mode 100644 index c0a8434307f7..000000000000 --- a/arch/arm/mach-lpc32xx/clock.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/clock.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __LPC32XX_CLOCK_H -#define __LPC32XX_CLOCK_H - -struct clk { - struct list_head node; - struct clk *parent; - u32 rate; - u32 usecount; - - int (*set_rate) (struct clk *, unsigned long); - unsigned long (*round_rate) (struct clk *, unsigned long); - unsigned long (*get_rate) (struct clk *clk); - int (*enable) (struct clk *, int); - - /* Register address and bit mask for simple clocks */ - void __iomem *enable_reg; - u32 enable_mask; -}; - -#endif diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 30c9e64fc65b..02575c2444e4 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -24,7 +24,6 @@ /* * Other arch specific structures and functions */ -extern void __init lpc32xx_init_irq(void); extern void __init lpc32xx_map_io(void); extern void __init lpc32xx_serial_init(void); diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h deleted file mode 100644 index 00190535df90..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/irqs.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/irqs.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARM_ARCH_IRQS_H -#define __ASM_ARM_ARCH_IRQS_H - -#define LPC32XX_SIC1_IRQ(n) (32 + (n)) -#define LPC32XX_SIC2_IRQ(n) (64 + (n)) - -/* - * MIC interrupts - */ -#define IRQ_LPC32XX_SUB1IRQ 0 -#define IRQ_LPC32XX_SUB2IRQ 1 -#define IRQ_LPC32XX_PWM3 3 -#define IRQ_LPC32XX_PWM4 4 -#define IRQ_LPC32XX_HSTIMER 5 -#define IRQ_LPC32XX_WATCH 6 -#define IRQ_LPC32XX_UART_IIR3 7 -#define IRQ_LPC32XX_UART_IIR4 8 -#define IRQ_LPC32XX_UART_IIR5 9 -#define IRQ_LPC32XX_UART_IIR6 10 -#define IRQ_LPC32XX_FLASH 11 -#define IRQ_LPC32XX_SD1 13 -#define IRQ_LPC32XX_LCD 14 -#define IRQ_LPC32XX_SD0 15 -#define IRQ_LPC32XX_TIMER0 16 -#define IRQ_LPC32XX_TIMER1 17 -#define IRQ_LPC32XX_TIMER2 18 -#define IRQ_LPC32XX_TIMER3 19 -#define IRQ_LPC32XX_SSP0 20 -#define IRQ_LPC32XX_SSP1 21 -#define IRQ_LPC32XX_I2S0 22 -#define IRQ_LPC32XX_I2S1 23 -#define IRQ_LPC32XX_UART_IIR7 24 -#define IRQ_LPC32XX_UART_IIR2 25 -#define IRQ_LPC32XX_UART_IIR1 26 -#define IRQ_LPC32XX_MSTIMER 27 -#define IRQ_LPC32XX_DMA 28 -#define IRQ_LPC32XX_ETHERNET 29 -#define IRQ_LPC32XX_SUB1FIQ 30 -#define IRQ_LPC32XX_SUB2FIQ 31 - -/* - * SIC1 interrupts start at offset 32 - */ -#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) -#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) -#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) -#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) -#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) -#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) -#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12) -#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13) -#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14) -#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17) -#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18) -#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19) -#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20) -#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22) -#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23) -#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24) -#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25) -#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26) -#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27) -#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28) -#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29) -#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30) -#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31) - -/* - * SIC2 interrupts start at offset 64 - */ -#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0) -#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1) -#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2) -#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3) -#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4) -#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5) -#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6) -#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7) -#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8) -#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9) -#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10) -#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11) -#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12) -#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15) -#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18) -#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19) -#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20) -#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22) -#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23) -#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24) -#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25) -#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26) -#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27) -#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28) -#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31) - -#define LPC32XX_NR_IRQS 96 - -#endif diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 0e4cbbe980eb..6c52bd32610e 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index 207e81275ff0..62471570d586 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -73,7 +73,6 @@ #include #include #include "common.h" -#include "clock.h" #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 21164605b83f..dadae67d79b7 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,4 +1,2 @@ -ifeq ($(CONFIG_SMP),y) -obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o -endif -obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o +obj-$(CONFIG_SMP) += platsmp.o +obj-y += mediatek.o diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 3c2c92aaa0ae..96ad1db0b04b 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -144,7 +144,7 @@ static struct clock_event_device ckevt = { .set_state_oneshot = timer_set_shutdown, }; -static cycle_t clksrc_read(struct clocksource *cs) +static u64 clksrc_read(struct clocksource *cs) { return timer_read(); } diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index ae2a018b9305..8f8748a0c84f 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -148,7 +148,7 @@ static void __init armada_370_coherency_init(struct device_node *np) of_node_put(cpu_config_np); cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY, - "AP_ARM_MVEBU_COHERENCY", + "arm/mvebu/coherency:starting", armada_xp_clear_l2_starting, NULL); exit: set_cpu_coherent(); diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index afb809509140..45c6b733c881 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -31,6 +31,32 @@ config ARCH_OMAP16XX select ARCH_OMAP_OTG select CPU_ARM926T +config OMAP_MUX + bool "OMAP multiplexing support" + depends on ARCH_OMAP + default y + help + Pin multiplexing support for OMAP boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. + +config OMAP_MUX_DEBUG + bool "Multiplexing debug output" + depends on OMAP_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. + +config OMAP_MUX_WARNINGS + bool "Warn about pins the bootloader didn't set up" + depends on OMAP_MUX + default y + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect OMAP_MUX for your product. + comment "OMAP Board Type" depends on ARCH_OMAP1 diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 82887d645a6a..32f6c53367bf 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -19,6 +19,7 @@ * */ +#include #include #include #include "soc.h" @@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, return platform_device_register(pdev); } +#define OMAP_I2C_MAX_CONTROLLERS 4 +static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; + +#define OMAP_I2C_CMDLINE_SETUP (BIT(31)) + +/** + * omap_i2c_bus_setup - Process command line options for the I2C bus speed + * @str: String of options + * + * This function allow to override the default I2C bus speed for given I2C + * bus with a command line option. + * + * Format: i2c_bus=bus_id,clkrate (in kHz) + * + * Returns 1 on success, 0 otherwise. + */ +static int __init omap_i2c_bus_setup(char *str) +{ + int ints[3]; + + get_options(str, 3, ints); + if (ints[0] < 2 || ints[1] < 1 || + ints[1] > OMAP_I2C_MAX_CONTROLLERS) + return 0; + i2c_pdata[ints[1] - 1].clkrate = ints[2]; + i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP; + + return 1; +} +__setup("i2c_bus=", omap_i2c_bus_setup); + +/* + * Register busses defined in command line but that are not registered with + * omap_register_i2c_bus from board initialization code. + */ +int __init omap_register_i2c_bus_cmdline(void) +{ + int i, err = 0; + + for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++) + if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) { + i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; + err = omap_i2c_add_bus(&i2c_pdata[i], i + 1); + if (err) + goto out; + } + +out: + return err; +} + +/** + * omap_register_i2c_bus - register I2C bus with device descriptors + * @bus_id: bus id counting from number 1 + * @clkrate: clock rate of the bus in kHz + * @info: pointer into I2C device descriptor table or NULL + * @len: number of descriptors in the table + * + * Returns 0 on success or an error code. + */ +int __init omap_register_i2c_bus(int bus_id, u32 clkrate, + struct i2c_board_info const *info, + unsigned len) +{ + int err; + + BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS); + + if (info) { + err = i2c_register_board_info(bus_id, info, len); + if (err) + return err; + } + + if (!i2c_pdata[bus_id - 1].clkrate) + i2c_pdata[bus_id - 1].clkrate = clkrate; + + i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; + + return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id); +} + static int __init omap_i2c_cmdline(void) { return omap_register_i2c_bus_cmdline(); diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 5b37ec29996e..093458b62c8d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -6,8 +6,8 @@ ccflags-y := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-omap/include # Common support -obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ +obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \ + common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ omap_device.o omap-headsmp.o sram.o drm.o hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ @@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o -# Pin multiplexing -obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o - # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o @@ -80,7 +77,7 @@ endif # Power Management omap-4-5-pm-common = omap-mpuss-lowpower.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) -obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common) obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o ifeq ($(CONFIG_PM),y) @@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o # Platform specific device init code -omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o -omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o -obj-y += $(omap-flash-y) $(omap-flash-m) - omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) -obj-y += usb-musb.o obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o -obj-y += usb-host.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o obj-y += $(onenand-m) $(onenand-y) nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o obj-y += $(nand-m) $(nand-y) - -smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o -obj-y += $(smsc911x-m) $(smsc911x-y) - -obj-y += common-board-devices.o twl-common.o dss-common.o diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c deleted file mode 100644 index 2188dc30e232..000000000000 --- a/arch/arm/mach-omap2/board-flash.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * board-flash.c - * Modified from mach-omap2/board-3430sdp-flash.c - * - * Copyright (C) 2009 Nokia Corporation - * Copyright (C) 2009 Texas Instruments - * - * Vimal Singh - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include "soc.h" -#include "common.h" -#include "board-flash.h" - -#define REG_FPGA_REV 0x10 -#define REG_FPGA_DIP_SWITCH_INPUT2 0x60 -#define MAX_SUPPORTED_GPMC_CONFIG 3 - -#define DEBUG_BASE 0x08000000 /* debug board */ - -/* various memory sizes */ -#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ -#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ - -static struct physmap_flash_data board_nor_data = { - .width = 2, -}; - -static struct resource board_nor_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device board_nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &board_nor_data, - }, - .num_resources = 1, - .resource = &board_nor_resource, -}; - -static void -__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) -{ - int err; - - board_nor_data.parts = nor_parts; - board_nor_data.nr_parts = nr_parts; - - /* Configure start address and size of NOR device */ - if (omap_rev() >= OMAP3430_REV_ES1_0) { - err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, - (unsigned long *)&board_nor_resource.start); - board_nor_resource.end = board_nor_resource.start - + FLASH_SIZE_SDPV2 - 1; - } else { - err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, - (unsigned long *)&board_nor_resource.start); - board_nor_resource.end = board_nor_resource.start - + FLASH_SIZE_SDPV1 - 1; - } - if (err < 0) { - pr_err("NOR: Can't request GPMC CS\n"); - return; - } - if (platform_device_register(&board_nor_device) < 0) - pr_err("Unable to register NOR device\n"); -} - -#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) -static struct omap_onenand_platform_data board_onenand_data = { - .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ -}; - -void -__init board_onenand_init(struct mtd_partition *onenand_parts, - u8 nr_parts, u8 cs) -{ - board_onenand_data.cs = cs; - board_onenand_data.parts = onenand_parts; - board_onenand_data.nr_parts = nr_parts; - - gpmc_onenand_init(&board_onenand_data); -} -#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */ - -#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) - -/* Note that all values in this struct are in nanoseconds */ -struct gpmc_timings nand_default_timings[1] = { - { - .sync_clk = 0, - - .cs_on = 0, - .cs_rd_off = 36, - .cs_wr_off = 36, - - .we_on = 6, - .oe_on = 6, - - .adv_on = 6, - .adv_rd_off = 24, - .adv_wr_off = 36, - - .we_off = 30, - .oe_off = 48, - - .access = 54, - .rd_cycle = 72, - .wr_cycle = 72, - - .wr_access = 30, - .wr_data_mux_bus = 0, - }, -}; - -static struct omap_nand_platform_data board_nand_data; - -void -__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, - int nand_type, struct gpmc_timings *gpmc_t) -{ - board_nand_data.cs = cs; - board_nand_data.parts = nand_parts; - board_nand_data.nr_parts = nr_parts; - board_nand_data.devsize = nand_type; - - board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW; - gpmc_nand_init(&board_nand_data, gpmc_t); -} -#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */ - -/** - * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get - * the various cs values. - */ -static u8 get_gpmc0_type(void) -{ - u8 cs = 0; - void __iomem *fpga_map_addr; - - fpga_map_addr = ioremap(DEBUG_BASE, 4096); - if (!fpga_map_addr) - return -ENOMEM; - - if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV))) - /* we dont have an DEBUG FPGA??? */ - /* Depend on #defines!! default to strata boot return param */ - goto unmap; - - /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ - cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; - - /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ - if (omap_rev() >= OMAP3430_REV_ES1_0) - /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ - cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | - ((cs & 2) << 1) | ((cs & 1) << 3); - else - /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ - cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); -unmap: - iounmap(fpga_map_addr); - return cs; -} - -/** - * board_flash_init - Identify devices connected to GPMC and register. - * - * @return - void. - */ -void __init board_flash_init(struct flash_partitions partition_info[], - char chip_sel_board[][GPMC_CS_NUM], int nand_type) -{ - u8 cs = 0; - u8 norcs = GPMC_CS_NUM + 1; - u8 nandcs = GPMC_CS_NUM + 1; - u8 onenandcs = GPMC_CS_NUM + 1; - u8 idx; - unsigned char *config_sel = NULL; - - /* REVISIT: Is this return correct idx for 2430 SDP? - * for which cs configuration matches for 2430 SDP? - */ - idx = get_gpmc0_type(); - if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { - pr_err("%s: Invalid chip select: %d\n", __func__, cs); - return; - } - config_sel = (unsigned char *)(chip_sel_board[idx]); - - while (cs < GPMC_CS_NUM) { - switch (config_sel[cs]) { - case PDC_NOR: - if (norcs > GPMC_CS_NUM) - norcs = cs; - break; - case PDC_NAND: - if (nandcs > GPMC_CS_NUM) - nandcs = cs; - break; - case PDC_ONENAND: - if (onenandcs > GPMC_CS_NUM) - onenandcs = cs; - break; - } - cs++; - } - - if (norcs > GPMC_CS_NUM) - pr_err("NOR: Unable to find configuration in GPMC\n"); - else - board_nor_init(partition_info[0].parts, - partition_info[0].nr_parts, norcs); - - if (onenandcs > GPMC_CS_NUM) - pr_err("OneNAND: Unable to find configuration in GPMC\n"); - else - board_onenand_init(partition_info[1].parts, - partition_info[1].nr_parts, onenandcs); - - if (nandcs > GPMC_CS_NUM) - pr_err("NAND: Unable to find configuration in GPMC\n"); - else - board_nand_init(partition_info[2].parts, - partition_info[2].nr_parts, nandcs, - nand_type, nand_default_timings); -} diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h deleted file mode 100644 index 8b39eec07318..000000000000 --- a/arch/arm/mach-omap2/board-flash.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * board-sdp.h - * - * Information structures for SDP-specific board config data - * - * Copyright (C) 2009 Nokia Corporation - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -#define PDC_NOR 1 -#define PDC_NAND 2 -#define PDC_ONENAND 3 -#define DBG_MPDB 4 - -struct flash_partitions { - struct mtd_partition *parts; - int nr_parts; -}; - -#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) -extern void board_flash_init(struct flash_partitions [], - char chip_sel[][GPMC_CS_NUM], int nand_type); -#else -static inline void board_flash_init(struct flash_partitions part[], - char chip_sel[][GPMC_CS_NUM], int nand_type) -{ -} -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) -extern void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t); -extern struct gpmc_timings nand_default_timings[]; -#else -static inline void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t) -{ -} -#define nand_default_timings NULL -#endif - -#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) -extern void board_onenand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs); -#else -static inline void board_onenand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs) -{ -} -#endif diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index bab814d2f37d..dc9e34e670a2 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -30,8 +30,6 @@ static const struct of_device_id omap_dt_match_table[] __initconst = { static void __init omap_generic_init(void) { - omapdss_early_init_of(); - pdata_quirks_init(omap_dt_match_table); omapdss_init_of(); @@ -306,7 +304,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .init_late = am43xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, - .init_time = omap4_local_timer_init, + .init_time = omap3_gptimer_timer_init, .dt_compat = am43_boards_compat, .restart = omap44xx_restart, MACHINE_END @@ -341,6 +339,7 @@ static const char *const dra72x_boards_compat[] __initconst = { "ti,am5718", "ti,am5716", "ti,dra722", + "ti,dra718", NULL, }; diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index ef9ed36e8a61..6c679659cda5 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -409,7 +409,7 @@ static struct clockdomain l4sec_7xx_clkdm = { .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4sec_wkup_sleep_deps, .sleepdep_srcs = l4sec_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l3main1_7xx_clkdm = { diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c deleted file mode 100644 index 5388fcd3de72..000000000000 --- a/arch/arm/mach-omap2/common-board-devices.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * common-board-devices.c - * - * Copyright (C) 2011 CompuLab, Ltd. - * Author: Mike Rapoport - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include -#include -#include - -#include - -#include "common.h" -#include "common-board-devices.h" - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846) -static struct omap2_mcspi_device_config ads7846_mcspi_config = { - .turbo_mode = 0, -}; - -static struct ads7846_platform_data ads7846_config = { - .x_max = 0x0fff, - .y_max = 0x0fff, - .x_plate_ohms = 180, - .pressure_max = 255, - .debounce_max = 10, - .debounce_tol = 3, - .debounce_rep = 1, - .gpio_pendown = -EINVAL, - .keep_vref_on = 1, -}; - -static struct spi_board_info ads7846_spi_board_info __initdata = { - .modalias = "ads7846", - .bus_num = -EINVAL, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &ads7846_mcspi_config, - .irq = -EINVAL, - .platform_data = &ads7846_config, -}; - -void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, - struct ads7846_platform_data *board_pdata) -{ - struct spi_board_info *spi_bi = &ads7846_spi_board_info; - int err; - - /* - * If a board defines get_pendown_state() function, request the pendown - * GPIO and set the GPIO debounce time. - * If a board does not define the get_pendown_state() function, then - * the ads7846 driver will setup the pendown GPIO itself. - */ - if (board_pdata && board_pdata->get_pendown_state) { - err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); - if (err) { - pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); - return; - } - - if (gpio_debounce) - gpio_set_debounce(gpio_pendown, gpio_debounce); - - gpio_export(gpio_pendown, 0); - } - - spi_bi->bus_num = bus_num; - spi_bi->irq = gpio_to_irq(gpio_pendown); - - ads7846_config.gpio_pendown = gpio_pendown; - - if (board_pdata) { - board_pdata->gpio_pendown = gpio_pendown; - board_pdata->gpio_pendown_debounce = gpio_debounce; - spi_bi->platform_data = board_pdata; - } - - spi_register_board_info(&ads7846_spi_board_info, 1); -} -#else -void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, - struct ads7846_platform_data *board_pdata) -{ -} -#endif diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index 07c88ae083fb..335c7822fea1 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h @@ -3,15 +3,7 @@ #include #include -#include "twl-common.h" -#define NAND_BLOCK_SIZE SZ_128K - -struct mtd_partition; -struct ads7846_platform_data; - -void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, - struct ads7846_platform_data *board_pdata); void *n8x0_legacy_init(void); extern struct menelaus_platform_data n8x0_menelaus_platform_data; diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index deed42e1dd9c..c4f2ace91ea2 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void) } #endif -#ifdef CONFIG_OMAP_MUX -int omap_mux_late_init(void); -#else -static inline int omap_mux_late_init(void) -{ - return 0; -} -#endif - extern void omap2_init_common_infrastructure(void); extern void omap_init_time(void); @@ -262,8 +253,6 @@ extern void __iomem *omap4_get_sar_ram_base(void); extern void omap4_mpuss_early_init(void); extern void omap_do_wfi(void); -extern void omap4_secondary_startup(void); -extern void omap4460_secondary_startup(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ @@ -275,16 +264,11 @@ extern void omap4_cpu_die(unsigned int cpu); extern int omap4_cpu_kill(unsigned int cpu); extern const struct smp_operations omap4_smp_ops; - -extern void omap5_secondary_startup(void); -extern void omap5_secondary_hyp_startup(void); #endif #if defined(CONFIG_SMP) && defined(CONFIG_PM) extern int omap4_mpuss_init(void); extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); -extern int omap4_finish_suspend(unsigned long cpu_state); -extern void omap4_cpu_resume(void); extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); #else static inline int omap4_enter_lowpower(unsigned int cpu, @@ -305,14 +289,41 @@ static inline int omap4_mpuss_init(void) return 0; } +#endif + +#ifdef CONFIG_ARCH_OMAP4 +void omap4_secondary_startup(void); +void omap4460_secondary_startup(void); +int omap4_finish_suspend(unsigned long cpu_state); +void omap4_cpu_resume(void); +#else +static inline void omap4_secondary_startup(void) +{ +} + +static inline void omap4460_secondary_startup(void) +{ +} static inline int omap4_finish_suspend(unsigned long cpu_state) { return 0; } - static inline void omap4_cpu_resume(void) -{} +{ +} +#endif +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) +void omap5_secondary_startup(void); +void omap5_secondary_hyp_startup(void); +#else +static inline void omap5_secondary_startup(void) +{ +} + +static inline void omap5_secondary_hyp_startup(void) +{ +} #endif void pdata_quirks_init(const struct of_device_id *); @@ -332,7 +343,6 @@ extern int omap_dss_reset(struct omap_hwmod *); int omap_clk_init(void); int __init omapdss_init_of(void); -void __init omapdss_early_init_of(void); #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index fa138d4032b6..a8b291f00109 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -21,6 +21,7 @@ #include "common.h" #include "pm.h" #include "prm.h" +#include "soc.h" #include "clockdomain.h" #define MAX_CPUS 2 @@ -30,6 +31,7 @@ struct idle_statedata { u32 cpu_state; u32 mpu_logic_state; u32 mpu_state; + u32 mpu_state_vote; }; static struct idle_statedata omap4_idle_data[] = { @@ -50,12 +52,26 @@ static struct idle_statedata omap4_idle_data[] = { }, }; +static struct idle_statedata omap5_idle_data[] = { + { + .cpu_state = PWRDM_POWER_ON, + .mpu_state = PWRDM_POWER_ON, + .mpu_logic_state = PWRDM_POWER_ON, + }, + { + .cpu_state = PWRDM_POWER_RET, + .mpu_state = PWRDM_POWER_RET, + .mpu_logic_state = PWRDM_POWER_RET, + }, +}; + static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS]; static struct clockdomain *cpu_clkdm[MAX_CPUS]; static atomic_t abort_barrier; static bool cpu_done[MAX_CPUS]; static struct idle_statedata *state_ptr = &omap4_idle_data[0]; +static DEFINE_RAW_SPINLOCK(mpu_lock); /* Private functions */ @@ -77,6 +93,32 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev, return index; } +static int omap_enter_idle_smp(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + struct idle_statedata *cx = state_ptr + index; + unsigned long flag; + + raw_spin_lock_irqsave(&mpu_lock, flag); + cx->mpu_state_vote++; + if (cx->mpu_state_vote == num_online_cpus()) { + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); + omap_set_pwrdm_state(mpu_pd, cx->mpu_state); + } + raw_spin_unlock_irqrestore(&mpu_lock, flag); + + omap4_enter_lowpower(dev->cpu, cx->cpu_state); + + raw_spin_lock_irqsave(&mpu_lock, flag); + if (cx->mpu_state_vote == num_online_cpus()) + omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); + cx->mpu_state_vote--; + raw_spin_unlock_irqrestore(&mpu_lock, flag); + + return index; +} + static int omap_enter_idle_coupled(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -220,6 +262,32 @@ static struct cpuidle_driver omap4_idle_driver = { .safe_state_index = 0, }; +static struct cpuidle_driver omap5_idle_driver = { + .name = "omap5_idle", + .owner = THIS_MODULE, + .states = { + { + /* C1 - CPU0 ON + CPU1 ON + MPU ON */ + .exit_latency = 2 + 2, + .target_residency = 5, + .enter = omap_enter_idle_simple, + .name = "C1", + .desc = "CPUx WFI, MPUSS ON" + }, + { + /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */ + .exit_latency = 48 + 60, + .target_residency = 100, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = omap_enter_idle_smp, + .name = "C2", + .desc = "CPUx CSWR, MPUSS CSWR", + }, + }, + .state_count = ARRAY_SIZE(omap5_idle_data), + .safe_state_index = 0, +}; + /* Public functions */ /** @@ -230,6 +298,16 @@ static struct cpuidle_driver omap4_idle_driver = { */ int __init omap4_idle_init(void) { + struct cpuidle_driver *idle_driver; + + if (soc_is_omap54xx()) { + state_ptr = &omap5_idle_data[0]; + idle_driver = &omap5_idle_driver; + } else { + state_ptr = &omap4_idle_data[0]; + idle_driver = &omap4_idle_driver; + } + mpu_pd = pwrdm_lookup("mpu_pwrdm"); cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm"); cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm"); @@ -244,5 +322,5 @@ int __init omap4_idle_init(void) /* Configure the broadcast timer on each cpu */ on_each_cpu(omap_setup_broadcast_timer, NULL, 1); - return cpuidle_register(&omap4_idle_driver, cpu_online_mask); + return cpuidle_register(idle_driver, cpu_online_mask); } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 60a20f3b44de..3fdb94599184 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -30,7 +30,6 @@ #include "soc.h" #include "common.h" -#include "mux.h" #include "control.h" #include "display.h" diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 70b3eaf085e4..e71cca0950e9 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -565,11 +565,6 @@ int omap_dss_reset(struct omap_hwmod *oh) return r; } -void __init omapdss_early_init_of(void) -{ - -} - static const char * const omapdss_compat_names[] __initconst = { "ti,omap2-dss", "ti,omap3-dss", diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c deleted file mode 100644 index 1d583bc0b1a9..000000000000 --- a/arch/arm/mach-omap2/dss-common.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments, Inc.. - * Author: Tomi Valkeinen - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -/* - * NOTE: this is a transitional file to help with DT adaptation. - * This file will be removed when DSS supports DT. - */ - -#include -#include -#include - -#include -#include