drm/bridge: anx7625: send DPCD command to downstream
Send DPCD command to downstream before anx7625 power down, let downstream monitor enter into standby mode. Signed-off-by: Xin Ji <xji@analogixsemi.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220213103437.3363848-1-hsinyi@chromium.org
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@ -129,6 +129,23 @@ static int anx7625_reg_write(struct anx7625_data *ctx,
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return ret;
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}
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static int anx7625_reg_block_write(struct anx7625_data *ctx,
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struct i2c_client *client,
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u8 reg_addr, u8 len, u8 *buf)
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{
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int ret;
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struct device *dev = &client->dev;
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i2c_access_workaround(ctx, client);
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ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
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if (ret < 0)
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dev_err(dev, "write i2c block failed id=%x\n:%x",
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client->addr, reg_addr);
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return ret;
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}
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static int anx7625_write_or(struct anx7625_data *ctx,
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struct i2c_client *client,
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u8 offset, u8 mask)
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@ -214,8 +231,8 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
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return 0;
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}
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static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
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u32 address, u8 len, u8 *buf)
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static int anx7625_aux_dpcd_trans(struct anx7625_data *ctx, u8 op,
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u32 address, u8 len, u8 *buf)
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{
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struct device *dev = &ctx->client->dev;
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int ret;
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@ -231,8 +248,7 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
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addrm = (address >> 8) & 0xFF;
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addrh = (address >> 16) & 0xFF;
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cmd = DPCD_CMD(len, DPCD_READ);
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cmd = ((len - 1) << 4) | 0x09;
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cmd = DPCD_CMD(len, op);
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/* Set command and length */
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ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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@ -246,6 +262,9 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
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ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_ADDR_19_16, addrh);
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if (op == DP_AUX_NATIVE_WRITE)
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ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_BUFF_START, len, buf);
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/* Enable aux access */
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ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
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@ -255,14 +274,17 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
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return -EIO;
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}
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usleep_range(2000, 2100);
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ret = wait_aux_op_finish(ctx);
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if (ret) {
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dev_err(dev, "aux IO error: wait aux op finish.\n");
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return ret;
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}
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/* Write done */
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if (op == DP_AUX_NATIVE_WRITE)
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return 0;
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/* Read done, read out dpcd data */
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ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
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AP_AUX_BUFF_START, len, buf);
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if (ret < 0) {
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@ -845,7 +867,7 @@ static int anx7625_hdcp_enable(struct anx7625_data *ctx)
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}
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/* Read downstream capability */
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anx7625_aux_dpcd_read(ctx, 0x68028, 1, &bcap);
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anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap);
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if (!(bcap & 0x01)) {
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pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
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return 0;
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@ -918,6 +940,7 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
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{
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struct device *dev = &ctx->client->dev;
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int ret;
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u8 data;
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DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
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@ -929,6 +952,11 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
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ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
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ret |= anx7625_video_mute_control(ctx, 1);
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dev_dbg(dev, "notify downstream enter into standby\n");
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/* Downstream monitor enter into standby mode */
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data = 2;
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ret |= anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
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if (ret < 0)
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DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
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@ -242,8 +242,6 @@
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#define AP_AUX_COMMAND 0x27 /* com+len */
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#define LENGTH_SHIFT 4
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#define DPCD_READ 0x09
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#define DPCD_WRITE 0x08
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#define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))
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/* Bit 0&1: 3D video structure */
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