drm/amdgpu/pm: move additional logic into amdgpu_dpm_force_performance_level
This is part of the forced performance level. Move it from the sysfs handler into amdgpu_dpm_force_performance_level. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bcf19fdd50
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@ -692,16 +692,25 @@ void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
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amdgpu_dpm_compute_clocks(adev);
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amdgpu_dpm_compute_clocks(adev);
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}
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}
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enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev)
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static enum amd_dpm_forced_level amdgpu_dpm_get_performance_level_locked(struct amdgpu_device *adev)
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{
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{
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level level;
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mutex_lock(&adev->pm.mutex);
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if (pp_funcs->get_performance_level)
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if (pp_funcs->get_performance_level)
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level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);
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level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);
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else
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else
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level = adev->pm.dpm.forced_level;
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level = adev->pm.dpm.forced_level;
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return level;
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}
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enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev)
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{
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enum amd_dpm_forced_level level;
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mutex_lock(&adev->pm.mutex);
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level = amdgpu_dpm_get_performance_level_locked(adev);
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mutex_unlock(&adev->pm.mutex);
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mutex_unlock(&adev->pm.mutex);
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return level;
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return level;
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@ -711,6 +720,11 @@ int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
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enum amd_dpm_forced_level level)
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enum amd_dpm_forced_level level)
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{
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{
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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enum amd_dpm_forced_level current_level;
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uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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int ret = 0;
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int ret = 0;
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if (!pp_funcs->force_performance_level)
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if (!pp_funcs->force_performance_level)
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@ -723,6 +737,49 @@ int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
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goto out;
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goto out;
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}
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}
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current_level = amdgpu_dpm_get_performance_level_locked(adev);
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if (current_level == level) {
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ret = 0;
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goto out;
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}
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if (adev->asic_type == CHIP_RAVEN) {
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if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
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if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
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level == AMD_DPM_FORCED_LEVEL_MANUAL)
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amdgpu_gfx_off_ctrl(adev, false);
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else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL &&
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level != AMD_DPM_FORCED_LEVEL_MANUAL)
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amdgpu_gfx_off_ctrl(adev, true);
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}
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}
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if (!(current_level & profile_mode_mask) &&
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
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ret = -EINVAL;
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goto out;
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}
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if (!(current_level & profile_mode_mask) &&
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(level & profile_mode_mask)) {
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/* enter UMD Pstate */
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_UNGATE);
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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} else if ((current_level & profile_mode_mask) &&
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!(level & profile_mode_mask)) {
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/* exit UMD Pstate */
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_GATE);
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}
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if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,
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if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,
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level))
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level))
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ret = -EINVAL;
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ret = -EINVAL;
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@ -299,11 +299,6 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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struct amdgpu_device *adev = drm_to_adev(ddev);
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level level;
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enum amd_dpm_forced_level current_level;
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uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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int ret = 0;
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int ret = 0;
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if (amdgpu_in_reset(adev))
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if (amdgpu_in_reset(adev))
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@ -341,51 +336,6 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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return ret;
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return ret;
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}
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}
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current_level = amdgpu_dpm_get_performance_level(adev);
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if (current_level == level) {
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pm_runtime_mark_last_busy(ddev->dev);
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pm_runtime_put_autosuspend(ddev->dev);
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return count;
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}
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if (adev->asic_type == CHIP_RAVEN) {
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if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
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if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
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amdgpu_gfx_off_ctrl(adev, false);
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else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
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amdgpu_gfx_off_ctrl(adev, true);
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}
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}
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/* profile_exit setting is valid only when current mode is in profile mode */
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if (!(current_level & profile_mode_mask) &&
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
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pr_err("Currently not in any profile mode!\n");
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pm_runtime_mark_last_busy(ddev->dev);
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pm_runtime_put_autosuspend(ddev->dev);
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return -EINVAL;
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}
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if (!(current_level & profile_mode_mask) &&
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(level & profile_mode_mask)) {
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/* enter UMD Pstate */
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_UNGATE);
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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} else if ((current_level & profile_mode_mask) &&
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!(level & profile_mode_mask)) {
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/* exit UMD Pstate */
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amdgpu_device_ip_set_clockgating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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amdgpu_device_ip_set_powergating_state(adev,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_PG_STATE_GATE);
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}
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if (amdgpu_dpm_force_performance_level(adev, level)) {
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if (amdgpu_dpm_force_performance_level(adev, level)) {
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pm_runtime_mark_last_busy(ddev->dev);
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pm_runtime_mark_last_busy(ddev->dev);
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pm_runtime_put_autosuspend(ddev->dev);
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pm_runtime_put_autosuspend(ddev->dev);
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