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drm/sun4i: hdmi ddc clk: Fix size of m divider

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m divider in DDC clock register is 4 bits wide. Fix that.

Fixes: 9c5681011a ("drm/sun4i: Add HDMI support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20200413095457.1176754-1-jernej.skrabec@siol.net
This commit is contained in:
Jernej Skrabec 2020-04-13 11:54:57 +02:00 committed by Maxime Ripard
parent 968d81a64a
commit 54e1e06bcf
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
2 changed files with 2 additions and 2 deletions
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2
drivers/gpu/drm/sun4i/sun4i_hdmi.h
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@ -148,7 +148,7 @@
#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3
#define SUN4I_HDMI_DDC_CLK_REG 0x528
#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3)
#define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
#define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540

2
drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
View File

@ -33,7 +33,7 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
unsigned long best_rate = 0;
u8 best_m = 0, best_n = 0, _m, _n;
for (_m = 0; _m < 8; _m++) {
for (_m = 0; _m < 16; _m++) {
for (_n = 0; _n < 8; _n++) {
unsigned long tmp_rate;