drm/amd/pm: Clean up errors in sislands_smc.h
Fix the following errors reported by checkpatch:
ERROR: that open brace { should be on the previous line
Signed-off-by: Ran Sun <sunran001@208suo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ran Sun
Alex Deucher
parent
803fe2098a
commit
5502cf77e8
@ -29,8 +29,7 @@
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#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
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struct PP_SIslands_Dpm2PerfLevel
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{
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struct PP_SIslands_Dpm2PerfLevel {
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uint8_t MaxPS;
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uint8_t TgtAct;
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uint8_t MaxPS_StepInc;
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@ -47,8 +46,7 @@ struct PP_SIslands_Dpm2PerfLevel
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typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
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struct PP_SIslands_DPM2Status
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{
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struct PP_SIslands_DPM2Status {
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uint32_t dpm2Flags;
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uint8_t CurrPSkip;
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uint8_t CurrPSkipPowerShift;
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@ -68,8 +66,7 @@ struct PP_SIslands_DPM2Status
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typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
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struct PP_SIslands_DPM2Parameters
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{
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struct PP_SIslands_DPM2Parameters {
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uint32_t TDPLimit;
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uint32_t NearTDPLimit;
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uint32_t SafePowerLimit;
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@ -78,8 +75,7 @@ struct PP_SIslands_DPM2Parameters
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};
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typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
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struct PP_SIslands_PAPMStatus
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{
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struct PP_SIslands_PAPMStatus {
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uint32_t EstimatedDGPU_T;
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uint32_t EstimatedDGPU_P;
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uint32_t EstimatedAPU_T;
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@ -89,8 +85,7 @@ struct PP_SIslands_PAPMStatus
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};
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typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
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struct PP_SIslands_PAPMParameters
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{
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struct PP_SIslands_PAPMParameters {
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uint32_t NearTDPLimitTherm;
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uint32_t NearTDPLimitPAPM;
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uint32_t PlatformPowerLimit;
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@ -100,8 +95,7 @@ struct PP_SIslands_PAPMParameters
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};
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typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
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struct SISLANDS_SMC_SCLK_VALUE
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{
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struct SISLANDS_SMC_SCLK_VALUE {
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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@ -113,8 +107,7 @@ struct SISLANDS_SMC_SCLK_VALUE
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typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
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struct SISLANDS_SMC_MCLK_VALUE
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{
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struct SISLANDS_SMC_MCLK_VALUE {
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL_1;
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uint32_t vMPLL_FUNC_CNTL_2;
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@ -129,8 +122,7 @@ struct SISLANDS_SMC_MCLK_VALUE
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typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
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struct SISLANDS_SMC_VOLTAGE_VALUE
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{
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struct SISLANDS_SMC_VOLTAGE_VALUE {
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uint16_t value;
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uint8_t index;
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uint8_t phase_settings;
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@ -138,8 +130,7 @@ struct SISLANDS_SMC_VOLTAGE_VALUE
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typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
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struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
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{
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struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL {
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uint8_t ACIndex;
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uint8_t displayWatermark;
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uint8_t gen2PCIE;
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@ -180,8 +171,7 @@ struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
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typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
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struct SISLANDS_SMC_SWSTATE
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{
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struct SISLANDS_SMC_SWSTATE {
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uint8_t flags;
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uint8_t levelCount;
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uint8_t padding2;
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@ -205,8 +195,7 @@ struct SISLANDS_SMC_SWSTATE_SINGLE {
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#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
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#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
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struct SISLANDS_SMC_VOLTAGEMASKTABLE
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{
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struct SISLANDS_SMC_VOLTAGEMASKTABLE {
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uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
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};
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@ -214,8 +203,7 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
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#define SISLANDS_MAX_NO_VREG_STEPS 32
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struct SISLANDS_SMC_STATETABLE
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{
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struct SISLANDS_SMC_STATETABLE {
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uint8_t thermalProtectType;
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uint8_t systemFlags;
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uint8_t maxVDDCIndexInPPTable;
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@ -254,8 +242,7 @@ typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
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#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
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#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
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struct PP_SIslands_FanTable
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{
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struct PP_SIslands_FanTable {
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uint8_t fdo_mode;
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uint8_t padding;
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int16_t temp_min;
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@ -285,8 +272,7 @@ typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
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#define SMC_SISLANDS_SCALE_I 7
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#define SMC_SISLANDS_SCALE_R 12
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struct PP_SIslands_CacConfig
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{
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struct PP_SIslands_CacConfig {
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uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
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uint32_t lkge_lut_V0;
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uint32_t lkge_lut_Vstep;
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@ -308,23 +294,20 @@ typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
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#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
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#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
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struct SMC_SIslands_MCRegisterAddress
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{
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struct SMC_SIslands_MCRegisterAddress {
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
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struct SMC_SIslands_MCRegisterSet
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{
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struct SMC_SIslands_MCRegisterSet {
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uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
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struct SMC_SIslands_MCRegisters
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{
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struct SMC_SIslands_MCRegisters {
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uint8_t last;
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uint8_t reserved[3];
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SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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@ -333,8 +316,7 @@ struct SMC_SIslands_MCRegisters
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typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
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struct SMC_SIslands_MCArbDramTimingRegisterSet
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{
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struct SMC_SIslands_MCArbDramTimingRegisterSet {
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uint32_t mc_arb_dram_timing;
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uint32_t mc_arb_dram_timing2;
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uint8_t mc_arb_rfsh_rate;
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@ -344,8 +326,7 @@ struct SMC_SIslands_MCArbDramTimingRegisterSet
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typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
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struct SMC_SIslands_MCArbDramTimingRegisters
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{
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struct SMC_SIslands_MCArbDramTimingRegisters {
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uint8_t arb_current;
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uint8_t reserved[3];
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SMC_SIslands_MCArbDramTimingRegisterSet data[16];
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@ -353,8 +334,7 @@ struct SMC_SIslands_MCArbDramTimingRegisters
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typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
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struct SMC_SISLANDS_SPLL_DIV_TABLE
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{
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struct SMC_SISLANDS_SPLL_DIV_TABLE {
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uint32_t freq[256];
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uint32_t ss[256];
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};
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@ -374,8 +354,7 @@ typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
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#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
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struct Smc_SIslands_DTE_Configuration
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{
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struct Smc_SIslands_DTE_Configuration {
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uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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uint32_t K;
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