soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
Dessert the PHY reset when powering up the domain and put it back into reset when the domain is powered down. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -19,6 +19,8 @@
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#define GPR_REG0 0x0
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#define PCIE_CLOCK_MODULE_EN BIT(0)
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#define USB_CLOCK_MODULE_EN BIT(1)
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#define PCIE_PHY_APB_RST BIT(4)
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#define PCIE_PHY_INIT_RST BIT(5)
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struct imx8mp_blk_ctrl_domain;
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@ -81,6 +83,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
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case IMX8MP_HSIOBLK_PD_PCIE:
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regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
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break;
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case IMX8MP_HSIOBLK_PD_PCIE_PHY:
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regmap_set_bits(bc->regmap, GPR_REG0,
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PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
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break;
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default:
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break;
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}
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@ -96,6 +102,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
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case IMX8MP_HSIOBLK_PD_PCIE:
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regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
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break;
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case IMX8MP_HSIOBLK_PD_PCIE_PHY:
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regmap_clear_bits(bc->regmap, GPR_REG0,
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PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
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break;
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default:
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break;
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}
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