phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits
Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but does not clear them because of an incorrect write mask. This fixes up the issue by using a newly introduced constant for the write mask. While at it also introduces a proper GENMASK based constant for the PCIE30_PHY_MODE. Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -40,6 +40,8 @@
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#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
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#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
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#define RK3588_LANE_AGGREGATION BIT(2)
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#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
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#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
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struct rockchip_p3phy_ops;
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@ -149,14 +151,15 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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}
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reg = mode;
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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RK3588_PCIE30_PHY_MODE_EN | reg);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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if (!IS_ERR(priv->pipe_grf)) {
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reg = mode & 3;
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reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3);
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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(reg << 16) | reg);
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RK3588_PCIE1LN_SEL_EN | reg);
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}
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reset_control_deassert(priv->p30phy);
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