From 23b697ec85f3e7beed271b9f344c54821de2251e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 11 Sep 2023 16:47:47 -0500 Subject: [PATCH 01/12] arm64: dts: xilinx: Apply overlays to base dtbs DT overlays in tree need to be applied to a base DTB to validate they apply, to run schema checks on them, and to catch any errors at compile time. Defining the "-dtbs" variable is not enough as the combined DT must be added to dtbs-y. zynqmp-sck-kr-g-revA.dtso and zynqmp-sck-kr-g-revB.dtso don't exist, so drop them. Signed-off-by: Rob Herring Fixes: 45fe0dc4ea2e ("arm64: xilinx: Use zynqmp prefix for SOM dt overlays") Link: https://lore.kernel.org/r/20230911214751.2202913-1-robh@kernel.org Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 5e40c0b4fa0a..1068b0fa8e98 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -22,11 +22,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo - -zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo -zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo -zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo -zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb From 995d4ef062ec7faee419fce9afc230d76b510c9e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:12 +0200 Subject: [PATCH 02/12] arm64: xilinx: Do not use '_' in DT node names Character '_' not recommended in node name. Use '-' instead. Pretty much run seds below for node names. s/zynqmp_ipi/zynqmp-ipi/ s/nvmem_firmware/nvmem-firmware/ s/soc_revision/soc-revision/ s/si5335_/si5335-/ Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5137958580c85a35cf6aadd1c33a2f6bcf81a9e5.1695040866.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index d0091d3cb764..52f998c22538 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -123,13 +123,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335_0: si5335_0 { /* clk0_usb - u23 */ + si5335_0: si5335-0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335_1: si5335_1 { /* clk1_dp - u23 */ + si5335_1: si5335-1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index b61fc99cd911..e50e95cbe817 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -129,7 +129,7 @@ }; }; - zynqmp_ipi: zynqmp_ipi { + zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; @@ -194,12 +194,12 @@ mbox-names = "tx", "rx"; }; - nvmem_firmware { + nvmem-firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; - soc_revision: soc_revision@0 { + soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; }; From e0df41b82b1235c0a0f7bb8ec3f4341d9e69b72b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:13 +0200 Subject: [PATCH 03/12] arm64: xilinx: Use lower case for partition address Lower case should be used for register address. Issue is reported as: flash@0: partitions: Unevaluated properties are not allowed ('partition@22A0000' was unexpected) Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a96ac9a32a363b04958157548f290d480c21590c.1695040866.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index c4774a42d5fc..157dcb4a27a8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -222,9 +222,9 @@ label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; - partition@22A0000 { + partition@22a0000 { label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ }; }; }; From fb1580d51c4e16dbc389149ce015ab650cd6456e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:14 +0200 Subject: [PATCH 04/12] arm64: xilinx: Remove mt25qu512a compatible string from SOM mt25qu512a is not documented in DT binding that's why remove it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a1e975f5785dfb6eb04e8d5905dcaa7467ccd585.1695040866.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 157dcb4a27a8..cd5cd7f3b5ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -131,7 +131,7 @@ &qspi { /* MIO 0-5 - U143 */ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ - compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ + compatible = "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; From 2da2ac3c8d11bd57cf00d06985a3d9ca5969abae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:15 +0200 Subject: [PATCH 05/12] arm64: xilinx: Put ethernet phys to mdio node All zynqmp boards have been already described via mdio node that's why also convert zc1751. With using mdio node there is an option to add reset property for the whole mdio bus. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com --- .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 8 ++++-- .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 16 +++++++----- .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 8 ++++-- .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 26 +++++++++++-------- .../dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 8 ++++-- 5 files changed, 43 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index e821d55d8d5a..73491626e01e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -98,8 +98,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index b59e11316b4b..f767708fb50d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -91,12 +91,16 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 38b0a312171b..f553b317e6b2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -88,8 +88,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* VSC8211 */ + reg = <0>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6636e76545a5..6ec1d9813973 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -116,17 +116,21 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 0d2ea9c09a0a..b1857e17ab7e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -77,8 +77,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; From aa2fda88527259121efd4d44bf4128d2089e811a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:16 +0200 Subject: [PATCH 06/12] arm64: xilinx: Remove address/size-cells from flash node Partitions are described via fixed-partitions that's why there is no need to have address/size-cells in flash node. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c4447028f914e77b8c28640dc458b8409198ee30.1695040866.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index cd5cd7f3b5ce..51622896b1b1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -132,8 +132,6 @@ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; From eb2f7ff7de56a75159e960337711f501f3a42544 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Sep 2023 14:41:17 +0200 Subject: [PATCH 07/12] arm64: xilinx: Remove address/size-cells from gem nodes Some boards are using one mdio bus which holds multiple phys and also boards are using mdio node for bus description. That's why there are cases where address/size-cells are unnecessary which is also reported by make W=1 dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle it based on used description. Error log: /axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7252203d52af3ca8867764c8514affc4828e530d.1695040866.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e50e95cbe817..f5e1eb8cb3b7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -584,8 +584,6 @@ ; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; @@ -600,8 +598,6 @@ ; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; @@ -616,8 +612,6 @@ ; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; @@ -632,8 +626,6 @@ ; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; From 6f3ecaea6324e77ad9d8f4a27345f59f47b5025f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 23 Nov 2023 08:02:27 +0100 Subject: [PATCH 08/12] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc All Xilinx boards can hosts also soft core CPUs like MicroBlaze or MicroBlaze V (RISC-V ISA) that's why move boards description from arm folder to soc folder. Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings: soc: renesas: Move renesas.yaml from arm to soc"). Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek --- .../devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml | 2 +- MAINTAINERS | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) rename Documentation/devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml (98%) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml similarity index 98% rename from Documentation/devicetree/bindings/arm/xilinx.yaml rename to Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index f57ed0347894..95758deca325 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/xilinx.yaml# +$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Platforms diff --git a/MAINTAINERS b/MAINTAINERS index 97f51d5ec1cf..f3077b954130 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3020,6 +3020,7 @@ F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +F: Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ F: drivers/clocksource/timer-cadence-ttc.c From fc622c97d3e290437bb48d2fcb0987dd73234b90 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 23 Nov 2023 08:02:28 +0100 Subject: [PATCH 09/12] dt-bindings: soc: Add new board description for MicroBlaze V MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. Processor can be used with standard AMD/Xilinx IPs including interrupt controller and timer. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index 95758deca325..d4c0fe1fe435 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -132,6 +132,11 @@ properties: - const: xlnx,zynqmp-smk-k26 - const: xlnx,zynqmp + - description: AMD MicroBlaze V (QEMU) + items: + - const: qemu,mbv + - const: amd,mbv + additionalProperties: true ... From 6a10a19a6bd2fd8d27a510678bf87bd9408f51d8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 30 Nov 2023 10:59:15 +0100 Subject: [PATCH 10/12] arm64: zynqmp: Move fixed clock to / for kv260 fixed clock nodes can't be on the bus because they are missing reg property. That's why move them to root. And because it is root it is good to have it as the first node in a file. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 28 ++++++++--------- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 30 +++++++++---------- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index ae1b9b2bdbee..dee238739290 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -21,20 +21,7 @@ /dts-v1/; /plugin/; -&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - /* u14 - 0x40 - ina260 */ - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ -}; - -&amba { +&{/} { si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -72,6 +59,19 @@ }; }; +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + /* u14 - 0x40 - ina260 */ + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; + /* DP/USB 3.0 and SATA */ &psgtr { status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index b59e48be6465..73c5cb156caf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -16,21 +16,7 @@ /dts-v1/; /plugin/; -&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - /* u14 - 0x40 - ina260 */ - /* u43 - 0x2d - usb5744 */ - /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ -}; - -&amba { +&{/} { si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -68,6 +54,20 @@ }; }; +&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + /* u14 - 0x40 - ina260 */ + /* u43 - 0x2d - usb5744 */ + /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ +}; + /* DP/USB 3.0 */ &psgtr { status = "okay"; From 0bfb7950cc1975372c4c58c3d3f9803f05245d46 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 30 Nov 2023 10:59:16 +0100 Subject: [PATCH 11/12] arm64: zynqmp: Fix clock node name in kv260 cards node name shouldn't use '_' that's why convert it to '-'. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 12 ++++++------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index dee238739290..92f4190d564d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -22,37 +22,37 @@ /plugin/; &{/} { - si5332_0: si5332_0 { /* u17 */ + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332_1 { /* u17 */ + si5332_1: si5332-1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_2: si5332_2 { /* u17 */ + si5332_2: si5332-2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; - si5332_3: si5332_3 { /* u17 */ + si5332_3: si5332-3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; - si5332_4: si5332_4 { /* u17 */ + si5332_4: si5332-4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_5: si5332_5 { /* u17 */ + si5332_5: si5332-5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 73c5cb156caf..f88b71f5b07a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -17,37 +17,37 @@ /plugin/; &{/} { - si5332_0: si5332_0 { /* u17 */ + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332_1 { /* u17 */ + si5332_1: si5332-1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_2: si5332_2 { /* u17 */ + si5332_2: si5332-2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; - si5332_3: si5332_3 { /* u17 */ + si5332_3: si5332-3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; - si5332_4: si5332_4 { /* u17 */ + si5332_4: si5332-4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_5: si5332_5 { /* u17 */ + si5332_5: si5332-5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; From a98b6987de7d44cb621294041364f70285b3d2c6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 30 Nov 2023 10:19:15 +0100 Subject: [PATCH 12/12] arm64: zynqmp: Add missing destination mailbox compatible The commit 81186dc16101 ("dt-bindings: zynqmp: add destination mailbox compatible") make compatible string for child nodes mandatory that's why add it. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index f5e1eb8cb3b7..eaba466804bc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -141,6 +141,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; + compatible = "xlnx,zynqmp-ipi-dest-mailbox"; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>,