drm/amdgpu: add hdp version 6 functions
Unify hdp related function into hdp structure for hdp version 6. V2: Remove hdp invalidate function as hdp v6 doesn't have read cache. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
Alex Deucher
parent
068421b173
commit
563fcfbf31
@ -75,7 +75,7 @@ amdgpu-y += \
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vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
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vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \
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nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \
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nbio_v4_3.o
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nbio_v4_3.o hdp_v6_0.o
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# add DF block
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amdgpu-y += \
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@ -1188,7 +1188,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
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#define amdgpu_asic_flush_hdp(adev, r) \
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((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
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#define amdgpu_asic_invalidate_hdp(adev, r) \
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((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
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((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
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((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
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#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
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#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
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#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
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100
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
Normal file
100
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
Normal file
@ -0,0 +1,100 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "hdp_v6_0.h"
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#include "hdp/hdp_6_0_0_offset.h"
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#include "hdp/hdp_6_0_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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else
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t hdp_clk_cntl;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
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return;
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hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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if (enable) {
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hdp_clk_cntl &=
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~(uint32_t)
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(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
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} else {
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hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
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}
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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}
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static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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uint32_t tmp;
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/* AMD_CG_SUPPORT_HDP_MGCG */
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tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
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*flags |= AMD_CG_SUPPORT_HDP_MGCG;
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/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
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tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
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if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_LS;
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else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_DS;
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else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_SD;
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}
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const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
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.flush_hdp = hdp_v6_0_flush_hdp,
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.update_clock_gating = hdp_v6_0_update_clock_gating,
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.get_clock_gating_state = hdp_v6_0_get_clockgating_state,
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};
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31
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.h
Normal file
31
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.h
Normal file
@ -0,0 +1,31 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __HDP_V6_0_H__
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#define __HDP_V6_0_H__
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#include "soc15_common.h"
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extern const struct amdgpu_hdp_funcs hdp_v6_0_funcs;
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#endif
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