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Documentation: admin-guide: Add riscv sysctl_perf_user_access

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riscv now uses this sysctl so document its usage for this architecture.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
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Alexandre Ghiti 2023-08-02 10:03:26 +02:00 committed by Palmer Dabbelt
parent cc4c07c89a
commit 57972127b2
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1 changed files with 23 additions and 4 deletions
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27
Documentation/admin-guide/sysctl/kernel.rst
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@ -941,16 +941,35 @@ enabled, otherwise writing to this file will return ``-EBUSY``.
The default value is 8.
perf_user_access (arm64 only)
=================================
perf_user_access (arm64 and riscv only)
=======================================
Controls user space access for reading perf event counters. When set to 1,
user space can read performance monitor counter registers directly.
Controls user space access for reading perf event counters.
arm64
=====
The default value is 0 (access disabled).
When set to 1, user space can read performance monitor counter registers
directly.
See Documentation/arch/arm64/perf.rst for more information.
riscv
=====
When set to 0, user space access is disabled.
The default value is 1, user space can read performance monitor counter
registers through perf, any direct access without perf intervention will trigger
an illegal instruction.
When set to 2, which enables legacy mode (user space has direct access to cycle
and insret CSRs only). Note that this legacy value is deprecated and will be
removed once all user space applications are fixed.
Note that the time CSR is always directly accessible to all modes.
pid_max
=======