iommu/arm-smmu-v3: Add a type for the STE
Instead of passing a naked __le16 * around to represent a STE wrap it in a "struct arm_smmu_ste" with an array of the correct size. This makes it much clearer which functions will comprise the "STE API". Reviewed-by: Moritz Fischer <mdf@kernel.org> Reviewed-by: Michael Shavit <mshavit@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Jason Gunthorpe
Will Deacon
parent
b41932f544
commit
57b8904887
@ -1252,7 +1252,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
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}
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static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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__le64 *dst)
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struct arm_smmu_ste *dst)
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{
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/*
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* This is hideously complicated, but we only really care about
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@ -1270,7 +1270,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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* 2. Write everything apart from dword 0, sync, write dword 0, sync
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* 3. Update Config, sync
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*/
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u64 val = le64_to_cpu(dst[0]);
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u64 val = le64_to_cpu(dst->data[0]);
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bool ste_live = false;
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struct arm_smmu_device *smmu = NULL;
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struct arm_smmu_ctx_desc_cfg *cd_table = NULL;
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@ -1328,10 +1328,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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else
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
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dst[0] = cpu_to_le64(val);
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dst[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
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dst->data[0] = cpu_to_le64(val);
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dst->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
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STRTAB_STE_1_SHCFG_INCOMING));
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dst[2] = 0; /* Nuke the VMID */
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dst->data[2] = 0; /* Nuke the VMID */
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/*
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* The SMMU can perform negative caching, so we must sync
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* the STE regardless of whether the old value was live.
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@ -1346,7 +1346,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1;
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BUG_ON(ste_live);
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dst[1] = cpu_to_le64(
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dst->data[1] = cpu_to_le64(
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FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
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FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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@ -1355,7 +1355,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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if (smmu->features & ARM_SMMU_FEAT_STALLS &&
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!master->stall_enabled)
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dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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dst->data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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val |= (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |
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@ -1365,7 +1365,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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if (s2_cfg) {
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BUG_ON(ste_live);
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dst[2] = cpu_to_le64(
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dst->data[2] = cpu_to_le64(
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FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) |
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FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) |
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#ifdef __BIG_ENDIAN
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@ -1374,18 +1374,18 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
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STRTAB_STE_2_S2R);
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dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
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dst->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
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}
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if (master->ats_enabled)
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dst[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,
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dst->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,
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STRTAB_STE_1_EATS_TRANS));
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arm_smmu_sync_ste_for_sid(smmu, sid);
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/* See comment in arm_smmu_write_ctx_desc() */
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WRITE_ONCE(dst[0], cpu_to_le64(val));
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WRITE_ONCE(dst->data[0], cpu_to_le64(val));
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arm_smmu_sync_ste_for_sid(smmu, sid);
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/* It's likely that we'll want to use the new STE soon */
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@ -1393,7 +1393,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
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}
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static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool force)
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static void arm_smmu_init_bypass_stes(struct arm_smmu_ste *strtab,
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unsigned int nent, bool force)
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{
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unsigned int i;
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u64 val = STRTAB_STE_0_V;
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@ -1404,11 +1405,11 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool fo
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
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for (i = 0; i < nent; ++i) {
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strtab[0] = cpu_to_le64(val);
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strtab[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
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STRTAB_STE_1_SHCFG_INCOMING));
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strtab[2] = 0;
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strtab += STRTAB_STE_DWORDS;
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strtab->data[0] = cpu_to_le64(val);
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strtab->data[1] = cpu_to_le64(FIELD_PREP(
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STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));
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strtab->data[2] = 0;
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strtab++;
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}
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}
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@ -2212,26 +2213,23 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
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return 0;
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}
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static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
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static struct arm_smmu_ste *
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arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
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{
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__le64 *step;
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struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
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if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
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struct arm_smmu_strtab_l1_desc *l1_desc;
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int idx;
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unsigned int idx1, idx2;
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/* Two-level walk */
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idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
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l1_desc = &cfg->l1_desc[idx];
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idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS;
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step = &l1_desc->l2ptr[idx];
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idx1 = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
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idx2 = sid & ((1 << STRTAB_SPLIT) - 1);
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return &cfg->l1_desc[idx1].l2ptr[idx2];
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} else {
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/* Simple linear lookup */
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step = &cfg->strtab[sid * STRTAB_STE_DWORDS];
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return (struct arm_smmu_ste *)&cfg
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->strtab[sid * STRTAB_STE_DWORDS];
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}
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return step;
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}
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static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
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@ -2241,7 +2239,8 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
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for (i = 0; i < master->num_streams; ++i) {
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u32 sid = master->streams[i].id;
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__le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
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struct arm_smmu_ste *step =
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arm_smmu_get_step_for_sid(smmu, sid);
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/* Bridged PCI devices may end up with duplicated IDs */
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for (j = 0; j < i; j++)
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@ -3772,7 +3771,7 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu)
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iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list);
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list_for_each_entry(e, &rmr_list, list) {
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__le64 *step;
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struct arm_smmu_ste *step;
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struct iommu_iort_rmr_data *rmr;
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int ret, i;
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@ -206,6 +206,11 @@
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#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
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#define STRTAB_STE_DWORDS 8
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struct arm_smmu_ste {
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__le64 data[STRTAB_STE_DWORDS];
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};
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#define STRTAB_STE_0_V (1UL << 0)
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#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
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#define STRTAB_STE_0_CFG_ABORT 0
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@ -571,7 +576,7 @@ struct arm_smmu_priq {
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struct arm_smmu_strtab_l1_desc {
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u8 span;
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__le64 *l2ptr;
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struct arm_smmu_ste *l2ptr;
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dma_addr_t l2ptr_dma;
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};
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