iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'macb-partial-store-and-forward'

Browse Source 
Pranavi Somisetty says:

====================
Add support for partial store and forward

Add support for partial store and forward mode in Cadence MACB.

Link for v1:
https://lore.kernel.org/all/20221213121245.13981-1-pranavi.somisetty@amd.com/

Changes v2:
1. Removed all the changes related to validating FCS when Rx checksum
offload is disabled.
2. Instead of using a platform dependent number (0xFFF) for the reset
value of rx watermark, derive it from designcfg_debug2 register.
3. Added a check to see if partial s/f is supported, by reading the
designcfg_debug6 register.
4. Added devicetree bindings for "rx-watermark" property.
Link for v2:
https://lore.kernel.org/all/20230511071214.18611-1-pranavi.somisetty@amd.com/

Changes v3:
1. Fixed DT schema error: "scalar properties shouldn't have array keywords"
2. Modified description of rx-watermark in to include units of the watermark value
3. Modified the DT property name corresponding to rx_watermark in pbuf_rxcutthru to
"cdns,rx-watermark".
4. Followed reverse christmas tree pattern in declaring variables.
5. Return -EINVAL when an invalid watermark value is set.
6. Removed netdev_info when partial store and forward is not enabled.
7. Validating the rx-watermark value in probe itself and only write to the register
in init.
8. Writing a reset value to the pbuf_cuthru register before disabing partial store
and forward is redundant. So removing it.
9. Removed the platform caps flag.
10. Instead of reading rx-watermark from DT in macb_configure_caps,
reading it in probe.
11. Changed Signed-Off-By and author names on the macb driver patch.
Link for v3:
https://lore.kernel.org/all/20230530095138.1302-1-pranavi.somisetty@amd.com/

Changes v4:
1. Modified description for "rx-watermark" property in the DT bindings.
2. Changed the width of the rx-watermark property to uint32.
3. Removed redundant code and unused variables.
4. When the rx-watermark value is invalid, instead of returning EINVAL,
do not enable partial store and forward.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2023-06-15 08:45:29 +01:00
commit 580b7fe5fc
3 changed files with 50 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/devicetree/bindings/net/cdns,macb.yaml
View File

@ -109,6 +109,16 @@ properties:
power-domains:
maxItems: 1
cdns,rx-watermark:
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the receive partial store and forward mode is activated,
the receiver will only begin to forward the packet to the external
AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
rx-watermark corresponds to the number of SRAM buffer locations,
that need to be filled, before the forwarding process is activated.
Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.
'#address-cells':
const: 1
@ -166,6 +176,7 @@ examples:
compatible = "cdns,macb";
reg = <0xfffc4000 0x4000>;
interrupts = <21>;
cdns,rx-watermark = <0x44>;
phy-mode = "rmii";
local-mac-address = [3a 0e 03 04 05 06];
clock-names = "pclk", "hclk", "tx_clk";

12
drivers/net/ethernet/cadence/macb.h
View File

@ -82,6 +82,7 @@
#define GEM_NCFGR 0x0004 /* Network Config */
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
#define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
#define GEM_JML 0x0048 /* Jumbo Max Length */
#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
#define GEM_HRB 0x0080 /* Hash Bottom */
@ -347,6 +348,10 @@
#define GEM_ADDR64_SIZE 1
/* Bitfields in PBUFRXCUT */
#define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */
#define GEM_ENCUTTHRU_SIZE 1
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
@ -513,6 +518,8 @@
#define GEM_TX_PKT_BUFF_OFFSET 21
#define GEM_TX_PKT_BUFF_SIZE 1
#define GEM_RX_PBUF_ADDR_OFFSET 22
#define GEM_RX_PBUF_ADDR_SIZE 4
/* Bitfields in DCFG5. */
#define GEM_TSU_OFFSET 8
@ -521,6 +528,8 @@
/* Bitfields in DCFG6. */
#define GEM_PBUF_LSO_OFFSET 27
#define GEM_PBUF_LSO_SIZE 1
#define GEM_PBUF_CUTTHRU_OFFSET 25
#define GEM_PBUF_CUTTHRU_SIZE 1
#define GEM_DAW64_OFFSET 23
#define GEM_DAW64_SIZE 1
@ -1290,6 +1299,9 @@ struct macb {
u32 wol;
/* holds value of rx watermark value for pbuf_rxcutthru register */
u32 rx_watermark;
struct macb_ptp_info *ptp_info; /* macb-ptp interface */
struct phy *sgmii_phy; /* for ZynqMP SGMII mode */

27
drivers/net/ethernet/cadence/macb_main.c
View File

@ -2635,6 +2635,9 @@ static void macb_reset_hw(struct macb *bp)
macb_writel(bp, TSR, -1);
macb_writel(bp, RSR, -1);
/* Disable RX partial store and forward and reset watermark value */
gem_writel(bp, PBUFRXCUT, 0);
/* Disable all interrupts */
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
queue_writel(queue, IDR, -1);
@ -2792,6 +2795,10 @@ static void macb_init_hw(struct macb *bp)
bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
macb_configure_dma(bp);
/* Enable RX partial store and forward and set watermark */
if (bp->rx_watermark)
gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
}
/* The hash address register is 64 bits long and takes up two
@ -4946,6 +4953,7 @@ static int macb_probe(struct platform_device *pdev)
phy_interface_t interface;
struct net_device *dev;
struct resource *regs;
u32 wtrmrk_rst_val;
void __iomem *mem;
struct macb *bp;
int err, val;
@ -5025,6 +5033,25 @@ static int macb_probe(struct platform_device *pdev)
bp->usrio = macb_config->usrio;
/* By default we set to partial store and forward mode for zynqmp.
* Disable if not set in devicetree.
*/
if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
err = of_property_read_u32(bp->pdev->dev.of_node,
"cdns,rx-watermark",
&bp->rx_watermark);
if (!err) {
/* Disable partial store and forward in case of error or
* invalid watermark value
*/
wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
dev_info(&bp->pdev->dev, "Invalid watermark value\n");
bp->rx_watermark = 0;
}
}
}
spin_lock_init(&bp->lock);
/* setup capabilities */