drm/i915: Disable atomics in L3 for gen9
Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as the machine stops responding milliseconds after receipt of the reset request [GDRT]. By disabling the cached atomics, the hang do not occur and we presume the GPU would reset normally for similar hangs. Sadly this is a shotgun approach, but since the impact is critical it is better to err on the safe side and work back from there. Reported-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Jason Ekstrand <jason@jlesktrand.net> Link: https://patchwork.freedesktop.org/patch/msgid/20210125220152.24070-1-chris@chris-wilson.co.uk Cc: stable@vger.kernel.org (cherry picked from commit b267c7ae0ad5b437b068f46919b17f85000154b4) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -1834,6 +1834,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_write_or(wal,
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GEN8_L3SQCREG4,
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GEN8_LQSC_FLUSH_COHERENT_LINES);
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/* Disable atomics in L3 to prevent unrecoverable hangs */
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wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
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GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
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wa_write_clr_set(wal, GEN8_L3SQCREG4,
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GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
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wa_write_clr_set(wal, GEN9_SCRATCH1,
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EVICTION_PERF_FIX_ENABLE, 0);
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}
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if (IS_HASWELL(i915)) {
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@ -8225,6 +8225,7 @@ enum {
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#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
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#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
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#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
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#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
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/* GEN8 chicken */
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#define HDC_CHICKEN0 _MMIO(0x7300)
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@ -12107,6 +12108,12 @@ enum skl_power_gate {
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#define __GEN11_VCS2_MOCS0 0x10000
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#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
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#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
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#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
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#define GEN9_SCRATCH1 _MMIO(0xb11c)
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#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
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#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
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#define PMFLUSHDONE_LNICRSDROP (1 << 20)
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#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
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