ASoC: mediatek: mt8186: support audsys clock control
Add mt8186 audio cg control. Audio clock gates are registered to CCF for reference count and clock parent management. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220523132858.22166-4-jiaxin.yu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jiaxin Yu
Mark Brown
parent
612c4695e3
commit
58949aa35c
150
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
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150
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
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// SPDX-License-Identifier: GPL-2.0
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//
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// mt8186-audsys-clk.h -- Mediatek 8186 audsys clock control
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include "mt8186-afe-common.h"
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#include "mt8186-audsys-clk.h"
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#include "mt8186-audsys-clkid.h"
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#include "mt8186-reg.h"
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struct afe_gate {
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int id;
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const char *name;
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const char *parent_name;
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int reg;
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u8 bit;
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const struct clk_ops *ops;
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unsigned long flags;
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u8 cg_flags;
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};
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#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.reg = _reg, \
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.bit = _bit, \
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.flags = _flags, \
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.cg_flags = _cgflags, \
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}
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#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
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GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
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CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
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#define GATE_AUD0(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
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#define GATE_AUD1(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
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#define GATE_AUD2(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
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static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
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/* AUD0 */
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GATE_AUD0(CLK_AUD_AFE, "aud_afe_clk", "top_audio", 2),
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GATE_AUD0(CLK_AUD_22M, "aud_apll22m_clk", "top_aud_engen1", 8),
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GATE_AUD0(CLK_AUD_24M, "aud_apll24m_clk", "top_aud_engen2", 9),
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GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner_clk", "top_aud_engen2", 18),
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GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner_clk", "top_aud_engen1", 19),
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GATE_AUD0(CLK_AUD_TDM, "aud_tdm_clk", "top_aud_1", 20),
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GATE_AUD0(CLK_AUD_ADC, "aud_adc_clk", "top_audio", 24),
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GATE_AUD0(CLK_AUD_DAC, "aud_dac_clk", "top_audio", 25),
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GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis_clk", "top_audio", 26),
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GATE_AUD0(CLK_AUD_TML, "aud_tml_clk", "top_audio", 27),
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GATE_AUD0(CLK_AUD_NLE, "aud_nle_clk", "top_audio", 28),
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/* AUD1 */
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GATE_AUD1(CLK_AUD_I2S1_BCLK, "aud_i2s1_bclk", "top_audio", 4),
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GATE_AUD1(CLK_AUD_I2S2_BCLK, "aud_i2s2_bclk", "top_audio", 5),
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GATE_AUD1(CLK_AUD_I2S3_BCLK, "aud_i2s3_bclk", "top_audio", 6),
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GATE_AUD1(CLK_AUD_I2S4_BCLK, "aud_i2s4_bclk", "top_audio", 7),
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GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "top_audio", 12),
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GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "top_audio", 13),
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GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "top_audio", 14),
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GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires_clk", "top_audio_h", 15),
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GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires_clk", "top_audio_h", 16),
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GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "top_audio_h", 17),
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GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_audio", 20),
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GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 21),
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GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "top_audio", 28),
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GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "top_audio", 29),
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GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "top_audio", 30),
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GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "top_audio_h", 31),
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/* AUD2 */
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GATE_AUD2(CLK_AUD_ETDM_IN1_BCLK, "aud_etdm_in1_bclk", "top_audio", 23),
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GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24),
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};
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int mt8186_audsys_clk_register(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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struct clk *clk;
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struct clk_lookup *cl;
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int i;
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afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
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sizeof(*afe_priv->lookup),
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GFP_KERNEL);
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if (!afe_priv->lookup)
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return -ENOMEM;
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for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
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const struct afe_gate *gate = &aud_clks[i];
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clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
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gate->flags, afe->base_addr + gate->reg,
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gate->bit, gate->cg_flags, NULL);
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if (IS_ERR(clk)) {
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dev_err(afe->dev, "Failed to register clk %s: %ld\n",
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gate->name, PTR_ERR(clk));
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continue;
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}
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/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
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cl = kzalloc(sizeof(*cl), GFP_KERNEL);
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if (!cl)
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return -ENOMEM;
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cl->clk = clk;
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cl->con_id = gate->name;
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cl->dev_id = dev_name(afe->dev);
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clkdev_add(cl);
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afe_priv->lookup[i] = cl;
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}
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return 0;
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}
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void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe)
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{
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struct mt8186_afe_private *afe_priv = afe->platform_priv;
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struct clk *clk;
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struct clk_lookup *cl;
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int i;
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if (!afe_priv)
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return;
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for (i = 0; i < CLK_AUD_NR_CLK; i++) {
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cl = afe_priv->lookup[i];
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if (!cl)
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continue;
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clk = cl->clk;
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clk_unregister_gate(clk);
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clkdev_drop(cl);
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}
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}
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15
sound/soc/mediatek/mt8186/mt8186-audsys-clk.h
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15
sound/soc/mediatek/mt8186/mt8186-audsys-clk.h
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/* SPDX-License-Identifier: GPL-2.0
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*
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* mt8186-audsys-clk.h -- Mediatek 8186 audsys clock definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Trevor Wu <trevor.wu@mediatek.com>
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*/
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#ifndef _MT8186_AUDSYS_CLK_H_
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#define _MT8186_AUDSYS_CLK_H_
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int mt8186_audsys_clk_register(struct mtk_base_afe *afe);
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void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe);
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#endif
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45
sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h
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sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h
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/* SPDX-License-Identifier: GPL-2.0
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*
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* mt8186-audsys-clkid.h -- Mediatek 8186 audsys clock id definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
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*/
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#ifndef _MT8186_AUDSYS_CLKID_H_
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#define _MT8186_AUDSYS_CLKID_H_
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enum{
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CLK_AUD_AFE,
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CLK_AUD_22M,
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CLK_AUD_24M,
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CLK_AUD_APLL2_TUNER,
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CLK_AUD_APLL_TUNER,
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CLK_AUD_TDM,
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CLK_AUD_ADC,
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CLK_AUD_DAC,
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CLK_AUD_DAC_PREDIS,
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CLK_AUD_TML,
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CLK_AUD_NLE,
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CLK_AUD_I2S1_BCLK,
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CLK_AUD_I2S2_BCLK,
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CLK_AUD_I2S3_BCLK,
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CLK_AUD_I2S4_BCLK,
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CLK_AUD_CONNSYS_I2S_ASRC,
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CLK_AUD_GENERAL1_ASRC,
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CLK_AUD_GENERAL2_ASRC,
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CLK_AUD_DAC_HIRES,
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CLK_AUD_ADC_HIRES,
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CLK_AUD_ADC_HIRES_TML,
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CLK_AUD_ADDA6_ADC,
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CLK_AUD_ADDA6_ADC_HIRES,
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CLK_AUD_3RD_DAC,
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CLK_AUD_3RD_DAC_PREDIS,
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CLK_AUD_3RD_DAC_TML,
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CLK_AUD_3RD_DAC_HIRES,
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CLK_AUD_ETDM_IN1_BCLK,
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CLK_AUD_ETDM_OUT1_BCLK,
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CLK_AUD_NR_CLK,
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};
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#endif
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