Merge tag 'amd-drm-fixes-5.14-2021-08-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.14-2021-08-25: amdgpu: - Fix for pinning display buffers multiple times - Fix delayed work handling for GFXOFF - Fix build when CONFIG_SUSPEND is not set Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210826032658.4068-1-alexander.deucher@amd.com
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589744dbdd
@ -1040,7 +1040,7 @@ void amdgpu_acpi_detect(void)
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*/
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bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)
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{
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#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_PM_SLEEP)
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#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_SUSPEND)
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if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
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if (adev->flags & AMD_IS_APU)
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return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;
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@ -2777,12 +2777,11 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
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mutex_lock(&adev->gfx.gfx_off_mutex);
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if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
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WARN_ON_ONCE(adev->gfx.gfx_off_state);
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WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
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if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
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adev->gfx.gfx_off_state = true;
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}
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mutex_unlock(&adev->gfx.gfx_off_mutex);
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}
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/**
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@ -563,24 +563,38 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
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mutex_lock(&adev->gfx.gfx_off_mutex);
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if (!enable)
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adev->gfx.gfx_off_req_count++;
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else if (adev->gfx.gfx_off_req_count > 0)
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if (enable) {
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/* If the count is already 0, it means there's an imbalance bug somewhere.
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* Note that the bug may be in a different caller than the one which triggers the
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* WARN_ON_ONCE.
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*/
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if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
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goto unlock;
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adev->gfx.gfx_off_req_count--;
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if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
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if (adev->gfx.gfx_off_req_count == 0 && !adev->gfx.gfx_off_state)
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schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
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} else if (!enable && adev->gfx.gfx_off_state) {
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if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
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} else {
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if (adev->gfx.gfx_off_req_count == 0) {
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cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
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if (adev->gfx.gfx_off_state &&
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!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
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adev->gfx.gfx_off_state = false;
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if (adev->gfx.funcs->init_spm_golden) {
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dev_dbg(adev->dev, "GFXOFF is disabled, re-init SPM golden settings\n");
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dev_dbg(adev->dev,
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"GFXOFF is disabled, re-init SPM golden settings\n");
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amdgpu_gfx_init_spm_golden(adev);
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}
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}
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}
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adev->gfx.gfx_off_req_count++;
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}
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unlock:
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mutex_unlock(&adev->gfx.gfx_off_mutex);
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}
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@ -920,11 +920,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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return -EINVAL;
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}
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/* This assumes only APU display buffers are pinned with (VRAM|GTT).
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* See function amdgpu_display_supported_domains()
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*/
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domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
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if (bo->tbo.pin_count) {
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uint32_t mem_type = bo->tbo.resource->mem_type;
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uint32_t mem_flags = bo->tbo.resource->placement;
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@ -949,6 +944,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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return 0;
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}
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/* This assumes only APU display buffers are pinned with (VRAM|GTT).
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* See function amdgpu_display_supported_domains()
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*/
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domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
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if (bo->tbo.base.import_attach)
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dma_buf_pin(bo->tbo.base.import_attach);
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