PCI: Move pci_configure_slot() to drivers/pci/probe.c
Move pci_configure_slot() and related functions from drivers/pci/hotplug/pcihp_slot to drivers/pci/probe.c. This is to prepare for doing device configuration during the normal enumeration process instead of just after hot-add. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Bjorn Helgaas
parent
5e3d234456
commit
589fcc2307
@ -24,7 +24,7 @@ obj-$(CONFIG_HOTPLUG_PCI_S390) += s390_pci_hpc.o
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obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o
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pci_hotplug-objs := pci_hotplug_core.o pcihp_slot.o
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pci_hotplug-objs := pci_hotplug_core.o
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ifdef CONFIG_HOTPLUG_PCI_CPCI
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pci_hotplug-objs += cpci_hotplug_core.o \
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@ -1,176 +0,0 @@
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/*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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* (c) Copyright 2009 Hewlett-Packard Development Company, L.P.
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include <linux/export.h>
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#include <linux/pci_hotplug.h>
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static struct hpp_type0 pci_default_type0 = {
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.revision = 1,
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.cache_line_size = 8,
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.latency_timer = 0x40,
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.enable_serr = 0,
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.enable_perr = 0,
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};
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static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
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{
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u16 pci_cmd, pci_bctl;
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if (!hpp) {
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/*
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* Perhaps we *should* use default settings for PCIe, but
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* pciehp didn't, so we won't either.
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*/
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if (pci_is_pcie(dev))
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return;
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hpp = &pci_default_type0;
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}
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if (hpp->revision > 1) {
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dev_warn(&dev->dev,
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"PCI settings rev %d not supported; using defaults\n",
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hpp->revision);
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hpp = &pci_default_type0;
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}
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
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pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
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if (hpp->enable_serr)
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pci_cmd |= PCI_COMMAND_SERR;
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else
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pci_cmd &= ~PCI_COMMAND_SERR;
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if (hpp->enable_perr)
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pci_cmd |= PCI_COMMAND_PARITY;
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else
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pci_cmd &= ~PCI_COMMAND_PARITY;
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pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
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/* Program bridge control value */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
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hpp->latency_timer);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
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if (hpp->enable_serr)
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pci_bctl |= PCI_BRIDGE_CTL_SERR;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
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if (hpp->enable_perr)
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pci_bctl |= PCI_BRIDGE_CTL_PARITY;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
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}
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}
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static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
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{
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if (hpp)
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dev_warn(&dev->dev, "PCI-X settings not supported\n");
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}
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static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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{
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int pos;
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u32 reg32;
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if (!hpp)
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return;
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if (hpp->revision > 1) {
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dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
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hpp->revision);
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return;
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}
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/* Initialize Device Control Register */
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pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
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~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
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/* Initialize Link Control Register */
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if (dev->subordinate)
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pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
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~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
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/* Find Advanced Error Reporting Enhanced Capability */
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (!pos)
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return;
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/* Initialize Uncorrectable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
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reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
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/* Initialize Uncorrectable Error Severity Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
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reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
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/* Initialize Correctable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
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reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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/*
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* FIXME: The following two registers are not supported yet.
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*
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* o Secondary Uncorrectable Error Severity Register
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* o Secondary Uncorrectable Error Mask Register
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*/
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}
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void pci_configure_slot(struct pci_dev *dev)
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{
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struct pci_dev *cdev;
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struct hotplug_params hpp;
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if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
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(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
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return;
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pcie_bus_configure_settings(dev->bus);
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memset(&hpp, 0, sizeof(hpp));
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pci_get_hp_params(dev, &hpp);
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program_hpp_type2(dev, hpp.t2);
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program_hpp_type1(dev, hpp.t1);
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program_hpp_type0(dev, hpp.t0);
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if (dev->subordinate) {
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list_for_each_entry(cdev, &dev->subordinate->devices,
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bus_list)
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pci_configure_slot(cdev);
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}
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}
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EXPORT_SYMBOL_GPL(pci_configure_slot);
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@ -6,6 +6,7 @@
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_hotplug.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/cpumask.h>
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@ -1236,6 +1237,155 @@ int pci_setup_device(struct pci_dev *dev)
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return 0;
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}
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static struct hpp_type0 pci_default_type0 = {
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.revision = 1,
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.cache_line_size = 8,
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.latency_timer = 0x40,
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.enable_serr = 0,
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.enable_perr = 0,
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};
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static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
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{
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u16 pci_cmd, pci_bctl;
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if (!hpp) {
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/*
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* Perhaps we *should* use default settings for PCIe, but
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* pciehp didn't, so we won't either.
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*/
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if (pci_is_pcie(dev))
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return;
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hpp = &pci_default_type0;
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}
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if (hpp->revision > 1) {
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dev_warn(&dev->dev,
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"PCI settings rev %d not supported; using defaults\n",
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hpp->revision);
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hpp = &pci_default_type0;
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}
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
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pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
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if (hpp->enable_serr)
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pci_cmd |= PCI_COMMAND_SERR;
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else
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pci_cmd &= ~PCI_COMMAND_SERR;
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if (hpp->enable_perr)
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pci_cmd |= PCI_COMMAND_PARITY;
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else
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pci_cmd &= ~PCI_COMMAND_PARITY;
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pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
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/* Program bridge control value */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
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hpp->latency_timer);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
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if (hpp->enable_serr)
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pci_bctl |= PCI_BRIDGE_CTL_SERR;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
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if (hpp->enable_perr)
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pci_bctl |= PCI_BRIDGE_CTL_PARITY;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
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}
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}
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static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
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{
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if (hpp)
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dev_warn(&dev->dev, "PCI-X settings not supported\n");
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}
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static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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{
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int pos;
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u32 reg32;
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if (!hpp)
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return;
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if (hpp->revision > 1) {
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dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
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hpp->revision);
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return;
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}
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/* Initialize Device Control Register */
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pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
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~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
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/* Initialize Link Control Register */
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if (dev->subordinate)
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pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
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~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
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/* Find Advanced Error Reporting Enhanced Capability */
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (!pos)
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return;
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/* Initialize Uncorrectable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
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reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
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/* Initialize Uncorrectable Error Severity Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
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reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
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/* Initialize Correctable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
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reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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/*
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* FIXME: The following two registers are not supported yet.
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*
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* o Secondary Uncorrectable Error Severity Register
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* o Secondary Uncorrectable Error Mask Register
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*/
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}
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void pci_configure_slot(struct pci_dev *dev)
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{
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struct pci_dev *cdev;
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struct hotplug_params hpp;
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int ret;
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if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
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(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
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return;
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pcie_bus_configure_settings(dev->bus);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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program_hpp_type2(dev, hpp.t2);
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program_hpp_type1(dev, hpp.t1);
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program_hpp_type0(dev, hpp.t0);
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if (dev->subordinate) {
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list_for_each_entry(cdev, &dev->subordinate->devices,
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bus_list)
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pci_configure_slot(cdev);
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}
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}
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EXPORT_SYMBOL_GPL(pci_configure_slot);
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static void pci_release_capabilities(struct pci_dev *dev)
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{
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pci_vpd_release(dev);
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