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drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write for a650

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downstream msm-5.14 kernel added a write to this register, so match that.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210608172808.11803-4-jonathan@marek.ca
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jonathan Marek 2021-06-08 13:27:46 -04:00 committed by Rob Clark
parent 64245fc551
commit 58e933e3f0
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
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@ -751,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
int ret;
u32 chipid;
if (adreno_is_a650(adreno_gpu))
if (adreno_is_a650(adreno_gpu)) {
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
}
if (state == GMU_WARM_BOOT) {
ret = a6xx_rpmh_start(gmu);