x86/cpu: Remove pointless evaluation of x86_coreid_bits
cpuinfo_x86::x86_coreid_bits is only used by the AMD numa topology code. No point in evaluating it on non AMD systems. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.687588373@linutronix.de
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@ -314,19 +314,6 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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setup_clear_cpu_cap(X86_FEATURE_PGE);
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}
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if (c->cpuid_level >= 0x00000001) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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/*
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* If HTT (EDX[28]) is set EBX[16:23] contain the number of
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* apicids which are reserved per package. Store the resulting
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* shift value for the package management code.
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*/
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if (edx & (1U << 28))
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c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
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}
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check_memory_type_self_snoop_errata(c);
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/*
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@ -65,20 +65,6 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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}
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if (c->cpuid_level >= 0x00000001) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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/*
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* If HTT (EDX[28]) is set EBX[16:23] contain the number of
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* apicids which are reserved per package. Store the resulting
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* shift value for the package management code.
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*/
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if (edx & (1U << 28))
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c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
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}
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}
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static void init_zhaoxin(struct cpuinfo_x86 *c)
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