drm/amd/display: Enable Panel Replay for static screen use case
[Why] Enable the Panel Replay if eDP panel and ASIC support. (prioritize Panel Replay over PSR) [How] - Setup the Panel Replay config during the device init (prioritize Panel Replay over PSR). - Separate the Replay init function into two functions amdgpu_dm_link_setup_replay() and amdgpu_dm_set_replay_caps() to fix the issue in the earlier commit that cause PSR and Replay enabled at the same time. Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom Chung
Alex Deucher
parent
12f72a1599
commit
5950efe25e
@ -67,6 +67,7 @@
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#include "amdgpu_dm_debugfs.h"
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#endif
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#include "amdgpu_dm_psr.h"
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#include "amdgpu_dm_replay.h"
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#include "ivsrcid/ivsrcid_vislands30.h"
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@ -4394,6 +4395,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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enum dc_connection_type new_connection_type = dc_connection_none;
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const struct dc_plane_cap *plane;
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bool psr_feature_enabled = false;
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bool replay_feature_enabled = false;
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int max_overlay = dm->dc->caps.max_slave_planes;
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dm->display_indexes_num = dm->dc->caps.max_streams;
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@ -4505,6 +4507,23 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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}
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}
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/* Determine whether to enable Replay support by default. */
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if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
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switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
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case IP_VERSION(3, 1, 4):
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case IP_VERSION(3, 1, 5):
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case IP_VERSION(3, 1, 6):
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case IP_VERSION(3, 2, 0):
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case IP_VERSION(3, 2, 1):
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case IP_VERSION(3, 5, 0):
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replay_feature_enabled = true;
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break;
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default:
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replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
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break;
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}
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}
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/* loops over all connectors on the board */
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for (i = 0; i < link_cnt; i++) {
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struct dc_link *link = NULL;
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@ -4573,6 +4592,11 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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amdgpu_dm_update_connector_after_detect(aconnector);
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setup_backlight_device(dm, aconnector);
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/* Disable PSR if Replay can be enabled */
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if (replay_feature_enabled)
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if (amdgpu_dm_set_replay_caps(link, aconnector))
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psr_feature_enabled = false;
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if (psr_feature_enabled)
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amdgpu_dm_set_psr_caps(link);
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@ -8522,10 +8546,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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dm_update_pflip_irq_state(drm_to_adev(dev),
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acrtc_attach);
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if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
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acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
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!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
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amdgpu_dm_link_setup_psr(acrtc_state->stream);
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
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!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
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struct amdgpu_dm_connector *aconn =
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(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
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amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
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} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
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!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
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amdgpu_dm_link_setup_psr(acrtc_state->stream);
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}
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}
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/* Decrement skip count when PSR is enabled and we're doing fast updates. */
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if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
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@ -8814,11 +8845,12 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
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}
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} /* for_each_crtc_in_state() */
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/* if there mode set or reset, disable eDP PSR */
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/* if there mode set or reset, disable eDP PSR, Replay */
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if (mode_set_reset_required) {
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if (dm->vblank_control_workqueue)
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flush_workqueue(dm->vblank_control_workqueue);
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amdgpu_dm_replay_disable_all(dm);
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amdgpu_dm_psr_disable_all(dm);
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}
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@ -29,6 +29,7 @@
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#include "dc.h"
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#include "amdgpu.h"
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#include "amdgpu_dm_psr.h"
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#include "amdgpu_dm_replay.h"
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#include "amdgpu_dm_crtc.h"
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#include "amdgpu_dm_plane.h"
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#include "amdgpu_dm_trace.h"
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@ -95,6 +96,48 @@ bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
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dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
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}
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/**
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* The DRM vblank counter enable/disable action is used as the trigger to enable
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* or disable various panel self-refresh features:
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*
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* Panel Replay and PSR SU
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* - Enable when:
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* - vblank counter is disabled
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* - entry is allowed: usermode demonstrates an adequate number of fast
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* commits)
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* - CRC capture window isn't active
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* - Keep enabled even when vblank counter gets enabled
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*
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* PSR1
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* - Enable condition same as above
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* - Disable when vblank counter is enabled
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*/
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static void amdgpu_dm_crtc_set_panel_sr_feature(
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struct vblank_control_work *vblank_work,
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bool vblank_enabled, bool allow_sr_entry)
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{
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struct dc_link *link = vblank_work->stream->link;
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bool is_sr_active = (link->replay_settings.replay_allow_active ||
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link->psr_settings.psr_allow_active);
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bool is_crc_window_active = false;
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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is_crc_window_active =
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amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
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#endif
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if (link->replay_settings.replay_feature_enabled &&
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allow_sr_entry && !is_sr_active && !is_crc_window_active) {
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amdgpu_dm_replay_enable(vblank_work->stream, true);
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} else if (vblank_enabled) {
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if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
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amdgpu_dm_psr_disable(vblank_work->stream);
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} else if (link->psr_settings.psr_feature_enabled &&
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allow_sr_entry && !is_sr_active && !is_crc_window_active) {
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amdgpu_dm_psr_enable(vblank_work->stream);
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}
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}
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static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
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{
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struct vblank_control_work *vblank_work =
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@ -123,18 +166,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
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* fill_dc_dirty_rects().
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*/
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if (vblank_work->stream && vblank_work->stream->link) {
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if (vblank_work->enable) {
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if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
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vblank_work->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_disable(vblank_work->stream);
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} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
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!vblank_work->stream->link->psr_settings.psr_allow_active &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
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#endif
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vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
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amdgpu_dm_psr_enable(vblank_work->stream);
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}
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amdgpu_dm_crtc_set_panel_sr_feature(
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vblank_work, vblank_work->enable,
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vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
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vblank_work->stream->link->replay_settings.replay_feature_enabled);
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}
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mutex_unlock(&dm->dc_lock);
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@ -60,21 +60,26 @@ static bool link_supports_replay(struct dc_link *link, struct amdgpu_dm_connecto
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if (!as_caps->dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT)
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return false;
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// Sink shall populate line deviation information
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if (dpcd_caps->pr_info.pixel_deviation_per_line == 0 ||
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dpcd_caps->pr_info.max_deviation_line == 0)
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return false;
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return true;
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}
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/*
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* amdgpu_dm_setup_replay() - setup replay configuration
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* amdgpu_dm_set_replay_caps() - setup Replay capabilities
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* @link: link
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* @aconnector: aconnector
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*
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*/
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bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
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bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
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{
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struct replay_config pr_config;
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struct replay_config pr_config = { 0 };
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union replay_debug_flags *debug_flags = NULL;
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// For eDP, if Replay is supported, return true to skip checks
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// If Replay is already set to support, return true to skip checks
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if (link->replay_settings.config.replay_supported)
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return true;
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@ -87,27 +92,50 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *ac
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if (!link_supports_replay(link, aconnector))
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return false;
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// Mark Replay is supported in link and update related attributes
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// Mark Replay is supported in pr_config
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pr_config.replay_supported = true;
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pr_config.replay_power_opt_supported = 0;
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pr_config.replay_enable_option |= pr_enable_option_static_screen;
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pr_config.replay_timing_sync_supported = aconnector->max_vfreq >= 2 * aconnector->min_vfreq;
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if (!pr_config.replay_timing_sync_supported)
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pr_config.replay_enable_option &= ~pr_enable_option_general_ui;
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debug_flags = (union replay_debug_flags *)&pr_config.debug_flags;
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debug_flags->u32All = 0;
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debug_flags->bitfields.visual_confirm =
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link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
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link->replay_settings.replay_feature_enabled = true;
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init_replay_config(link, &pr_config);
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return true;
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}
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/*
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* amdgpu_dm_link_setup_replay() - configure replay link
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* @link: link
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* @aconnector: aconnector
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*
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*/
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bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
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{
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struct replay_config *pr_config;
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if (link == NULL || aconnector == NULL)
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return false;
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pr_config = &link->replay_settings.config;
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if (!pr_config->replay_supported)
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return false;
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pr_config->replay_power_opt_supported = 0x11;
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pr_config->replay_smu_opt_supported = false;
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pr_config->replay_enable_option |= pr_enable_option_static_screen;
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pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq;
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pr_config->replay_timing_sync_supported = false;
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if (!pr_config->replay_timing_sync_supported)
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pr_config->replay_enable_option &= ~pr_enable_option_general_ui;
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link->replay_settings.replay_feature_enabled = true;
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return true;
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}
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/*
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* amdgpu_dm_replay_enable() - enable replay f/w
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@ -117,51 +145,23 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *ac
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*/
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bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)
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{
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uint64_t state;
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unsigned int retry_count;
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bool replay_active = true;
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const unsigned int max_retry = 1000;
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bool force_static = true;
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struct dc_link *link = NULL;
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if (stream == NULL)
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return false;
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link = stream->link;
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if (link == NULL)
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return false;
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link->dc->link_srv->edp_setup_replay(link, stream);
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link->dc->link_srv->edp_set_replay_allow_active(link, NULL, false, false, NULL);
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link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, false, true, NULL);
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if (wait == true) {
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for (retry_count = 0; retry_count <= max_retry; retry_count++) {
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dc_link_get_replay_state(link, &state);
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if (replay_active) {
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if (state != REPLAY_STATE_0 &&
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(!force_static || state == REPLAY_STATE_3))
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break;
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} else {
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if (state == REPLAY_STATE_0)
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break;
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}
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udelay(500);
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}
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/* assert if max retry hit */
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if (retry_count >= max_retry)
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ASSERT(0);
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} else {
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/* To-do: Add trace log */
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if (link) {
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link->dc->link_srv->edp_setup_replay(link, stream);
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link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total);
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DRM_DEBUG_DRIVER("Enabling replay...\n");
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link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);
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return true;
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}
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return true;
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return false;
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}
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/*
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@ -172,12 +172,31 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)
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*/
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bool amdgpu_dm_replay_disable(struct dc_stream_state *stream)
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{
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bool replay_active = false;
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struct dc_link *link = NULL;
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if (stream->link) {
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if (stream == NULL)
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return false;
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link = stream->link;
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if (link) {
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DRM_DEBUG_DRIVER("Disabling replay...\n");
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stream->link->dc->link_srv->edp_set_replay_allow_active(stream->link, NULL, false, false, NULL);
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link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL);
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return true;
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}
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return false;
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}
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/*
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* amdgpu_dm_replay_disable_all() - disable replay f/w
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* if replay is enabled on any stream
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*
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* Return: true if success
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*/
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bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm)
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{
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DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n");
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return dc_set_replay_allow_active(dm->dc, false);
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}
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@ -40,7 +40,9 @@ enum replay_enable_option {
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bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable);
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bool amdgpu_dm_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
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bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
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bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
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bool amdgpu_dm_replay_disable(struct dc_stream_state *stream);
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bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm);
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#endif /* AMDGPU_DM_AMDGPU_DM_REPLAY_H_ */
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@ -244,6 +244,7 @@ enum DC_FEATURE_MASK {
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DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
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DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
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DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
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DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4
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};
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enum DC_DEBUG_MASK {
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