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drm/amd/pm: raise the deep sleep clock threshold for smu 13.0.6

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The DS clock may exceed the limit as sclk dfll divider is 16
to target freq.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma 2023-11-07 18:10:29 +08:00 committed by Alex Deucher
parent 4eaa007c73
commit 5a2913aada
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
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@ -94,7 +94,7 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
#define LINK_SPEED_MAX 4
#define SMU_13_0_6_DSCLK_THRESHOLD 100
#define SMU_13_0_6_DSCLK_THRESHOLD 140
#define MCA_BANK_IPID(_ip, _hwid, _type) \
[AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }