drm/amd/pm: raise the deep sleep clock threshold for smu 13.0.6
The DS clock may exceed the limit as sclk dfll divider is 16 to target freq. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -94,7 +94,7 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
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#define LINK_SPEED_MAX 4
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#define SMU_13_0_6_DSCLK_THRESHOLD 100
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#define SMU_13_0_6_DSCLK_THRESHOLD 140
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#define MCA_BANK_IPID(_ip, _hwid, _type) \
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[AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
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