[PATCH] m68knommu: memory register defines for 520x ColdFire CPU's
Here is a small patch to automatically detect the DRAM size on m520x. It was generated against 2.6.17-uc0, and tested on an Intec 5208 dev board. (This part of the patch if the memory register defines for the 520x ColdFire CPU family - Greg). Signed-off-by: Michael Broughton <mbobowik@telusplanet.net> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -31,6 +31,16 @@
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
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#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
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#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
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#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
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#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
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#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
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#define MCF_GPIO_PAR_UART (0xA4036)
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#define MCF_GPIO_PAR_UART (0xA4036)
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#define MCF_GPIO_PAR_FECI2C (0xA4033)
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#define MCF_GPIO_PAR_FECI2C (0xA4033)
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#define ICR_INTRCONF 0x05
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#define ICR_INTRCONF 0x05
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#define MCFPIT_IMR MCFINTC_IMRL
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#define MCFPIT_IMR MCFINTC_IMRL
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#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
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#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
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/****************************************************************************/
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/****************************************************************************/
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#endif /* m520xsim_h */
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#endif /* m520xsim_h */
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